JP2564550B2 - Integrated exchange - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to an integrated exchange that integrates the functions of circuit switching and packet switching.

[Prior art]

The conventional device configurations of the switch having only the circuit switching function and the switch having only the packet switching function realize each switching function by the processor dedicated to the switching. Various methods have been devised for the purpose of realizing the functions of the exchange, and the methods for realizing the functions have achieved their own development.

[Problems to be solved by the invention]

Therefore, it is often difficult to share the processor, peripherals, software and its development environment, etc. with the currently widespread computer, and it is not possible to fully utilize the technologies and assets accumulated in both fields. There was a shortcoming that it was not. In particular, in a switching system that integrates the functions of circuit switching and packet switching, this drawback has a greater influence as the software scale increases.

An object of the present invention is to configure various exchange terminal interfaces on a bus for connecting a peripheral device of a computer without changing the hardware and basic software of the computer when configuring an exchange that integrates circuit switching and packet switching with a computer. By connecting modules having functions and trunk line interface functions and executing an exchange processing program in the computer, the technologies and assets accumulated in the fields of exchanges and computers are utilized to develop and operate hardware and software, It is to provide an integrated exchange that can reduce costs such as maintenance and management and improve flexibility in adding functions.

[Means for solving problems]

To achieve the above object, the present invention provides a single switching device having a circuit switching terminal interface function, a packet switching terminal interface function, and a trunk circuit interface function as a peripheral device having a direct memory access function on a peripheral device connecting bus of a computer. When connecting the modules or connecting the respective switching modules individually having the respective functions and executing the switching program for controlling the switching modules on the computer, only the communication data of the circuit switching is stored in the modules. After being turned back, the communication control information of the circuit switching is packetized in the switching module, and then is taken into the computer together with the data and the control information of the packet switching using the direct memory access function provided in the computer,
By doing so, integrated switching of circuit switching and packet switching is performed.

[Action]

Line / packet integrated switching is performed by executing software that controls the modules and realizes a switching function on the computer.

〔Example〕

FIG. 1 is an explanatory diagram showing the flow of information in each of the first and second embodiments of the present invention described below. In FIG. 1, only communication data for circuit switching is returned in a switching module attached to a computer, and other information is processed by the computer. When the communication data including the circuit switching is processed by a computer, the switching system can be realized based on the control disclosed in the specification of Japanese Patent Application No. 58-99239 "Digital Switching System".

First Embodiment FIG. 2 is a block diagram of the first embodiment of the present invention based on the information flow shown in FIG. This embodiment is an example in which a module having an integrated exchange function is added to a computer. The details will be described below with reference to the drawings.

In FIG. 2, 1 is an integrated switching module, 11 is an integrated switching module control unit (I-CTL), 12 is a circuit switching (hereinafter abbreviated as CS) functional block (CS-BL) including a call switch.
K), 13 is a packet switching (hereinafter abbreviated as PS) function block (PS-BLK), 14 is a relay function block (LN-BLK), 2 is a computer, 21 is a central processing unit (CPU), and 22 is main memory ( M
M), 23 is a direct memory access mechanism (DMA), 231
Is a peripheral device connection bus (I / O bus). I-CTL11 is
While controlling CS-BLK12, PS-BLK13, LN-BLK14, DM
It sends and receives the necessary information to and from MM22 in cooperation with A23, and CPU21
It enables integrated exchange processing. CS-BLK12, PS-BLK13,
The LN-BLK14 has interfaces with CS terminals, PS terminals, and trunk lines, respectively, and also performs processing such as conversion of control signals into packet form.

FIG. 3 is an explanatory diagram showing a schematic configuration of a program and a buffer in this embodiment. In FIG.
221 is an operating system (hereinafter abbreviated as OS), 222
Is an exchange program, 2221 is a control information buffer, 2222 is a packet buffer, 2223 is an input / output control program (hereinafter referred to as IO
2224 is a packet switching processing program, 2226 is a packet switching processing program, and 2227 is another processing program. The control information buffer 2221 is a buffer of information used by the firmware in the IOCS 2223 and the exchange module 1 for the purpose of controlling the exchange module 1 and the DMA 23.

In FIG. 3, various requests, reports, requests, etc. from the exchange module 1 for the exchange program 222 are realized by a combination of an interrupt for the OS 221 and information setting in the control information buffer 2221 or packet setting in the packet buffer 2222. To be done. Further, various controls, instructions, and the like from the exchange program 222 for the exchange module 1 are realized by a combination of an input / output control instruction and information setting in the control information buffer 2221 or packet setting in the packet buffer 2222.

In this embodiment, it is premised that the CS-BLK 12 has a function of packetizing the control signal for circuit switching and an opposite function in order to share the processing as much as possible.
Therefore, the packetized various signals for circuit switching and the packet for packet switching are processed in common by the program configuration shown in FIG. 3 until packet analysis, and the switching processing is performed according to each communication mode according to the analysis result. You can proceed. These packets may be transferred one by one, or may be transferred collectively. To prevent performance degradation due to interrupt analysis of OS221, Japanese Patent Application No. 62-011
As disclosed in the specification of the "Switch" 401, the method of collectively transferring a plurality of packets is excellent. In this case, details of the processing including usage of the control information buffer 2221 and details of the packet analysis method For example, Japanese Patent Application Sho 62-XXXXXX
It is disclosed in the specification of "Signal Processing Method" (filed on May 15, 1987). In the case of the method of transferring the packets one by one, the processing can be easily realized by simplifying the method disclosed in the above specification.

FIG. 4 is an outline of data packet processing at the time of outgoing connection as an example of packet switching processing in the configurations of FIGS. 2 and 3, and FIG. 5 is an example of circuit switching processing in the configurations of FIGS. 2 and 3. 6 is a flowchart showing an outline of processing up to setting of a connection path within the own station.

Hereinafter, description will be given with reference to the drawings. In the following description, the control information buffer 2221 and the packet buffer 2222 in the MM22 are not distinguished for simplicity. The hardware, firmware, OS 221, and exchange program 222 in the drawing are examples of processing sharing, and in this embodiment as well, there may be various implementations such as performing part of packet analysis by hardware.

In FIG. 4, the processing is shown corresponding to the related blocks in FIG. 2, and is executed in the following order.

Packets from PS terminals are sent by PS-BLK13 (for example)
Layer 2 communication procedure processing is performed. At the same time PS-BLK13
Reports to I-CTL11 that the packet has been received.

I-CTL11 activates DMA23 based on the report from PS-BLK13.

The DMA23 transfers the packet from the PS-BLK13 to the MM22.

I-CTL11 detects the end of DMA23 transfer and interrupts CPU21.

The CPU 21 activates the exchange program 222 after analyzing the cause of interruption by the OS 221.

The exchange program 222 processes the packet accommodated in the MM22, and sets the packet in the MM22 again for transmission.

At the same time, the exchange program 222 instructs the I-CTL 11 to activate the DMA 23 for transmitting the packet.

I-CTL11 is DMA2 based on the instruction from exchange program 222
Start 3

The DMA23 transfers the packet from the MM22 to the LN-BLK14.

The LN-BLK 14 executes the layer 2 communication procedure (for example) and transmits the packet to the partner station.

The exchange program 222 continues another exchange process unless there is an abnormal end report from the I-CTL 11.

In the above description, the packets are transferred one by one, but as described in the description of FIG. 3, in order to reduce the interrupt analysis overhead of OS221, for example, Japanese Patent Application No. 62-011401.
Multiple packets may be transferred together, as disclosed in the "Switch" specification. A detailed example of the transfer operation in this case is disclosed in the specification of Japanese Patent Application No. 62-XXXXXX "Signal Processing Method" (filed on May 15, 1987).

It is clear that the communication of the data packet at the time of outgoing / outgoing connection of the packet switching is continued by repeatedly performing the above processes 1 to 3. Regarding communication between PS terminals in the own station, LN-BLK14 in FIG. 4 may be read as PS-BLK13. Regarding the control packet in the packet switching, the processing regarding the related blocks in FIG. 2 is the same as that in FIG. 4, and only the processing in the switching program 222 is different.

In FIGS. 5 (a) and 5 (b), the processing is shown corresponding to the related blocks in FIG. 2, and is executed in the following order.

The CS-BLK 12 receives the calling / selection information from the terminal, converts it into a form suitable for subsequent handling (hereinafter referred to as a signal packet), and reports the reception of the information to the I-CTL 11.

The switching program 222 sets the path setting information in the MM22 in order to process the signal packet accommodated in the MM22 and form a circuit switching communication path.

The DMA 23 transfers the packet from the MM 22 to the I-CTL 11.

The I-CTL11 receives and analyzes the packet, drives the switch of the CS-BLK12 according to the content, detects the completion of the operation, and issues an end interrupt to the CPU21.

The CPU 21 activates the exchange program 222 after analyzing the cause of interruption by the OS 221.

The exchange program 222 sets the call information signal packet in the MM22, and instructs the I-CTL11 to activate the DMA23.

I-CTL11 is DMA2 based on the instruction from exchange program 222
Start 3

The DMA 23 transfers the signal packet from the MM 22 to the CS-BLK 12.

The CS-BLK 12 receives the signal packet, converts it into a signal format suitable for the terminal, and transmits it.

The above is the processing shown in FIG. 5 (a).

The CS-BLK12 receives the response information from the terminal, converts the information into a signal packet, and receives the information by I-
Report to CTL11.

Do the same as ~.

The exchange program 222 processes the signal packet accommodated in the MM22 and sets the communication enable information in the MM22.

Do the same as ~.

Communication is performed using the speech path formed by the switches in the CS-BLK12.

 The above is the processing shown in FIG. 5 (b).

Obviously, other processing in circuit switching can be realized in the same environment as that shown in the above description.

In the above description of the first embodiment, the number of the integrated exchange module 1 is one, but it is clear that the embodiment having a plurality of the modules can be easily configured by expanding the above description.

Second Embodiment FIG. 6 is a block diagram of the second embodiment of the present invention based on the information flow shown in FIG. In this embodiment, a computer is added with a module having a packet switching function, a module having a circuit switching function, and a trunk line module.

In FIG. 6, 3 is a CS module, 31 is a CS module control unit (CS-CTL), 32 is a CS function block (CS-BLK) including a call switch, 4 is a PS module, 41 is a PS module control unit (PS -CTL), 42 is PS function block (PS-BLK),
5 is a relay line module, 51 is a relay line module control unit (LN-CTL), 52 is a relay function block (LN-BLK), 53 is CS
Information path. Others are the same as those in FIG. CS-B
LK32, PS-BLK42, LN-BLK52 are basically the same as in Fig. 2, but they are not controlled by I-CTL11 but CS-CT, respectively.
It is controlled by L31, PS-CTL41, and LN-CTL51. CS-CT
The L31, PS-CTL41, and LN-CTL51 realize the CS, PS, and relay functions of the I-CTL11 function, respectively. The CS information path 53 is installed between the CS-BLK 32 and the LN-BLK 52 as a path used when transferring communication data during CS communication with a partner station. When transferring communication data during PS communication with the partner station, the second computer uses the MM22 to perform packet exchange processing, so a direct connection route such as the CS information path 53 is unnecessary, and I / O Information is transferred via the O bus 231.

The program and buffer configuration in this embodiment is basically the same as that shown in FIG. IOCS2223 in Figure 3
It suffices to have a function of controlling CS-CTL31, PS-CTL41, LN-CTL51 instead of I-CTL11, which can be easily realized by a known technique.

The schematic operation of this embodiment is basically the same as that shown in FIGS. 4 and 5. However, in packet switching, PS-CTL41 and PS-BLK42 instead of I-CTL11 and PS-BLK13
For circuit switching, use CS-CTL31 and CS-BLK32 instead of I-CTL11 and CS-BLK12, and use I-CTL for trunk line control.
LN-CTL51 and LN-BLK52 may be used instead of CTL11 and LN-BLK14, respectively.

In the above description of the second embodiment, each module is one, but it is clear that the embodiment having a plurality of each module can be easily configured by expanding the above description.

〔The invention's effect〕

As described above, according to the present invention, in the case of configuring an exchange that integrates a circuit switching function and a packet switching function,
By connecting a module having a circuit switching terminal interface function, a packet switching terminal interface function, and a trunk circuit interface function to a peripheral device connecting bus of a computer, and executing a switching program for controlling the switching module on the computer, The technologies and assets accumulated in the field of computers can be utilized, and it is possible to reduce costs such as hardware and software development, operation, maintenance and management, and improve flexibility in adding functions.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing the flow of information in two embodiments of the present invention, FIG. 2 is a block diagram showing the configuration of the first embodiment of the present invention, and FIG. 3 is a program of the first embodiment. And FIG. 4 is an explanatory view showing a buffer structure, FIG. 4 is a flow chart showing an outline of packet processing of the first embodiment, FIG.
FIG. 6B is a flow chart showing the outline of the circuit switching processing of the first embodiment, and FIG. 6 is a block diagram showing the configuration of the second embodiment of the present invention. Explanation of symbols 1 ... Integrated switching module, 11 ... Integrated switching module controller, 12 ... Circuit switching functional block, 13 ... Packet switching functional block, 14 ... Relay functional block, 2 ... Computer, 21 ... Central processing unit, 22 ... Main memory, 221
...... Operating system, 222 ...... Switching program, 2221 ...... Control information buffer, 2222 ...... Packet buffer, 2223 ...... Input / output control program, 2224 ...... Packet analysis program, 2225 ...... Line switching processing program,
2226 ... Packet switching processing program, 2227 ... Other processing program, 23 ... Direct memory access mechanism, 231 ... Peripheral device connection bus, 3 ... Circuit switching module, 31 ... Circuit switching module control unit, 32 ... Circuit switching function block, 4 ... Packet switching module, 41 ...
... packet switching module control unit, 42 ... packet switching function block, 5 ... relay line module, 51 ... relay line module control unit, 52 ... relay function block.

Claims (1)

(57) [Claims] 1. A bus for connecting a peripheral device of a computer, having a circuit switching terminal interface function, a packet switching terminal interface function and a trunk line interface function as a peripheral device having a direct memory access function,
When one switching module is connected or each switching module individually having each of the functions is connected and the switching program for controlling the switching module is executed by the computer, only the communication data of the circuit switching is described above. It is returned in the module, and the communication control information of the circuit switching is packetized in the switching module and then stored in the computer together with the data and control information of the packet switching using the direct memory access function provided in the computer. An integrated exchange characterized by performing integrated switching of circuit switching and packet switching by being taken in and processed.