KR100269289B1 - 실리콘막의결정화방법 - Google Patents
실리콘막의결정화방법 Download PDFInfo
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- KR100269289B1 KR100269289B1 KR1019970005053A KR19970005053A KR100269289B1 KR 100269289 B1 KR100269289 B1 KR 100269289B1 KR 1019970005053 A KR1019970005053 A KR 1019970005053A KR 19970005053 A KR19970005053 A KR 19970005053A KR 100269289 B1 KR100269289 B1 KR 100269289B1
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- film
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/02436—Intermediate layers between substrates and deposited layers
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- H01L21/0245—Silicon, silicon germanium, germanium
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- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02502—Layer structure consisting of two layers
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- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
- H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
Claims (4)
- 절연막 상에 비정질실리콘막을 증착하는 단계;상기 비정질실리콘막 상에, 상기 비정질실리콘막을 증착한 설비의 진공을 그대로 유지한 채 연속하여 다결정실리콘막을 증착하는 단계;상기 다결정실리콘막에 실리콘이온(Si+)을 주입하여 비정질화시키는 단계; 및결과물을 열처리하여 비정질화된 다결정실리콘막을 재결정화시키는 단계를 구비하는 것을 특징으로 하는 실리콘막의 결정화방법.
- 제 1 항에 있어서, 상기 비정질실리콘막은,420℃ ∼ 550℃의 온도에서 증착하는 것을 특징으로 하는 실리콘막의 결정화방법.
- 제 1 항에 있어서, 상기 다결정실리콘막은,550℃ ∼ 650℃의 온도에서 증착하는 것을 특징으로 하는 실리콘막의 결정화방법.
- 제 1 항에 있어서, 상기 실리콘이온(Si+)은,0° ∼ 7°의 틸트각도로 주입하는 것을 특징으로 하는 실리콘막의 결정화방법.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019970005053A KR100269289B1 (ko) | 1997-02-19 | 1997-02-19 | 실리콘막의결정화방법 |
US09/026,538 US6057213A (en) | 1997-02-19 | 1998-02-19 | Methods of forming polycrystalline semiconductor layers |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019970005053A KR100269289B1 (ko) | 1997-02-19 | 1997-02-19 | 실리콘막의결정화방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR19980068459A KR19980068459A (ko) | 1998-10-15 |
KR100269289B1 true KR100269289B1 (ko) | 2000-10-16 |
Family
ID=19497464
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019970005053A Expired - Fee Related KR100269289B1 (ko) | 1997-02-19 | 1997-02-19 | 실리콘막의결정화방법 |
Country Status (2)
Country | Link |
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US (1) | US6057213A (ko) |
KR (1) | KR100269289B1 (ko) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6399458B1 (en) * | 1999-09-21 | 2002-06-04 | International Business Machines Corporation | Optimized reachthrough implant for simultaneously forming an MOS capacitor |
KR100460209B1 (ko) * | 2002-11-08 | 2004-12-04 | 엘지.필립스 엘시디 주식회사 | 비정질 실리콘층의 결정화 방법 |
KR20100074193A (ko) * | 2007-09-21 | 2010-07-01 | 더 트러스티이스 오브 콜롬비아 유니버시티 인 더 시티 오브 뉴욕 | 박막 트랜지스터에서 사용되는 측면 결정화된 반도체 섬의 집합 |
CN104992899A (zh) * | 2015-06-09 | 2015-10-21 | 深圳市华星光电技术有限公司 | 多晶硅薄膜的制备方法及多晶硅tft结构 |
CN106876401B (zh) * | 2017-03-07 | 2018-10-30 | 长江存储科技有限责任公司 | 存储器件的形成方法 |
US10651039B2 (en) * | 2017-12-29 | 2020-05-12 | Texas Instruments Incorporated | Polysilicon gate formation in CMOS transistors |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6178119A (ja) * | 1984-09-25 | 1986-04-21 | Sony Corp | 半導体の製造方法 |
JPS61131413A (ja) * | 1984-11-30 | 1986-06-19 | Sony Corp | 半導体薄膜の形成方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55115341A (en) * | 1979-02-28 | 1980-09-05 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
US4654958A (en) * | 1985-02-11 | 1987-04-07 | Intel Corporation | Process for forming isolated silicon regions and field-effect devices on a silicon substrate |
US4904611A (en) * | 1987-09-18 | 1990-02-27 | Xerox Corporation | Formation of large grain polycrystalline films |
JPH01162376A (ja) * | 1987-12-18 | 1989-06-26 | Fujitsu Ltd | 半導体装置の製造方法 |
US5318919A (en) * | 1990-07-31 | 1994-06-07 | Sanyo Electric Co., Ltd. | Manufacturing method of thin film transistor |
US5529951A (en) * | 1993-11-02 | 1996-06-25 | Sony Corporation | Method of forming polycrystalline silicon layer on substrate by large area excimer laser irradiation |
US5393682A (en) * | 1993-12-13 | 1995-02-28 | Taiwan Semiconductor Manufacturing Company | Method of making tapered poly profile for TFT device manufacturing |
US5399883A (en) * | 1994-05-04 | 1995-03-21 | North Carolina State University At Raleigh | High voltage silicon carbide MESFETs and methods of fabricating same |
US5543348A (en) * | 1995-03-29 | 1996-08-06 | Kabushiki Kaisha Toshiba | Controlled recrystallization of buried strap in a semiconductor memory device |
US5652156A (en) * | 1995-04-10 | 1997-07-29 | Taiwan Semiconductor Manufacturing Company Ltd. | Layered polysilicon deposition method |
US5614428A (en) * | 1995-10-23 | 1997-03-25 | Lsi Logic Corporation | Process and structure for reduction of channeling during implantation of source and drain regions in formation of MOS integrated circuit structures |
-
1997
- 1997-02-19 KR KR1019970005053A patent/KR100269289B1/ko not_active Expired - Fee Related
-
1998
- 1998-02-19 US US09/026,538 patent/US6057213A/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6178119A (ja) * | 1984-09-25 | 1986-04-21 | Sony Corp | 半導体の製造方法 |
JPS61131413A (ja) * | 1984-11-30 | 1986-06-19 | Sony Corp | 半導体薄膜の形成方法 |
Also Published As
Publication number | Publication date |
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KR19980068459A (ko) | 1998-10-15 |
US6057213A (en) | 2000-05-02 |
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