KR100268782B1 - Method for manufacturing capacitor of semiconductor device - Google Patents
Method for manufacturing capacitor of semiconductor device Download PDFInfo
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- KR100268782B1 KR100268782B1 KR1019970024184A KR19970024184A KR100268782B1 KR 100268782 B1 KR100268782 B1 KR 100268782B1 KR 1019970024184 A KR1019970024184 A KR 1019970024184A KR 19970024184 A KR19970024184 A KR 19970024184A KR 100268782 B1 KR100268782 B1 KR 100268782B1
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 239000003990 capacitor Substances 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title description 2
- 238000003860 storage Methods 0.000 claims abstract description 45
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 24
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 19
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 15
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 238000009832 plasma treatment Methods 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 238000005121 nitriding Methods 0.000 claims description 3
- 239000002994 raw material Substances 0.000 claims description 3
- 238000009279 wet oxidation reaction Methods 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 abstract description 9
- 239000011229 interlayer Substances 0.000 abstract description 5
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- 238000002955 isolation Methods 0.000 abstract description 3
- 229910020286 SiOxNy Inorganic materials 0.000 abstract description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract description 2
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 abstract 1
- 239000010408 film Substances 0.000 description 75
- 239000007789 gas Substances 0.000 description 10
- 239000010410 layer Substances 0.000 description 8
- 230000008021 deposition Effects 0.000 description 3
- 229910020776 SixNy Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910017855 NH 4 F Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000006396 nitration reaction Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Semiconductor Memories (AREA)
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Abstract
Description
본 발명은 반도체소자의 캐패시터 형성방법에 관한 것으로써, 특히 캐패시터의 유전체로 단차피복성이 우수한 LPCVD Ta2O5막을 사용할 경우, 상기 LPCVD Ta2O5막을 형성하기 전에 전하저장전극 표면에 특수처리함으로써 캐패시터의 전기적 특성을 개선시키고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a capacitor of a semiconductor device, and in particular, when using an LPCVD Ta 2 O 5 film having excellent step coverage as a dielectric of a capacitor, a special treatment is performed on the surface of the charge storage electrode before forming the LPCVD Ta 2 O 5 film. By doing so, the present invention relates to a technology capable of improving electrical characteristics of capacitors and thereby improving characteristics and reliability of semiconductor devices.
최근 반도체소자의 고집적화 추세에 따라 셀 크기가 감소되어 충분한 정전용량을 갖는 캐패시터를 형성하기가 어려워지고있다.Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance due to a decrease in cell size.
특히, 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자에서는 캐패시터의 정전용량을 증가시키기 위하여 유전상수가 높은 물질을 유전체막으로 사용하거나, 유전체막의 두께를 얇게하거나 또는 전하저장전극의 표면적을 증가시키는 등의 방법이 있다.In particular, in a DRAM device composed of one MOS transistor and a capacitor, a material having a high dielectric constant is used as the dielectric film, a thickness of the dielectric film is increased, or the surface area of the charge storage electrode is increased to increase the capacitance of the capacitor. There is a way.
도시되어 있지는 않지만, 종래기술에 따른 반도체소자의 캐패시터 제조방법을 살펴보면 다음과 같다.Although not shown, looking at the capacitor manufacturing method of the semiconductor device according to the prior art as follows.
먼저, 반도체기판 상에 소자분리 산화막과 게이트산화막을 형성하고, 게이트전극과 소오스/드레인전극으로 구성되는 모스 전계효과 트랜지스터를 형성한 후, 상기 구조의 전표면에 층간절연막을 형성한다.First, a device isolation oxide film and a gate oxide film are formed on a semiconductor substrate, and a MOS field effect transistor including a gate electrode and a source / drain electrode is formed, and then an interlayer insulating film is formed on the entire surface of the structure.
그 다음 상기 소오스/드레인전극 중 전하저장전극 콘택으로 예정되어 있는 부분 상측의 층간절연막을 제거하여 전하저장전극 콘택홀을 형성하고, 상기 콘택홀을 통하여 소오스/드레인전극과 접촉되는 전하저장전극을 다결정실리콘층 패턴으로형성한 후, 상기 전하저장전극의 표면에 산화막이나 질화막 또는 산화막-질화막-산화막의 적층구조로된 유전체막을 도포하며, 상기 유전체막상에 전하저장전극을 감싸는 플레이트전극을 형성하여 캐패시터를 완성한다.Next, a charge storage electrode contact hole is formed by removing an interlayer insulating layer on an upper portion of the source / drain electrode, which is intended to be a charge storage electrode contact, and polycrystalline a charge storage electrode contacting the source / drain electrode through the contact hole. After forming a silicon layer pattern, a dielectric film having a laminated structure of an oxide film, a nitride film, or an oxide film-nitride film-oxide film is coated on the surface of the charge storage electrode, and a plate electrode is formed on the dielectric film to surround the charge storage electrode. Complete
상기와 같은 종래기술에 따른 반도체소자의 캐패시터에서 유전체막은 고유전율, 저누설전류밀도, 높은 절연파괴전압 및 상하측 전극과의 안정적인 계면특성 등이 요구되는데, 상기 산화막은 유전상수가 약 3.8 정도이고 질화막은 약 7.2 정도로 비교적 작고, 전극으로 사용되는 다결정실리콘층은 비저항이 800~1000μΩcm 정도로 비교적 높아 정전용량이 제한된다.In the capacitor of the semiconductor device according to the prior art as described above, the dielectric film requires high dielectric constant, low leakage current density, high dielectric breakdown voltage, and stable interfacial characteristics with the upper and lower electrodes. The oxide film has a dielectric constant of about 3.8. The nitride film is relatively small at about 7.2, and the polysilicon layer used as an electrode has a relatively high resistivity of about 800 to 1000 mu OMEGA cm.
상기와 같은 문제점을 해결하기 위하여 산화막-질화막-산화막의 적층구조로된 유전체막 대신에 Ta2O5막과 같은 고유전체막을 사용한다.In order to solve the above problems, a high-k dielectric film such as a Ta 2 O 5 film is used instead of a dielectric film having a stacked structure of an oxide film-nitride film-oxide film.
상기 Ta2O5막은 256M DPAM 이상의 고집적 메모리 소자의 캐패시터의 유전체막으로 사용이 널리 고려되고 있다.The Ta 2 O 5 film is widely considered to be used as a dielectric film of a capacitor of a high density memory device of 256M DPAM or more.
그러나 상기 Ta2O5막을 유전체막으로 사용하는 캐패시터는 상기 Ta2O5막의 증착방법에 따라 캐패시터의 전기적 특성이 크게 변화된다.However, in the capacitor using the Ta 2 O 5 film as the dielectric film, the electrical characteristics of the capacitor change greatly according to the deposition method of the Ta 2 O 5 film.
즉, 플라즈마 화학기상증착(plasma enhanced cheemical vapor deposition, 이하 PECVD라 함)방법으로 상기 Ta2O5막을 증착하여 평판 캐패시터를 형성하는 경우, 저압화학기상증착(low pressure chemical vapor deposition, 이하 LPCVD라 함)방법으로 Ta2O5막을 증착할 때보다 전기적 특성이 우수하다.That is, when the Ta 2 O 5 film is deposited to form a flat plate capacitor by plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD) is called. The electrical properties are better than that of the Ta 2 O 5 film.
그러나, 실제로 사용되는 캐패시터는 실린더형 및 핀구조등 다양한 구조의 소자이고, 또한, 이러한 소자들은 단차가 크기때문에 상기 Ta2O5막은 단차피복성(stepcoverage)이 우수해야 한다.However, the capacitor actually used is a device having various structures such as a cylindrical shape and a fin structure, and since these devices have a large step, the Ta 2 O 5 film should have excellent step coverage.
그런데, 상기 PECVD방법으로 증착된 Ta2O5막은 LPCVD방법으로 증착된 Ta2O5막에 비하여 단차피복성가 매우 불량하여, 실제의 소자에 적용할 경우 높은 누설전류를 유발시키는 문제점이 있다.However, the Ta 2 O 5 film deposited by the PECVD method is very poor step coverage compared to the Ta 2 O 5 film deposited by the LPCVD method, there is a problem that causes high leakage current when applied to the actual device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 캐패시터 형성시 단차피복성가 우수한 LPCVD방법으로 증착된 Ta2O5막을 사용하고, 상기 LPCVD방법으로 증착된 Ta2O5막을 증착하기 전에 전하저장전극 표면에 특수처리함으로써 캐패시터의 전기적 특성을 개선하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 반도체소자의 캐패시터 형성방법을 제공하는데 그 목적이 있다.The present invention uses a Ta 2 O 5 film deposited by the LPCVD method with excellent step coverage when forming a capacitor, and charge storage before depositing the Ta 2 O 5 film deposited by the LPCVD method to form a capacitor It is an object of the present invention to provide a method for forming a capacitor of a semiconductor device by improving the electrical characteristics of the capacitor and thereby improving the characteristics and reliability of the capacitor by special treatment on the electrode surface.
제1도는 본 발명에 따른 반도체소자의 캐패시터 형성방법을 나타낸 단면도.1 is a cross-sectional view showing a method of forming a capacitor of a semiconductor device according to the present invention.
제2도는 본 발명에 따른 반도체소자의 캐패시터 형성방법에 대한 누설전류 특성을 나타낸 그래프도.2 is a graph showing leakage current characteristics of a method for forming a capacitor of a semiconductor device according to the present invention.
〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
11 : 반도체기판 13 : 도프드 다결정실리콘11: semiconductor substrate 13: doped polycrystalline silicon
15 : 플라즈마 처리된 질화막 17 : LPCVD Ta2O5막15 plasma treated
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 캐패시터 형성방법은, 반도체기판 상부에 도프드 다결정실리콘으로 전하저장전극을 형성하는 공정과, 상기 전하저장전극 전체표면을 질화화하는 공정과, 상기 질화된 전하저장전극의 표면을 산화시키는 공정과, 상기 전하전극전극 표면에 Ta2O5막을 LPCVD방법으로 증착하는 공정과, 상기 Ta2O5막을 플라즈마처리하는 공정과, 상기 Ta2O5막을 열처리하는 공정과, 전체표면 상부에 플레이트 전극을 형성하는 공정을 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of forming a capacitor of a semiconductor device according to the present invention comprises the steps of forming a charge storage electrode of the doped polycrystalline silicon on the semiconductor substrate, the step of nitriding the entire surface of the charge storage electrode; a step of oxidizing the surface of the nitride charge storage electrode, and a step of depositing a Ta 2 O 5 LPCVD film method to the charge electrode electrode surface, the step of plasma processing the Ta 2 O 5 film and the Ta 2 O 5 film And a step of forming a plate electrode on the entire surface.
한편, 이상의 목적을 달성하기 위한 본 발명의 원리는, 캐패시터의 유전체막 형성시 PECVD방법으로 증착한 Ta2O5막은 단차피복성이 불량하기 때문에 단차피복성이 우수한 LPCVD방법으로 증착된 Ta2O5막을 사용하는데, 상기 LPCVD방법으로 증착된 Ta2O5막이 우수한 전기적 특성을 갖게 하기 위하여 상기 LPCVD방법으로 증착된 Ta2O5막을 증착하기 전에 하부층을 질화화한 후 플라즈마 처리하여 산화시키고, 상기 LPCVD방법으로 증착된 Ta2O5막을 증착해서 플라즈마처리 또는 UV-O3가스 처리하고, Ta2O5막을 다결정화시키기 위하여 열처리를 실시함으로써 캐패시터의 전기적 특성을 개선하는 것이다.On the other hand, the principles of the present invention for achieving the above object, the step coverage is deposited as excellent LPCVD method, because the step coverage which when the dielectric film formed deposited PECVD method Ta 2 O 5 film of the capacitor to poor Ta 2 O uses 5 film, and oxidation after the LPCVD method as-deposited Ta 2 O 5 as a film by nitriding Chemistry a lower layer prior to depositing a film of Ta 2 O 5 deposition by the LPCVD method to have excellent electrical characteristics the plasma treatment, the The Ta 2 O 5 film deposited by the LPCVD method is deposited to perform plasma treatment or UV-O 3 gas treatment, and heat treatment is performed to polycrystalline the Ta 2 O 5 film, thereby improving the electrical characteristics of the capacitor.
이하, 첨부된 도면을 참고로 하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail.
도 1은 본 발명에 따른 반도체소자의 캐패시터 형성방법을 도시한 단면도이다.1 is a cross-sectional view showing a method of forming a capacitor of a semiconductor device according to the present invention.
먼저, 반도체기판(11)에 소자분리 절연막(도시안됨), 게이트산화막(도시안됨), 게이트전극(도시안됨) 및 비트라인(도시안됨) 등의 하부구조물을 형성한다.First, lower structures such as an isolation layer (not shown), a gate oxide layer (not shown), a gate electrode (not shown), and a bit line (not shown) are formed on the
다음, 전체표면에 평탄화막(도시안됨)을 형성한다.Next, a planarization film (not shown) is formed over the entire surface.
그 다음, 도핑되지 않은 산화막으로 층간절연막(도시안됨)을 형성하다.Then, an interlayer insulating film (not shown) is formed of an undoped oxide film.
그리고, 상기 층간절연막은 콘택마스크를 이용하여 콘택부분으로 예정되는 부분에 콘택홀(도시안됨)을 형성한다.In addition, the interlayer insulating layer forms a contact hole (not shown) in a portion that is intended to be a contact portion using a contact mask.
그 다음, 상기 구조의 전표면에 다결정실리콘막(도시안됨)을 화학기상증착방법(Chemical Vapor Deposition, 이하 CVD라함)으로 형성한 다음, 상기 콘택홀(도시안됨) 내부에만 상기 다결정실리콘막이 남도록 식각하여 상기 콘택홀(도시안됨)을메우는 콘택플러그(도시안됨)를 형성한다.Then, a polysilicon film (not shown) is formed on the entire surface of the structure by chemical vapor deposition (CVD), and then etched so that the polycrystalline silicon film remains only inside the contact hole (not shown). As a result, a contact plug (not shown) filling the contact hole (not shown) is formed.
그리고, 상기 콘택플러그(도시안됨)과 접촉되는 전하저장전극(13)을 형성한다. 여기서, 상기 전하저장전극(13)은 불순물이 도핑된 다결정실리콘으로 형성하며, 전하저장전극의 구조는 실린더형, 핀형 및 다른 구조를 가지는 경우가 있다. 그리고, 상기 전하저장전극(13)의 구조에 반구형 다결정실리콘(hemispherical grained silicate glass, HSG)을 사용하는 경우도 있다.In addition, the
그 다음, 전하저장전극(13) 표면에 발생한 자연산화막을 제거한다. 이대, 상기 자연산화막은 산화막 식각용액인 HF+H2O또는 HF+NH4F+H2O 등을 사용하여 제거한다.Next, the natural oxide film generated on the surface of the
그 후, 상기 전하저장전극(13)인 도프드 다결정실리콘의 전체표면을 질화화시킨다. 여기서, 상기 전하저장전극(13)의 질화화는 NH3가스를 이용하여 알.티.엔.(rapid thermal nitration, 이하 RTN라 함)법으로 800~900℃ 정도의 온도에서 40~100초 정도 실시한다.Thereafter, the entire surface of the doped polycrystalline silicon, which is the
그리고, 상기 질화화된 전하저장전극의 표면은 N2O 및 O2등 산소가 함유된 가스를 이용하여 플라즈마 상태에서 처리하여 산질화막(SiOxNy)이 얇게 형성된게 한다. 이때, 상기 플라즈마를 발생시키는 파워(power)는 100~200W 정도로 한다.In addition, the surface of the nitrided charge storage electrode is treated in a plasma state using a gas containing oxygen such as N 2 O and O 2 to form a thin oxynitride layer (SiOxNy). At this time, the power (power) for generating the plasma is about 100 ~ 200W.
그리고, 상기 질화된 전하저장전극은 150~450℃ 정도의 기판온도, 1mTorr~9Torr 정도의 압력의 조건을 갖는다.The nitrided charge storage electrode has a substrate temperature of about 150 to 450 ° C. and a pressure of about 1 mTorr to 9 Torr.
한편, 상기 플라즈마 여기가스에 의해 질화된 전하저장전극(15)의 표면을 산화시키는 대신 O2또는 H2O 증기를 이용한 건식 또는 습식 산화에 의하여 상기 질화된 전하저장전극(15)의 표면을 산화시킬 수 있다. 그러나, 상기와 같은 산화방법은 700℃ 이상의 고온에서의 공정을 요구하기 때문에 질화막 자체의 산화저항성이 파괴되어 상기 질화막 하부의 도프드 다결정실리콘(13)까지 산화되어 캐패시터의 유효 산화막 두께가 증가되는 문제점이 있다.On the other hand, instead of oxidizing the surface of the
또한, 상기 질화화된 전하저장전극(15)을 산화시키는 공정은 상기 질화된 전하저장전극(15)의 표면에 증착하고자 하는 Ta2O5막의 일부를 PECVD방법으로 증착한 다음, 다시 LPCVD방법으로 Ta2O5막의 나머지 부분을 증착하여 산화시키는 방법으로대신할 수 있다.In addition, the process of oxidizing the nitrided
이때, 상기 PECVD방법으로 Ta2O5막은 N2O 또는 O2가스와 Ta(OC2H5)5을 원료로 사용하여 350~450℃ 정도의 온도에서 80~200W의 알.에프.(R.F) 전력을 조건으로 5~50Å 정도의 Ta2O5막을 증착한다.At this time, by using the PECVD method, the Ta 2 O 5 film is formed using N 2 O or O 2 gas and Ta (OC 2 H 5 ) 5 as a raw material. ) Ta 2 O 5 film is deposited on the condition of power of 5 ~ 50Å.
참고로, 상기 RTN 공정을 실시하는 조건에서 온도가 900℃ 이상으로 고온이거나, 처리시간이 길어지면 상기 전하저장전극의 표면위에 질화된 부분이 두꺼워져서 후속 산화공정시 상기 질화된 부분이 충분히 산화되지 않는 경우가 발생하게 된다.For reference, when the temperature is higher than 900 ° C. under the conditions of the RTN process or the processing time is long, the nitrided part becomes thick on the surface of the charge storage electrode so that the nitrided part is not sufficiently oxidized in the subsequent oxidation process. If not, will occur.
아래의 표 1은 RTN 온도에 다른 반도체기판 상의 질화막 두께를 나타낸다.Table 1 below shows the thickness of the nitride film on the semiconductor substrate at different RTN temperatures.
상기와 같이 질화된 전하저장전극 표면을 산질화막으로 변경하여도 Ta2O5막을 사용한 캐패시터의 유효산화막 두께에 미치는 영향은 3Å 이하이지만, 누설전류 특성은 개선가능하다.Even if the surface of the nitrided charge storage electrode is changed to an oxynitride film, the effect on the effective oxide film thickness of the capacitor using the Ta 2 O 5 film is 3 kΩ or less, but the leakage current characteristics can be improved.
즉, 전하저장전극 HF 클리닝 공정 후 RTN처리하면 전하저장전극 표면에 SixNy막이 형성되며, 이 표면을 플라즈마 산화(N2O)처리하므로써 SixNy이 SixOyNz형태로 변형되어 캐패시터의 누설전류를 감소시킨다.That is, when the RTN treatment is performed after the charge storage electrode HF cleaning process, a SixNy film is formed on the surface of the charge storage electrode, and the surface is subjected to plasma oxidation (N 2 O), thereby transforming SixNy into SixOyNz to reduce the leakage current of the capacitor.
그 다음, 상기 산화된 전하저장전극의 상부에 LPCVD방법으로 Ta2O5막(17)을 일정두께 증착한다. 이때, 상기 Ta2O5막(17)은 N2O 또는 O2가스와 Ta(OC2H5)5을 원료로 사용하여 1mTorr~9Torr 정도의 압력 및 350~450℃ 정도 온도에서 증착한다.(도 1)Then, a Ta 2 O 5 film 17 is deposited to a predetermined thickness on the oxidized charge storage electrode by LPCVD. At this time, the Ta 2 O 5
그 후, 상기 Ta2O5막 내의 산소결핍 및 탄소를 제거하기 위하여, 상기 Ta2O5막을 N2O 또는 O2가스에 의한 플라즈마 가스로 150~450℃ 정도의 온도에서 처리한다. 여기서, 상기 N2O 또는 O2가스에 의한 플라즈마처리 대신 자외선에 의해서 활성화된 UV-O3가스로 처리하기도 한다.Then, to remove oxygen and carbon deficiency in the Ta 2 O 5 film, is processed by the Ta 2 O 5 N 2 O or O film temperature of 150 ~ 450 ℃ to the plasma gas degree by the second gas. Here, instead of the plasma treatment by the N 2 O or O 2 gas may be treated with UV-O 3 gas activated by ultraviolet light.
그리고, 상기 Ta2O5막을 다결정화시키기 위하여 700~820℃ 정도 온도의 N2O 또는 O2분위기에서 열처리 한다.In order to polycrystallize the Ta 2 O 5 film, heat treatment is performed in an N 2 O or O 2 atmosphere at a temperature of about 700 to 820 ° C.
그리고, 후속공정으로 전체표면에 TiN을 증착한 후, 도프드 다결정실리콘을 증착하여 플레이트 전극을 형성한다.Subsequently, TiN is deposited on the entire surface in a subsequent process, and then doped polycrystalline silicon is deposited to form a plate electrode.
그 다음, 상기 플레이트 전극을 패터닝하여 캐패시터 형성공정을 완료한다.The plate electrode is then patterned to complete the capacitor formation process.
참고로, 도 2는 실린더 구조의 전하저장전극 상에서 유효산화막 두께가 30Å인 Ta2O5캐패시터에 있어서, Ta2O5증착을 PECVD방법으로만 한 경우, PECVD 공정 후 LPCVD로 차례로 증착한 경우, LPCVD 후 PECVD방법으로 차례로 증착하여 Ta2O5막을 형성한 각각 경우에 대한 누설전류 특성이다.For reference, FIG. 2 is a Ta 2 O 5 capacitor having an effective oxide film thickness of 30 μs on a cylinder-shaped charge storage electrode. When Ta 2 O 5 deposition is performed only by PECVD, after the PECVD process is sequentially deposited by LPCVD, Leakage current characteristics for each case of Ta 2 O 5 film formation by successive deposition by LPCVD after LPCVD.
앞에서 언급했듯이 PECVD방법으로만 Ta2O5을 증착한 경우의 누설전류값이 가장 높고, PE/LPCVD방법을 차례로 사용하여 Ta2O5박막을 형성한 경우의 누설전류값이 가장 낮다. 여기서, 상기 PECVD방법으로만 Ta2O5을 증착한 경우에는 상기 PECVD Ta2O5의 단차피복성이 불량하기 때문에 누설전류 값이 가장 높다.As mentioned above, the leakage current value is highest when Ta 2 O 5 is deposited only by PECVD method, and the leakage current value is lowest when Ta 2 O 5 thin film is formed by using PE / LPCVD method. Here, when Ta 2 O 5 is deposited only by the PECVD method, the leakage current value is the highest because the step coverage of the PECVD Ta 2 O 5 is poor.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 캐패시터 형성방법은, 고유전율을 갖는 Ta2O5막을 유전체막으로 사용하는 캐패시터에서 PECVD방법으로 증착된 Ta2O5막의 불량한 단차피복성을 개선하기 위해서, 단차피복성이 우수한 LPCVD방법으로 Ta2O5막을 증착하는데, 상기 LPCVD방법으로 증착한 Ta2O5막 증착하기 전에 하부의 전하저장전극의 표면을 특수처리함으로써 캐패시터의 전기적 특성을 개선하여 누설전류가 발생하는 것을 방지하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, the method for forming a capacitor of a semiconductor device according to the present invention improves poor step coverage of a Ta 2 O 5 film deposited by PECVD in a capacitor using a Ta 2 O 5 film having a high dielectric constant as a dielectric film. To this end, a Ta 2 O 5 film is deposited by an LPCVD method having excellent step coverage, and the electrical characteristics of the capacitor are improved by specially treating the surface of the lower charge storage electrode before depositing the Ta 2 O 5 film deposited by the LPCVD method. There is an advantage of preventing leakage current from occurring and thereby improving characteristics and reliability of the semiconductor device.
Claims (12)
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| KR1019970024184A KR100268782B1 (en) | 1997-06-11 | 1997-06-11 | Method for manufacturing capacitor of semiconductor device |
| GB9812283A GB2326279B (en) | 1997-06-11 | 1998-06-09 | Method of forming a capacitor of a semiconductor device |
| DE19825736A DE19825736C2 (en) | 1997-06-11 | 1998-06-09 | Method of forming a capacitor of a semiconductor device |
| TW087109222A TW396501B (en) | 1997-06-11 | 1998-06-10 | Method of forming a capacitor of a semiconductor device |
| JP17656798A JP3451943B2 (en) | 1997-06-11 | 1998-06-10 | Method for forming capacitor of semiconductor device |
| US09/095,696 US5985730A (en) | 1997-06-11 | 1998-06-11 | Method of forming a capacitor of a semiconductor device |
| CN98102096A CN1129171C (en) | 1997-06-11 | 1998-06-11 | Method of forming capacitor of semiconductor device |
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