KR100262637B1 - Portionally variable ratio scaling apparatus and method of video signals - Google Patents

Abstract

PURPOSE: An apparatus and method for converting a display rate of a video signal is provided to change a vertical and horizontal ratio of a video by easily changing an output speed of video data in an arbitrary horizontal/vertical position. CONSTITUTION: A microprocessor(500) generates information on change volume of clock speed. A bus decoder(501) receives the information outputted from the microprocessor(500). A pixel counter unit(502) determines the length of a horizontal section. A horizontal clock speed control unit(506) controls a horizontal clock speed. A horizontal clock value generation unit(507) generates a horizontal clock value. A horizontal clock value low pass filter(508) filters an output signal of the generation unit(507). A horizontal clock generation unit(503) generates a horizontal clock signal. A vertical counter unit(504) determines the length of each vertical section. A vertical clock speed control unit(513) controls a vertical clock speed. A vertical clock value generation unit(514) generates a vertical clock value. A vertical clock value low pass generation unit(515) filters an output signal of the generation unit(514). A clock selection unit(509) selectively selects an output signal among signals of the generation units(503,505). A video processing unit(510) converts and displays an input video.

Description

Display ratio converting apparatus and method of video signal {Portionally Variable Ratio Scaling Apparatus And Method of video Signals}

The present invention relates to an apparatus and method for converting a display ratio of an image signal, and more particularly, to displaying an image signal capable of varying aspect ratios of an image at a corresponding position by varying clock speeds of the image data at arbitrary horizontal and vertical positions. It relates to a ratio converter and a method.

Recently, with the development of video display devices and the development of information and communication, the general public can easily access images for personal use. Accordingly, more and more homes and offices collect images. Until now, screen editing has been mainly performed on a PC. Most screen editing is based on reading image data from video RAM, transforming it, and then rewriting it.

However, in the case of TV, since the purpose is to display an image as it is, it is not a device that can perform an editing function. Since the general aspect ratio is a fixed aspect ratio such as 4: 3 or 16: 9, when attempting to convert the aspect ratio in consideration of the characteristics of the input image, it has been limited to the technique of changing the aspect ratio of the entire screen.

This is not simply for editing, but for easy viewing. In addition, a method of changing the display ratio in the horizontal direction and the vertical direction by adjusting the deflection inclination of the display device or adjusting the read / write clock speed has been proposed.

This technique changes the display ratio of the entire screen at a constant ratio in the horizontal or vertical direction of the screen. Therefore, only the ratio of the entire screen could be changed linearly.

For example, the general analog deflection wave generator shown in FIG. 1 generates horizontal and vertical sawtooth wave circuits 11 for generating horizontal and vertical saw tooth waves according to input horizontal and vertical synchronization signals Hsync / Vsync. 21 and horizontal and vertical S-shaped correction circuits 12 and 22 for correcting the start and end portions of the output waveforms output from the horizontal and vertical sawtooth wave generating circuits 11 and 21 into S-shaped shapes, respectively. And amplifying the output signals of the horizontal and vertical S-shape correction circuits 12 and 22 to a predetermined level and outputting them to the CRTs, respectively. Here, the horizontal and vertical sawtooth waves are set to scan in one direction, for example from left to right, at regular intervals from top to bottom. Here, the image may be horizontally converted at a constant ratio in all vertical directions by horizontal S-shape correction or vertically at a constant ratio in all horizontal directions by vertical S-shape correction.

This is because a straight line is represented only by a straight line, so the angle between the horizontal line and the vertical line is always perpendicular. The reason is that a typical display device is designed to scan at regular intervals in one direction, usually from left to right and top to bottom.

That is, as shown in FIG. 2A, the normal shape without the ratio conversion (display ratio of the image = 1) is the ratio of the scanning time and the scanning distance at an arbitrary point 1 (x ₁ , y ₁ ) of the screen in the horizontal and vertical directions. Equation 1 always holds for.

_x11 t: t = d _{x12 x11:} d _x12 and _y11 t: t d = _{y12 y11:} d _y12

However, when it is necessary to intentionally change the aspect ratio of the screen to make a screen that looks better than the original image or vice versa, the conventional method cannot. That is, until now, the ratio of deflection of the input image is fixed at a constant ratio in the horizontal or vertical direction of the entire screen. Therefore, the ratio of the entire screen can be changed in common at the same time. It was impossible to convert.

If the aspect ratio of the screen of the necessary part of the entire screen can be changed, it is possible to provide an improved screen by utilizing the inherent characteristics of the video signal, and this technique may be applied to various fields of the video display device.

The present invention is to propose a technique capable of converting the output speed of the image data to have a desired ratio during a desired position or a desired section of the screen in a state in which the entire screen is divided into a plurality of horizontal sections and vertical sections.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the problems mentioned in the prior art described above, and an object of the present invention is to provide a form suitable for a given screen regardless of the aspect ratio of the input video signal or the range of the viewing area. An aspect of the present invention provides an apparatus and method for converting a display ratio of a video signal to enable different clock speeds of video data at arbitrary horizontal and vertical positions so as to indicate an aspect ratio of the video signal.

Another object of the present invention is to provide an apparatus and method for converting a display ratio of a video signal satisfying the following Equation 2 as necessary at any point of a screen.

_x11 t: t ≠ d _{x12 x11:} d _x12 and _y11 t: t ≠ d _{y12 y11:} d _y12

According to an aspect of the present invention for achieving the above object, a display processor for converting the display ratio of an image signal generates a clock speed change amount information for each block unit is made of the horizontal and vertical sections of the input image, the clock speed A bus decoder for receiving, decoding, and storing the change amount information, and the clock rate change amount of the horizontal and / or vertical conversion of the block are determined in a predetermined order using the stored clock speed change amount information, and the horizontal and / or the change amount is determined from the change amount. The clock speed control unit controls the vertical clock conversion speed.

According to another aspect of the present invention for achieving the above object, the display ratio conversion method of the video signal generates the clock speed change amount information for each block unit that is made by overlapping the horizontal section and the vertical section in the preset order And receiving, decoding, and storing the clock speed change amount information, and determining a clock speed change amount of a corresponding horizontal and / or vertical conversion in a preset order by using the stored clock speed change amount information. And / or controlling the vertical clock conversion signal.

According to the present invention, by using a control device such as a microprocessor, it is possible to easily convert the output speed of the image data in any horizontal and vertical position, resulting in a change in the aspect ratio of the image at that position. In addition, any input pixel can be controlled to be displayed at a desired position.

1 is a block diagram showing the configuration of a general analog deflection wave generator.

2A is a screen state diagram of a normal case without ratio conversion.

FIG. 2B is a screen state diagram in which horizontal clock conversion is performed at a constant rate for all vertical sections with respect to the normal screen shown in FIG.

FIG. 2C is a screen state diagram in which vertical clock conversion is performed at a constant rate for all horizontal sections with respect to the normal screen shown in FIG. 2A.

FIG. 2D is a screen state diagram in which horizontal clock conversion is performed at different rates for all vertical sections with respect to the normal screen shown in FIG. 2A.

FIG. 2E is a screen state diagram in which vertical clock conversion is performed at different rates for all horizontal sections with respect to the normal screen shown in FIG. 2A.

FIG. 2F is a screen state diagram illustrating a case in which the horizontal ratio of each vertical position is different from the normal screen shown in FIG. 2A and the vertical ratio of the horizontal positions is different, and the horizontal and vertical clock conversion of the screen is performed differently according to the horizontal and vertical sections. .

3 is a block diagram illustrating an apparatus for converting a screen display ratio according to an embodiment of the present invention.

FIG. 4 is a block diagram showing the format of a control bus output from the microprocessor shown in FIG.

FIG. 5 is a block diagram illustrating an internal configuration of the bus decoder illustrated in FIG. 3.

FIG. 6 is a block diagram of another embodiment of the bus decoder shown in FIG.

7A to 7B are screen state diagrams for describing an implementation of a display ratio converting method according to the present invention.

8 is a block diagram illustrating a horizontal clock speed controller and a vertical clock speed controller illustrated in FIG. 3.

FIG. 9 is a block diagram illustrating an internal configuration of the horizontal and vertical clock value generators shown in FIG. 3.

FIG. 10 is a block diagram showing the configuration of the flip-flop array shown in FIG.

FIG. 11 is a block diagram illustrating another embodiment of the bus decoder illustrated in FIG. 5.

12A to 12C are block diagrams illustrating respective embodiments of the image processor illustrated in FIG. 5.

FIG. 13 is a block diagram showing the internal configuration of the horizontal processing unit shown in FIG. 12A.

FIG. 14 is a block diagram showing the internal configuration of the vertical processing unit shown in FIGS. 12B to 12C.

FIG. 15 is a diagram illustrating a screen conversion state according to operations of the horizontal processing unit and the vertical processing unit illustrated in FIGS. 13 to 14.

FIG. 16 is a diagram illustrating address translation in horizontal and vertical conversions according to the operations of FIGS. 13 to 14.

17A to 17D are graphs showing changes in clock speeds between horizontal and vertical sections.

Description of the main symbols in the drawings

500: microprocessor 501: bus decoder

502: pixel counter unit 503: horizontal clock generator

504: vertical position counter unit 505: vertical clock generating unit

506: horizontal clock speed control unit 507: horizontal clock value generating unit

508; Horizontal Clock Value Low Pass Filter 509: Clock Selector

510: image processing unit 513: vertical clock speed control unit

514: vertical clock value generator 515: vertical clock value low pass filter

521: horizontal / vertical conversion display section 522: section definition display section

523: section number display section 524: slope display section

525: increase / decrease display section 526: section length display section

Hereinafter, the configuration, operation and effects according to an embodiment of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram of an apparatus for converting a display ratio of a video signal according to an exemplary embodiment.

Referring to FIG. 3, an apparatus for converting a display ratio of a video signal according to an embodiment of the present invention may include a microprocessor that generates clock speed variation information for each block unit in which an input image is formed into a plurality of horizontal and vertical sections according to an input of a user's control signal. And a bus decoder 101 for receiving, decoding, and storing clock speed change amount information output from the microprocessor 500, and horizontal and horizontal blocks of the corresponding block using the clock speed change amount information stored in the bus decoder 101. And a clock speed control unit for determining a clock speed change amount in the vertical direction and controlling the horizontal and / or vertical clock speed change amount by the change amount. Here, the clock speed controller is a pixel clock output from the bus decoder 501, and a tilt or increase provided from the pixel counter unit 502 for determining the length of each horizontal section and the clock speed change amount information stored in the bus decoder 501. / Horizontal clock speed control unit 506 for controlling the horizontal clock speed in response to the reduction information, and the horizontal clock value using the horizontal clock speed control signal and the input horizontal synchronization signal (Hsync) output from the horizontal clock speed control unit 506 A horizontal clock value generator 507 to generate the horizontal clock value low pass filter 508 for filtering the output signal of the horizontal clock value generator 507 to a predetermined frequency band, and a horizontal clock value low pass filter 508 The length of each vertical section is determined by the horizontal clock generator 503 that receives the output signal of the signal and generates a horizontal clock signal, and the horizontal synchronization signal Vsync output from the bus decoder 501. A vertical clock speed controller 513 for controlling the vertical clock speed by receiving the inclination or the increase / decrease information provided from the position controller 504, the clock speed change information stored in the bus decoder 501, and the vertical clock speed controller. The output signal of the vertical clock value generator 514 and the vertical clock value generator 514 for generating a vertical clock value by using the vertical clock speed control signal output from 513 and a vertical synchronous signal provided from the outside A vertical clock value low pass filter 515 for filtering to a predetermined frequency band, a vertical clock generator 505 for receiving an output signal of the vertical clock value low pass filter 515 and generating a vertical clock signal, and a horizontal clock A clock selector 509 for selectively selecting output signals of the generator 503 and the vertical clock generator 505, and an input image according to the display ratio conversion value of the video signal inputted through the clock selector 509; To The image processing unit 510 converts and displays each block.

In the apparatus for converting the display ratio of the video signal according to the above configuration, the entire screen is divided into a plurality of sections in the horizontal and vertical directions by the microprocessor 100, and the clock speed is converted over each section.

Of course, if the conversion control data memory is sufficient and the change in the slope of the change rate is so severe that the image loss does not matter, processing can be performed for each pixel unit. However, in the exemplary embodiment of the present invention, the subdivision can only be visually impaired. It will be described by processing for each section unit of a plurality of preset sections.

That is, the screen is divided into 64 sections horizontally and 64 sections vertically. Each section also has a section length rather than an equal interval, and according to an embodiment of the present invention, each section can be freely adjusted horizontally in units of 1 to 64 pixels or vertically in units of lines. Therefore, no matter how rapidly the change of the conversion rate is visually felt, almost no boundary is felt.

The bus decoder 501 of FIG. 3 receives a bus input in series from the microprocessor 500 and stores necessary data in 64 horizontal and vertical sections. Then, when defining a rectangle that occurs when each horizontal and vertical section overlaps as a block, the stored data receives how much to adjust the horizontal or vertical clock speed for each corresponding block.

Here, the pixel counter unit 502 counts the length of each horizontal section by a pixel clock, and when carry is generated, the end of the section is notified and the count is progressed to the next horizontal section.

Similarly, the vertical position counter unit 504 counts the length of each vertical section by the horizontal synchronization signal (Hsync), and if a carry occurs, the end of the section is notified and the count is advanced to the next vertical section.

The horizontal clock speed controller 506 controls the horizontal clock speed by receiving the slope or increase / decrease information from the bus decoder 501. Then, the horizontal clock value generated by the horizontal clock value generator 507 is changed into a horizontal conversion clock by the digital horizontal clock generator 503 via the horizontal low pass filter 508. This is the horizontal conversion clock at the desired rate for the displayed image.

In addition, the vertical clock speed control unit 513 controls the vertical clock speed by receiving slope or increase / decrease information from the bus decoder 501. Then, the vertical clock value generated by the vertical clock value generator 514 is converted into a vertical conversion clock by the digital vertical clock generator 505 through the vertical low pass filter 515. This is the vertical conversion clock at the desired rate for the displayed image.

On the other hand, the horizontal to vertical interval of 64 means that the sign of the change in the clock speed (tilt) can be changed up to 64 times, so that the curve of the 64th order can be formed, but the period of the sine wave is repeated up to 32 times. Can be.

Therefore, the horizontal clock value low pass filter 508 will have a band of 31.5 kHz x 32 = about 1 MHz or more, for example, if each section has a scanning line of 60 Hz and 525 lines, assuming that the intervals are equally spaced. The low pass filter 515 will have a band of 60 Hz x 32 = about 2 kHz or more. However, as shown in FIG. 6, when the vertical conversion clock is changed according to the horizontal section, that is, when the horizontal line of the screen is converted up and down, the vertical clock value low pass filter 515 also has a band of about 1 MHz or more.

4 shows the format of the control bus output from the microprocessor 500.

Referring to FIG. 4, a bus having clock speed variation information output from the microprocessor 500 may include a vertical / horizontal transformation display section for distinguishing whether subsequent values are values to be applied to horizontal transformation or values to be applied to vertical transformation. 521, a section definition display section 522 for discriminating whether it belongs to a horizontal section or a vertical section for horizontal to vertical conversion, a section number display section 523 for indicating section 0-63, The slope display section 524 for distinguishing whether or not the clock speed conversion is performed and the increase / decrease display section for increasing or decreasing the slope of the clock speed when the state of the slope display section 524 performs the clock speed conversion ( 525 and a section length display section 526 for determining how many pixels (or how many lines in the vertical) the same slope is maintained at the current slope.

The horizontal / vertical conversion display section 521 of the sub address is composed of 1 bit, and distinguishes whether subsequent values are values to be applied to the horizontal conversion or values to be applied to the vertical conversion. In addition, the interval definition display section 522 is composed of 1 bit, and even in the horizontal conversion, the horizontal conversion is performed at different positions in the vertically different positions, thereby distinguishing the horizontal section or the vertical section of the horizontal transformation.

The section number display section 524 is composed of 6 bits and indicates a section of 0 to 63 (or 1 to 64).

When the slope display section 524 is 1, the clock speed is kept constant in the current state, so the increase / decrease display section 525 is ignored. However, when the slope display section 524 is 0, the increase / decrease display section 525 is 1 to increase the speed of the converted clock, and 0 to decrease the speed of the converted clock.

The section length display section 526 determines how many pixels (or how many lines are vertical) to maintain the same slope with the current slope. At this time, the determined value becomes the load value of the pixel counter unit 502 in the horizontal transformation or the load value of the vertical position counter unit 504 in the vertical transformation.

Hereinafter, the operation of the bus decoder 501 for horizontal clock speed conversion will be described with reference to FIG. 5.

In the present invention, since the horizontal conversion is different for each vertical section, the 6-bit x 64 flip-flop memory 536 is set separately so that it is selected for each vertical section by the 64 x 1 mux 539. When the horizontal conversion line counter 541 carries a load after the number of lines in the horizontal conversion line counter 541 is reached, the modulo-64 counter MC52 is notified at the end of the vertical section. The output of this counter MC52 selects the next input of the 6 bit 64 x 1 mux 539 and the 8 bit 64 x 1 mux 538a-538n for vertical section selection.

Since the 8-bit data in the selected vertical section has 64 kinds of conversion data in each horizontal section, when the carry of the horizontal conversion pixel counter unit 502 comes in, it is horizontally passed through the modulo-64 counter MC51. The section number will be output. This value selects the 64 x 1 mux 540 for horizontal section selection, and the slope or increment / decrement value for that block and the current 6-bit value (ie, the horizontal length of the current block) It is output as a load value of the conversion pixel counter 502.

In the vertical conversion, the carry of the vertical position counter 504 for vertical conversion is input in the same manner as the horizontal conversion, and the vertical section is selected by the modulo-64 counter MC53.

In an exemplary embodiment of the present invention, as shown in FIGS. 7A to 7B, the vertical and horizontal section blocks for horizontal transformation and the vertical and horizontal section blocks for vertical transformation are separately provided. The vertical sections were divided, and in the vertical conversion, all horizontal sections were converted to a certain ratio. However, by further expanding this, FIG. 6 shows a bus decoder 501 configured to vary conversion ratios for each horizontal section even in the vertical conversion.

In an embodiment of the present invention, the shape of each block may be arbitrarily determined by the section length data. For convenience, all blocks should not overlap each other and there should not be empty areas, so the vertical lengths of the horizontal sections along one vertical section are made constant. This is because the deflection beam of the CPT runs in order from left to right and top to bottom, but this does not prevent the horizontal straight line from bending up and down. Even if the decoder of FIG. 6 is used, the horizontal straight line can be bent up and down as shown in FIG. 2E through the horizontal change of the vertical conversion clock speed.

8 is a configuration diagram of the horizontal and vertical clock speed controllers 506 and 513 of FIG. In this case, the increase / decrease signal for the slope or the slope is received from the bus decoder 501 to drive the increase / decrease counter 568 that increases the current value when the slope is increased and decreases the current value when the slope is decreased. .

The output of this increment / decrement counter 568 is passed to the clock speed control output. This clock speed control output changes linearly in each section as shown in Figs. 17A and 17B.

FIG. 17A shows the change of the read clock speed with respect to the normal clock speed when used at constant speed, and FIG. 17B shows the change of the write clock speed with respect to the normal clock speed when reading at constant speed.

For reference, since the control value is sufficiently smaller than the normal clock value of the normal screen of FIG. 9, the clock speed is changed relatively slowly, and the digital clock generator is controlled through the horizontal or vertical low pass filters 508 and 515. oscillator (VCO) (503,505) or digital / analog conversion of this value is input to the analog clock generator even if the clock generator generates a changed clock frequency without difficulty.

This digital clock value is preferably 10 bits or more, more than the number of pixels per horizontal scan line (the number of lines on the screen in the case of vertical conversion).

In Fig. 9, the speed control value is summed with the normal clock value to generate a horizontal / vertical clock value such as the waveform shown in Fig. 17D.

In the clock number comparison unit 571 and 574 of FIG. 9, when the number of clocks is counted up to a point corresponding to the end of the image, when the number is larger than the horizontal or vertical length of the memory, the clock is returned to the origin again and then written or read per line When the number of clocks exceeds the boundary, the start of the horizontal scan line (upper part in the vertical case) is broken by an amount exceeding the image data. However, this can be ignored for scrambling effect of the screen.However, to prevent this phenomenon, if the over-count signal occurs, / WE (when changing the speed during writing) or / RE (lead) of the line memory or the field memory is read. Time speed changes).

In this clock speed control method, the output of FIG. 3 is a deflection wave and is not used for direct image conversion. However, the clock whose speed is controlled is input to the image processor 510 to adjust the image display ratio.

FIG. 10 shows how the flip-flop arrays 535a-535n of FIG. 5 store 8-bit data by dividing the vertical section of the horizontal section. That is, when the outputs of the decoders representing the vertical kth section and the horizontal lth section are at the same time high level, the selection signal of the corresponding 2x1 mux 576 is at the high level so that 8 bits is an 8 bit flip-flop ( 577), otherwise, the current value is continuously fed back to maintain its value.

FIG. 11 illustrates an example in which flip-flop memory 587 is used instead of the 64 x 64 8-bit flip-flop arrays 535a-535n shown in FIG. 5. Since the flip-flop memory 587 stores inclination to increase / decrease information for a given length in units of blocks, the flip-flop memory 587 is a kind of two-bit field memory.

In addition, since the 2-bit data is stored only in the vertical direction for the vertical conversion, the flip-flop memory 587 at this time may be a 2-bit line memory in the vertical direction. However, as shown in FIG. 6, when the conversion ratio is changed by placing a horizontal section in the vertical conversion, a 2-bit field memory must be used as in the horizontal conversion.

In this case, two-bit data necessary for generating a horizontal conversion clock value needs to be stored in the flip-flop memory 587 only for the horizontal scanning valid period for horizontal conversion, and two necessary for vertical conversion only for the vertical scanning effective period for vertical conversion. This is done by storing bit data.

12A and 12C illustrate an internal structure of the image processor of FIG. 3, and may be divided into a horizontal processor and a vertical processor according to a method. If the horizontal conversion is performed during A / D or D / A conversion, the image is processed using only the vertical processor. You can also configure a processing part. That is, FIG. 12A is a case where horizontal conversion is performed by using a clock whose speed is controlled when reading the horizontal processing unit 602 which is a line memory, and then vertical conversion is performed using the vertical processing unit 603. FIG. In the case of horizontal conversion during A / D conversion, FIG. 12C illustrates a case in which horizontal conversion is performed by the output clock during D / A conversion.

Here, the horizontal conversion during A / D conversion converts the speed when writing to the field memory of the vertical processing unit 605. Thus, the horizontal conversion during the D / A conversion is performed by the vertical processing unit 607. This is the case as shown in Fig. 17A because the speed at the time of reading from the field memory of " Therefore, the opposite clock speed changes must occur to convert at the same rate.

FIG. 13 shows the configuration of the horizontal processing unit 602 shown in FIG. 12 for writing and reading horizontal scanning sections alternately to the line memories 608 and 609 for horizontal conversion.

FIG. 14 is a configuration of the vertical processing units 605 and 607 shown in FIGS. 12B to 12C, which alternately write and read each field using two pairs of field memories. Here, when the first field first memory 611 writes the input image in the horizontal direction and reads the second field first memory 616 in the vertical direction, the output of the first field first memory 611 is shown in FIG. 15B. To be: Then, when the image is rotated 90 degrees through the D / A converter 613 and the low pass filter 614, and then A / D converted again through the A / D converter 615, the effect of vertical resampling is obtained. have. In this case, depending on the speed of the vertical conversion clock, the number of lines may have a different number of output lines than the number of input lines. In this case, blanks may be generated at the top and bottom of the screen, or a part of the screen may not be visible. The vertical conversion clock is applied only to one of the D / A clock and A / D clock, and the normal clock is used for the other. Here, when the vertical conversion clock is used for the D / A conversion clock, it is the same as in FIG. 17A. When the vertical conversion clock is used for the A / D conversion clock, the same screen is vertically generated only when the opposite clock speeds are generated as shown in FIG. 17B. You can get the conversion form.

15 and 16 are diagrams illustrating how to vertically transform an image in the vertical processing units 605 and 607.

17A to 17D show a method of obtaining a deflection waveform in which a sawtooth wave having such an effect is obtained for understanding, when a clock capable of ratio conversion of an image is obtained by actually adding a clock control output and a normal clock value.

FIG. 2D illustrates an image obtained by converting an aspect ratio using a horizontal conversion clock obtained in FIG. 17D and a constant vertical conversion clock in a horizontal direction.

However, as shown in FIG. 6, if the clock speed is changed according to the horizontal section even in the vertical deflection, the vertical conversion clock speed is slowed down and accelerated according to the horizontal section. After passing through, as shown in FIG. 2F, the position of the vertical data is changed up and down even during the horizontal scan line. In this way, the image when the screen is vertically shifted up and down along the horizontal section is shown in Fig. 12F.

According to the present invention as described above, by varying the number of input clocks and the number of output clocks per hour over all sections or any section of the screen, such as CRT, by changing the number of pixels per line and the number of lines per field Can be. Therefore, the shape of the input image can be freely changed at any horizontal and vertical position of the screen.

Claims (16)

In an image display device for displaying an input image having an image size on a screen divided into a plurality of horizontal section or vertical section set in advance, A microprocessor for generating clock speed variation information for each block unit formed of an input image into the horizontal section and the vertical section; A bus decoder which receives, decodes and stores the clock speed change amount information; And a clock speed controller configured to determine a clock speed change amount of the horizontal and / or vertical conversion of the corresponding block in a preset order using the stored clock speed change amount information, and to control the horizontal and / or vertical clock conversion speed from the change amount. And an apparatus for converting a display ratio of a video signal. The apparatus of claim 1, wherein the clock speed conversion information output from the microprocessor is generated by an input signal of a user. The apparatus of claim 1, wherein the block is selected within 1 to 64 pixel units in the horizontal section and 1 to 64 line units in the vertical section. The pixel clock controller of claim 1, wherein the clock speed controller comprises: a pixel counter unit configured to determine a length of each horizontal section by a pixel clock output from the bus decoder; A horizontal clock speed control unit for controlling a horizontal clock speed by receiving a slope provided from the bus decoder or increase / decrease information on the slope; A horizontal clock value generator for generating a horizontal clock value by using a horizontal clock speed control signal and an input horizontal synchronization signal output from the horizontal clock speed controller; A horizontal clock generator which receives the output signal of the horizontal clock value generator and generates a horizontal clock signal; A vertical position counter unit for determining the length of each vertical section by a horizontal synchronization signal output from the bus decoder; A vertical clock speed controller configured to control a vertical clock speed based on a slope provided from the bus decoder or increase / decrease information on the slope; A vertical clock value generator for generating a vertical clock value using a vertical clock speed control signal and an input vertical synchronization signal output from the vertical clock speed controller; A vertical clock generator for receiving an output signal of the vertical clock value generator and generating a vertical clock signal; and And an image processing unit for converting and displaying the input image for each block according to the display ratio conversion value of the video signal output from the vertical clock generator. The method of claim 4, wherein the horizontal clock speed control unit to the vertical clock speed control unit At least one increase / decrease counter is provided to increase the current value when the increase is received by increasing or decreasing the slope provided by the bus decoder or the increase / decrease information on the slope. An apparatus for converting a display ratio of a video signal. 5. The horizontal and vertical clock counters of claim 4, wherein the horizontal clock clock generator generates a horizontal clock clock and a horizontal clock clock. Receiving the number of the horizontal or vertical clock to the point corresponding to the end of the image when the number is greater than the pre-stored horizontal or vertical length when the number is greater than the horizontal / vertical clock number comparison unit to return to the origin and write or read An apparatus for converting a display ratio of a video signal. 5. The image processing apparatus of claim 4, wherein the image processing unit comprises: a horizontal processing unit which writes the input image signal using a normal clock and reads the horizontal image by using a horizontal conversion clock; And a vertical processing unit for vertically converting the video signal output from the horizontal processing unit. The video signal processor of claim 4, wherein the image processor comprises an analog / digital converter for horizontally processing an input video signal and a vertical processor for vertically processing the video signal output from the analog / digital converter. Display ratio inverter. The image signal processor of claim 4, wherein the image processor comprises a digital / analog converter for vertically processing an input image signal, and a vertical processor for horizontally processing an image signal output from the digital / analog converter. Display ratio inverter. 8. The method of claim 7, wherein the vertical processing unit writes and reads each field alternately by using a pair of first and second field memories, and reads in the vertical direction when reading and writing an input image horizontally in the first field memory. A display ratio converting apparatus for a video signal. 2. The apparatus of claim 1, wherein the bus decoder stores at least one clock speed change amount and outputs horizontal and / or vertical clock signals for each block unit for horizontal and / or vertical sections. And a flop memory. 12. The apparatus of claim 11, wherein the flip-flop array or the flip-flop memory is a 2-bit field memory or a 2-bit line memory. The method of claim 1, wherein the clock speed variation information output from the microprocessor to the bus decoder is stored only during a horizontal scan valid period when the horizontal conversion is performed, and only during a vertical scan valid period when the vertical conversion is executed. A display ratio converting apparatus for a video signal. The data format of claim 1, wherein the data format of the clock speed change amount information comprises: a vertical / horizontal conversion display section for discriminating whether subsequent values are values to be applied to horizontal conversion or values to be applied to vertical conversion; A section definition display section for discriminating whether it belongs to a horizontal section or a vertical section of a horizontal to vertical transformation, A section number display section for indicating a selected section within a preset range, A slope display section for distinguishing whether or not to perform a conversion from read to write clock speeds; An increase / decrease display section for increasing or decreasing a slope of a clock speed according to the state of the slope display section; And an interval length display section for determining how many pixels and how many lines to maintain the same inclination with the current inclination. In an image display method for displaying an input image having an image size on a screen divided into a plurality of horizontal section or vertical section set in advance, Generating clock speed variation information for each block unit which is formed by overlapping the horizontal and vertical sections with an input image in a preset order; Receiving, decoding and storing the clock speed change amount information; Determining a clock speed change amount of a corresponding horizontal and / or vertical conversion in a preset order by using the stored clock speed change amount information, and controlling the horizontal and / or vertical clock conversion signal by the change amount. Method of converting display ratio of video signal. The method of claim 15, wherein the generating of the horizontal and / vertical conversion signal is Storing the clock speed change amount information; Determining a length of a horizontal section and / or a vertical section by receiving the clock speed change amount information; And generating a horizontal and / or vertical conversion signal by controlling a clock speed according to the slope included in the clock speed variation information and the increase / decrease information of the slope.