JPH11288257A - Method and device for compression display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display which is free from drop-out of picture elements and a device which doesn't require operation between data and has as small circuit scale as possible. SOLUTION: In the proposed compression display method which displays a picture by performing the number of picture elements conversion processing of a picture having a resolution higher than the number of picture elements which can be displayed, to m/n (m-1=n), one dot for n dots in the horizontal direction and one line for n lines in the vertical direction are set as thinning object positions in digital picture element signals, and first to n-th thinning object positions are successively changed in each at least one or more fields, and picture signals are thinned by a write control signal, and other remaining picture signals are written in a memory 33, and picture signals in this memory 33 are consecutively read out by a read control signal, thus performing the number of picture elements conversion processing. Thus, a data operation part is not required, and picture element conversion is realized by only controlling data write to the memory 33, and degradation of resolution is prevented because an original input signal is not subjected to any operation processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a video display device having a predetermined number of display pixels (for example, 640.times.480 dots) which has a higher resolution (for example, 800.times.600) than the displayable number of pixels of this device. The present invention relates to a compression display method and an apparatus for displaying a (dot) video by performing a pixel number conversion process using a digital signal processing technique.

[0002]

2. Description of the Related Art Generally, a plasma display panel (PDP) and a liquid crystal display (LCD) are display devices in which the number of display pixels is fixed, for example, 640 × 480 dots, 800 × 600 dots, or the like. For example, as shown in FIG. 7, the video display device 1 having a display pixel number of 640 × 480 dots and a low resolution is
800 × 60 with higher resolution than the number of displayable pixels of 1
When displaying the video 12 of the video display device 10 of 0 dots, a portion of the video 12 will be missing if left as it is. Such a lack of information is a fatal defect in monitors such as computer images.

Conventionally, when the number of display pixels and the number of pixels of a display video signal are different, the number of pixels of the input video signal in the horizontal and vertical directions is calculated by using digital signal processing, and the number of pixels of the display device is Several methods have been proposed to make the display the same.

An example of a conventional apparatus for compressing 800 × 600 dots into 640 × 480 dots, that is, 4/5 will be described with reference to FIGS. This conventional device,
It comprises a vertical processing unit 15, a horizontal processing unit 16 and a control unit 17. The vertical processing unit 15 includes a video input signal that is input from the video input terminal 13 and a line memory or the like.
The video input signal delayed by 1H in the H delay circuit 18 is sent to the pixel conversion circuit 19. Further, the horizontal processing unit 16 includes a 1D delay circuit 23 including a video input signal input from the memory 20 and a DFF (D-type flip-flop).
The video input signal delayed by the clock is sent to the pixel conversion circuit 24.

The pixel conversion circuit 19 and the pixel conversion circuit 24
Are based on the count values of the line counter 21 and the dot counter 26, respectively,
Based on a selection table value (operation coefficient table value) as shown in FIG. 8 (b) of FIG. 27, if a mixture ratio as shown in FIG. 1, '= × 3/4 + × １ ／,' =
× 1/2 + × 1/2, '= × １ ／ + × 3 /
An operation is performed on the data to be 4, and the data is stored in the memories 20 and 25, respectively.

[0006] The memories 20 and 25 are stored in a first-out (First)
-In), a first look-out (First-Out) memory, and among the data calculated by the pixel conversion circuits 19 and 24,
The WE signal from the conversion tables 22 and 27 controls the WE signal as shown in FIG. 8B to skip the pixel data at the thinning target position, and further outputs the RE signal from the output control circuit 28 as shown in FIG. , And ',', 'are read out continuously and repeatedly, thereby realizing a conversion process of the number of pixels.

[0007]

In the above-described image conversion processing by the conventional compression display method and the conventional apparatus, the number of pixels is reduced as compared with the case where one dot or one line is thinned to convert the number of pixels. It has the advantage of not missing,
Since the original input signal is subjected to arithmetic processing,
There is a problem that the resolution is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to obtain a circuit having the smallest possible circuit size without missing pixels and without performing calculations between data.

[0009]

According to the present invention, an image having a resolution higher than the number of displayable pixels is converted to m / n (m-1 = n) by digital signal processing technology. In the compressed display method for performing display, one dot is set as a thinning target position in the horizontal direction for every n dots and one line is set for every n lines in the digital pixel signal. The number of pixels is converted by sequentially changing from the first to the n-th for each field or more, thinning out with the write signal, writing other pixel signals to the memory, and continuously reading out the pixel signals of this memory with the read control signal. This is a compressed display method characterized by performing processing.

The output value from the dot counter 40 is sent to a selector 47 via a decoding circuit 45. The output from the field counter 42 moves one dot per n dots sequentially for each field to select a thinning position. You. Similarly, the output value from the line counter 41 is sent to the selector 48 via the decoded output, and the output from the field counter 42 moves one line per n lines every one field to select a thinning position. Outputs of the selectors 47 and 48 are output to a write signal output terminal 50 via an OR circuit 49, and a WE signal for data writing and thinning is output.

While this WE signal is High, line data is not written to the memory 33, and other data is
It is read continuously and data is output. The same applies to horizontal. In this case, the present invention realizes pixel conversion only by controlling data writing to the memory 33 without having a data operation unit as in the related art.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment (FIGS. 1, 2 and 3) In FIG. 1, a video signal input terminal 30 is first-in, first-in, and read-out via an A / D conversion circuit 32. (First-Out), and the like.
The memory 33 is connected to the video signal output terminal 31.

The control circuit 34 generates a synchronizing signal in accordance with the time axis conversion performed in the pixel number converting process, and a writing signal for generating a WE signal for controlling data writing and thinning out to the memory 33. It comprises a control circuit 38 and a read control circuit 39 for generating a read enable (RE) signal for continuously reading data written in the memory 33. For example, when the image of 800 × 600 dots is converted into the image of 640 × 480 dots, that is, when the image is compressed to 4/5 in the vertical and horizontal directions, the read control circuit 39 determines the period of the vertical and horizontal synchronization signals ( Frequency) is also set to 4/5.

On the input side of the synchronizing signal generation circuit 37,
A synchronizing signal input terminal 35 for inputting a horizontal synchronizing signal (HD) and a vertical synchronizing signal (VD) is coupled, and an output side of a synchronizing signal generation circuit 37 has an HD / VD synchronizing signal output terminal 36.
Are combined. Further, a write control circuit 38 and a read control circuit 39 are connected to the memory 33 to control writing and thinning of data with the WE signal of the write control circuit 38 and to read with the RE signal of the read control circuit 39. Control is performed.

A more detailed circuit of the write control circuit 38 is shown in FIG. 2, reference numeral 40 denotes a dot counter for counting the number of dots; 41, a line counter for counting the number of lines; 42, a field counter for counting the number of fields; 45, a decoding circuit for decoding the output value of the dot counter 40; 46, a decoding circuit for decoding the output value of the line counter 41; 47, a 5-1 selector for sequentially selecting one of five to one dots from the output of the decoding circuit 45 by the output of the field counter 42; A selector 5-1 for sequentially selecting one line from five lines based on the output of the field counter 42 is used as the output of the selector 46.
This is a two-input OR circuit that takes the logical OR of the outputs of the eight outputs. Reference numerals 43 and 44 denote inverters, respectively, and reference numeral 50 denotes a write signal output terminal.

The operation of the above configuration will be described.
V output from the synchronization signal generation circuit 37 shown in FIG.
The D signal is sent to the line counter 41, sent to the field counter 42 via the inverter 44, and output from the synchronization signal generation circuit 37 in FIG.
The HD signal shown in (b) is sent to the dot counter 40, and is sent to the line counter 4 via the inverter 43.
Sent to 1.

The output value from the dot counter 40 is decoded by a decoding circuit 45, and the decoded output is sent to a selector 47. The selector 47 sequentially selects one dot at a time for each of the first to second dots, etc., from each output in which the first to fifth dots are set as one unit by a select signal for each field from the field counter 42. Is done. Similarly, the output value from the line counter 41 is decoded by the decode circuit 46, and the decoded output is sent to the selector 48. In this selector 48, the 1st to 5th lines are changed to 1 line by a select signal for each field from the field counter 42.
.. Are sequentially selected line by line for thinning, such as first, second,. The dot output of the selector 47 and the line output of the selector 48 are sent to a write signal output terminal 50 via an OR circuit 49, and
As shown in (c), a WE signal for data writing and thinning is output.

While this WE signal is High, the line data is not written to the memory 33, and the other data is
The data is continuously read and data is output as shown in FIG. The same applies to horizontal. In this case, in the present invention, the pixel conversion is realized only by controlling the writing and reading of the data to and from the memory 33 without having the conventional data operation unit. In the case of compression to 4/5, reading is performed by 1 line × 1/1 in the horizontal direction rather than writing so that reading does not overtake writing.
It is necessary to delay by 5 (120 dots) or more.

FIG. 3E shows an example of a display compressed by the above output data. That is, field 1
Are thinned out and the dot portions of 1, 6, 10,... And the line portions of 1, 6, 10,. In field 2,
Each of the hatched portions of 2, 7, 11,...
Each line portion of 7, 11,... Is thinned out and compressed so that there is no hatched portion. In the field 3 and subsequent fields as well, thinning is sequentially performed for each field.

As described above, when four dots are generated from five dots, the four dots display the input video signal as it is, and only one dot is displayed by switching the thinning position for each field. The reason why the thinning-out position is switched for each field is that if the thinning-out position is changed for each line in the horizontal direction, the vertical line is not displayed in a straight line.

In the embodiment shown in FIG. 2, the positions of thinning out dots in the horizontal direction and the positions of thinning out lines in the vertical direction are switched for each field. However, the present invention is not limited to this example. By changing the signal for thinning out from the field counter 42 in FIG.
Alternatively, the number of fields to be thinned out may be changed, for example, for each of a plurality of fields, and the line thinning position in the vertical direction may be set for every one or a plurality of fields.

FIG. 5 shows another embodiment of the present invention. In the embodiment shown in FIGS. 2 and 4, by setting the decoding circuits 45 and 46, 5 dots in the horizontal direction and 5 lines in the vertical direction are set as one unit, and the second, third, fourth, and fifth are sequentially from the first. In the process of returning to the first position again. Therefore, the image fluctuates in units of 5 dots × 5 lines. Therefore, in the embodiment shown in FIG. 5, of the unit of 5 dots × 5 lines, only two dots and two lines adjacent to each other are alternately thinned out, and the other three dots and three lines are fixed.

More specifically, the decoding circuits 45 and 46 set 5 dots in the horizontal direction and 5 lines in the vertical direction as one unit, the first, second, and third are fixed, and the fourth and fifth are fixed.
6 and 7 are alternately thinned out for each field. FIGS. 6A and 6B are explanatory diagrams of pixel conversion operations at that time.
(C), (d) and (e) are shown. In this case, the fourth and fifth
Although the thinning is performed alternately as a pair, the processing may be performed as a pair of the first and second, the second and third, or the third and fourth.

[0024]

According to the first aspect of the present invention, the pixel data at the position to be decimated from the digital pixel signals is decimated by the write control signal, and the other pixel signals are written into the memory, and the pixel signals in this memory are read out. Since the signals are continuously read, a complicated arithmetic circuit such as a pixel conversion circuit is not required, and the circuit can be simplified and provided at a low cost.

According to the present invention, one dot is set for every n dots in the horizontal direction and one line is set for every n lines in the digital pixel signal, and the position to be thinned is at least one field or more. The number of pixels is converted by sequentially changing from the first to the nth every time, thinning out other pixel signals with a write control signal and writing the pixel signals of this memory continuously with a read control signal. Is performed, the arithmetic processing is not performed on the original input signal, and the resolution can be prevented from deteriorating.

According to a third aspect of the present invention, one dot is set for every n dots in the horizontal direction and one line is set for every n lines in the digital pixel signal. By alternately changing only two adjacent dots every time, thinning out with a write control signal, writing the other pixel signals as they are into the memory, and continuously reading out the pixel signals of this memory with the readout control signal, the number of pixels is reduced. Is performed, it is possible to prevent the image from fluctuating in units of n dots × n lines.

[Brief description of the drawings]

FIG. 1 is a first embodiment of a compressed display method and apparatus according to the present invention;
It is a block diagram showing an example.

FIG. 2 is a detailed block diagram of a write control circuit 38 in FIG.

FIG. 3 is an operation waveform diagram and an operation explanatory diagram in FIG. 1;

FIG. 4 is a block diagram showing a modification of FIG. 2;

FIG. 5 is a second view of a compressed display method and apparatus according to the present invention.
It is a block diagram showing an example.

FIG. 6 is an operation waveform diagram and an operation explanatory diagram in FIG. 5;

FIG. 7 is an image 12 having a higher resolution than the number of displayable pixels.
FIG. 4 is an explanatory diagram of a defect that occurs when “.

FIG. 8 is an explanatory diagram for describing a conventional compressed display method and a conventional apparatus when the number of display pixels and the number of pixels of a display video signal are different.

FIG. 9 is a conventional compressed display method and apparatus for realizing FIG. 8;

[Explanation of symbols]

10: High-resolution image display device, 11: Low-resolution image display device, 12: Video, 13: Video input terminal, 14
... video output terminal, 15 ... vertical processing unit, 16 ... horizontal processing unit, 17 ... control unit, 18 ... 1H delay circuit, 19 ... pixel conversion circuit, 20 ... memory, 21 ... line counter, 22 ...
Conversion table, 23 1D delay circuit, 24 pixel conversion circuit, 25 memory, 26 dot counter, 27 conversion table, 28 output control circuit, 30 video signal input terminal, 31 video signal output terminal, 32 ... A / D conversion circuit,
33 ... memory, 34 ... control circuit, 35 ... sync signal input terminal, 36 ... sync signal output terminal, 37 ... sync signal generation circuit, 38 ... write control circuit, 39 ... read control circuit,
40 ... dot counter, 41 ... line counter, 42 ...
Field counter, 43 inverter, 44 inverter, 45 decode circuit, 46 decode circuit, 47
... selector, 48 ... selector, 49 ... OR circuit, 50 ...
Write signal output terminal.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI G09G 3/20 660 G09G 3/36 3/36 5/18 5/18 H04N 1/387 101 H04N 1/387 101 5/66 Z 5/66 G06F 15/66 355D

Claims (7)

[Claims] 1. A compression display method for displaying an image having a resolution higher than the number of displayable pixels by performing a pixel number conversion process using a digital signal processing technique. The pixel data is decimated by a write control signal, the other pixel signals are written to a memory, and the pixel signals in the memory are read continuously by a read control signal, thereby performing a conversion process of the number of pixels. The compression display method to be used. 2. An image having a resolution higher than the number of pixels that can be displayed is converted to m / n (m-1 = m-1) using digital signal processing technology.
In the compression display method for performing the pixel number conversion process to n) for display, one dot is set for every n dots in the horizontal direction and one line is set for every n lines in the digital pixel signal as a thinning target position. Then, the thinning target position is sequentially changed from the first to the nth at least every one field or more, thinned by a write control signal, and the other pixel signals are written to the memory, and the pixel signals of this memory are continuously read by the read control signal. A compression display method, wherein a conversion process of the number of pixels is performed by reading the data in a compressed manner. 3. An image having a resolution higher than the number of displayable pixels is converted to m / n (m-1 = 1) using digital signal processing technology.
In the compression display method for performing the pixel number conversion process to n) for display, one dot is set for every n dots in the horizontal direction and one line is set for every n lines in the digital pixel signal as a thinning target position. Only the two dots adjacent to each other are alternately changed at least every one field or more in this thinning target position, and the other pixel signals are written to the memory by thinning out with the write control signal, and the pixel signals of this memory are read out by the read control signal. By reading continuously with
A compressed display method, wherein a conversion process of the number of pixels is performed. 4. A compression display device for displaying an image having a higher resolution than the number of displayable pixels by performing a pixel number conversion process using a digital signal processing technique, a memory 33 for storing digital pixel signals, And a control circuit 34 for controlling writing and reading of digital pixel signals to and from the memory 33. The control circuit 34 generates a synchronizing signal to generate a synchronizing signal in accordance with the time axis conversion performed in the pixel number conversion processing. A circuit 37; a write control circuit 38 for controlling data writing and thinning-out to the memory 33 based on a synchronization signal of the synchronization signal generation circuit 37; and a write control circuit 38 for controlling the memory 33 based on a synchronization signal of the synchronization signal generation circuit 37. And a read control circuit 39 for generating a read control signal for continuously reading the written data. Apparatus. 5. A compression display device for displaying an image having a resolution higher than the number of displayable pixels by performing a pixel number conversion process using a digital signal processing technique, and a memory 33 for storing digital pixel signals. A control circuit 34 for controlling writing and reading of digital pixel signals to and from the memory 33. The control circuit 34 generates a synchronization signal for generating a synchronization signal in accordance with the time axis conversion performed in the pixel number conversion processing. A circuit 37; a write control circuit 38 for controlling the writing and thinning-out of data in the memory 33 based on the synchronization signal of the synchronization signal generation circuit 37; and the memory 33 based on the synchronization signal of the synchronization signal generation circuit 37. A read control circuit 39 for generating a read control signal for continuously reading the written data; , The dot counter 40 for counting the number of dots on the basis of the horizontal synchronizing signal from the synchronizing signal generating circuit 37
A line counter 41 for counting the number of lines based on the horizontal and vertical synchronization signals from the synchronization signal generation circuit 37;
A field counter 42 for counting the number of fields based on the vertical synchronization signal from the synchronization signal generation circuit 37, and a decoding circuit 45 for decoding the output value of the dot counter 40 for sequentially changing the positions to be thinned out in the horizontal direction.
A decoding circuit 46 for decoding the output value of the line counter 41 in order to sequentially change the position of the thinning target in the vertical direction, and the position of the thinning target in the horizontal direction based on the output of the decoding circuit 45 and the output of the field counter 42. A selector 47 for selecting, a selector 48 for selecting a thinning target position in the vertical direction from an output of the decoding circuit 46 with an output of the field counter 42, and a two-input OR for obtaining a logical sum of outputs of the selector 47 and the selector 48. A compression display device comprising a circuit 49. 6. An image having a resolution higher than the number of displayable pixels is converted to m / n (m-1 = m-1) using a digital signal processing technique.
In the compression display device for performing the pixel number conversion process to n) and displaying, the selector 47 and the selector 48 are selected so as to sequentially change the thinning target position from the first to the nth for each field. 6. The method according to claim 5, wherein
The compressed display device as described in the above. 7. An image having a resolution higher than the number of displayable pixels is converted to m / n (m-1 = m-1) using digital signal processing technology.
In the compressed display device for performing the pixel number conversion process to n) for display, the selector 47 and the selector 48 select the thinning target positions so that only two dots adjacent to each other are alternately changed for each field. 6. The compressed display device according to claim 5, wherein: