[go: up one dir, main page]

KR100253344B1 - Contact hole formation method of semiconductor memory - Google Patents

Contact hole formation method of semiconductor memory Download PDF

Info

Publication number
KR100253344B1
KR100253344B1 KR1019970058509A KR19970058509A KR100253344B1 KR 100253344 B1 KR100253344 B1 KR 100253344B1 KR 1019970058509 A KR1019970058509 A KR 1019970058509A KR 19970058509 A KR19970058509 A KR 19970058509A KR 100253344 B1 KR100253344 B1 KR 100253344B1
Authority
KR
South Korea
Prior art keywords
oxide film
thermal oxide
mos transistor
film
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019970058509A
Other languages
Korean (ko)
Other versions
KR19990038682A (en
Inventor
문영호
Original Assignee
김영환
현대반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대반도체주식회사 filed Critical 김영환
Priority to KR1019970058509A priority Critical patent/KR100253344B1/en
Publication of KR19990038682A publication Critical patent/KR19990038682A/en
Application granted granted Critical
Publication of KR100253344B1 publication Critical patent/KR100253344B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체 메모리의 콘택홀 형성방법에 관한 것으로, 종래 반도체 메모리의 콘택홀 형성방법은 필드산화막의 새부리영역에 의해 콘택의 면적이 줄어들게 되어 모스 트랜지스터의 소스가 완전히 노출되지 않아 이후에 형성하는 캐패시터와의 콘택저항이 증가하여 반도체 메모리의 특성이 저하되는 문제점이 있었다. 이와 같은 문제점을 감안한 본 발명은 모스 트랜지스터가 제조된 기판의 상부에 제 1열산화막, 질화막, 제 2열산화막을 순차적으로 증착하는 단계와; 상기 제 2열산화막의 상부에 두꺼운 제 3열산화막을 증착하고, 상기 제 3열산화막의 일부를 식각하여 상기 제 2열산화막의 일부를 노출시키는 단계와; 상기 노출된 제 2열산화막과 그 하부의 질화막, 제 1열산화막을 이온주입의 버퍼로 사용하는 이온주입공정으로 상기 모스 트랜지스터의 소스에 불순물이온을 주입하는 단계와; 상기 제 2열산화막, 질화막, 제 1열산화막을 선택적으로 식각하여 상기 모스 트랜지스터의 소스를 노출시키는 단계로 구성되어 상기 제 1열산화막, 질화막, 제 2열산화막을 통해 콘택저항을 감소시키기 위한 불순물 이온을 주입하여 그 구조를 약화시켜, 이온주입의 버퍼로 사용되지 않은 제 1열산화막, 질화막, 제 2열산화막의 다른 부분들에 비해 쉽게 식각되도록 하여 원하는 면적의 소스를 노출시켜 이후에 형성하는 캐패시터와의 접속을 용이하게 하여 전체적인 반도체 메모리의 특성을 향상시키는 효과가 있다.The present invention relates to a method of forming a contact hole in a semiconductor memory. In the conventional method of forming a contact hole in a semiconductor memory, a contact area is reduced by a new bevel region of a field oxide film so that a source of a MOS transistor is not completely exposed and a capacitor is formed later. There is a problem that the characteristics of the semiconductor memory are deteriorated due to an increase in the contact resistance between and. In view of the above problems, the present invention includes the steps of sequentially depositing a first thermal oxide film, a nitride film, and a second thermal oxide film on the substrate on which the MOS transistor is manufactured; Depositing a thick third thermal oxide film on the second thermal oxide film, and etching a portion of the third thermal oxide film to expose a portion of the second thermal oxide film; Implanting impurity ions into the source of the MOS transistor by an ion implantation process using the exposed second thermal oxide film, a nitride film below it, and the first thermal oxide film as an ion implantation buffer; Selectively etching the second thermal oxide film, the nitride film, and the first thermal oxide film to expose the source of the MOS transistor to reduce the contact resistance through the first thermal oxide film, the nitride film, and the second thermal oxide film. By implanting ions, the structure is weakened, and is easily etched compared to other parts of the first thermal oxide film, the nitride film, and the second thermal oxide film, which are not used as buffers for ion implantation, thereby exposing a source having a desired area to form later. There is an effect of facilitating the connection with the capacitor to improve the characteristics of the overall semiconductor memory.

Description

반도체 메모리의 콘택홀 형성방법Contact hole formation method of semiconductor memory

본 발명은 반도체 메모리의 콘택홀 형성방법에 관한 것으로, 특히 콘택홀을 형성할 절연막에 이온을 주입하여 그 절연막을 약화시킨 후, 플라즈마 식각법을 이용하여 그 약화된 절연막의 일부를 식각함으로써, 정확한 콘택홀을 형성하는데 적당하도록 한 반도체 메모리의 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact hole in a semiconductor memory, and more particularly, by implanting ions into an insulating film to form a contact hole to weaken the insulating film, and then etching a part of the weakened insulating film by using a plasma etching method. A method for forming a contact hole in a semiconductor memory suitable for forming a contact hole.

일반적으로, 반도체소자의 콘택홀은 기판에 형성한 반도체 소자의 상부에 절연막을 증착하고, 그 절연막을 사진식각공정을 통해 선택적으로 식각하여 상기 반도체 소자의 특정영역을 외부로 노출시키기 위한 구멍을 의미하며, 금속공정시 금속배선과 반도체 소자의 특정영역을 접합시키거나, 캐패시터 등 면적이 큰 반도체 소자를 기판에 형성하지 않고 기 제조한 반도체 소자와는 절연층을 사이에 두고 상부에 제조하기 위해 형성한다. 콘택홀은 사진식각공정에서의 정밀한 마스크 정렬과 절연막을 식각하는 공정에서의 식각종료점 검출이 중요한 기술적 해결과제이며, 이와 같은 종래 반도체 메모리의 콘택홀 형성방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In general, a contact hole of a semiconductor device is a hole for depositing an insulating film on the semiconductor device formed on the substrate, and selectively etching the insulating film through a photolithography process to expose a specific region of the semiconductor device to the outside. It is formed to join a metal wiring and a specific region of a semiconductor device during metal processing, or to manufacture a semiconductor device having a large area such as a capacitor on a substrate with an insulating layer interposed therebetween. do. The contact hole is an important technical problem for precise mask alignment in the photolithography process and the detection of the etching end point in the process of etching the insulating film. Referring to the accompanying drawings, the method for forming a contact hole in the conventional semiconductor memory will be described in detail below. Same as

도1a 및 도1b는 종래 반도체 메모리의 콘택홀 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 필드산화막(2)을 형성하여 반도체 소자가 제조될 영역을 정의하고, 그 반도체 소자가 제조될 영역에 모스 트랜지스터(3)를 제조한 다음, 상기 필드산화막(2) 및 모스 트랜지스터(3)의 상부에 열산화막(4), 질화막(5), 열산화막(6)을 순차적으로 증착하는 단계(도1a)와; 상기 증착한 열산화막(6)의 상부에 두껍고 그 상부가 평탄한 열산화막(7)을 증착한 후, 사진식각공정을 통해 상기 열산화막(7)의 일부를 식각하여 상기 모스 트랜지스터(3)의 소스를 노출시키고, 상기 열산화막(7)을 모두 제거하는 단계(도1b)로 이루어진다.1A and 1B are cross-sectional views of a process for manufacturing a contact hole in a conventional semiconductor memory. As shown in FIG. 1, a field oxide film 2 is formed on a substrate 1 to define a region in which a semiconductor device is to be manufactured. After manufacturing the MOS transistor 3 in the region where the device is to be manufactured, the thermal oxide film 4, the nitride film 5, and the thermal oxide film 6 are sequentially disposed on the field oxide film 2 and the MOS transistor 3. Depositing (FIG. 1A); After depositing a thick and flat thermal oxide film 7 on the deposited thermal oxide film 6, a portion of the thermal oxide film 7 is etched through a photolithography process to source the MOS transistor 3. Exposing and removing all of the thermal oxide film 7 (FIG. 1B).

이하, 상기와 같이 구성된 종래 반도체 메모리의 콘택홀 형성방법을 좀 더 상세히 설명한다.Hereinafter, a method of forming a contact hole in a conventional semiconductor memory configured as described above will be described in more detail.

먼저, 도1a에 도시한 바와 같이 기판(1)의 상부에 필드산화막(2)을 로코스(LOCOS)공정을 통해 제조한다. 이와 같이 로코스공정을 통해 필드산화막(2)을 증착하는 경우, 그 필드산화막(2)의 측면부는 새부리모양을 갖게 됨은 알려진 바와 같다.First, as shown in FIG. 1A, a field oxide film 2 is manufactured on a substrate 1 through a LOCOS process. As described above, when the field oxide film 2 is deposited through the LOCOS process, it is known that the side portion of the field oxide film 2 has a beak shape.

그 다음, 상기 필드산화막(2)의 사이에 노출된 기판에 모스 트랜지스터(3)를 제조하고, 그 모스 트랜지스터(3)의 게이트 형성과 동시에 필드산화막(2)의 상부에 게이트(부호생략)를 형성하며, 이는 모스 트랜지스터(2)의 게이트와 단차를 줄이는 역할을 하게 된다.Next, a MOS transistor 3 is fabricated on the substrate exposed between the field oxide films 2, and a gate (not shown) is formed on the field oxide film 2 at the same time as the gate of the MOS transistor 3 is formed. This serves to reduce the gate and the step of the MOS transistor 2.

그 다음, 상기 모스 트랜지스터(3)와 필드산화막(2) 및 그 필드산화막(2)의 상부에 형성한 게이트의 상부전면에 고온저압의 증착분위기에서 산화막을 증착하는 열산화막(4)을 증착하고, 그 열산화막(4)의 상부에 질화막(5), 열산화막(6)을 순차적으로 증착한다. 이와 같이 산화막, 질화막, 산화막이 적층된 절연층을 보통 ONO구조의 절연층이라하며, 이는 일반 산화막보다 절연성이 우수하고, 식각율을 달리하는 질화막을 포함하여 선택적식각이 어느 정도 가능한 특징이 있어 많이 사용되고 있다.Then, a thermal oxide film 4 is deposited on the MOS transistor 3, the field oxide film 2, and the upper surface of the gate formed on the field oxide film 2 in the deposition atmosphere at high temperature and low pressure. The nitride film 5 and the thermal oxide film 6 are sequentially deposited on the thermal oxide film 4. In this way, the insulating layer in which the oxide film, the nitride film, and the oxide film are stacked is generally called an insulating layer having an ONO structure, which is characterized by being more insulating than the general oxide film and having a selective etching ability to some extent including a nitride film having a different etching rate. It is used.

그 다음, 도1b에 도시한 바와 같이 상기 열산화막(6)의 상부에 열산화막(7)을 두껍게 증착한다. 이때 최초 증착된 열산화막(7)의 상부는 평탄하지 않으므로, 사진식각공정을 진행할 때, 조사되는 광의 초점이 맞지 않게 되어 정확한 패턴을 얻을 수 없으므로, 평탄화공정을 통해 그 열산화막(7)의 상부를 평탄화한다.Then, as shown in FIG. 1B, a thermal oxide film 7 is thickly deposited on top of the thermal oxide film 6. At this time, since the upper portion of the thermally oxidized film 7 deposited first is not flat, when the photolithography process is performed, the irradiated light is not focused and an accurate pattern cannot be obtained. Therefore, the upper portion of the thermal oxide film 7 is planarized. Planarize.

그 다음, 상기 상부가 평탄한 열산화막(7)의 상부에 포토레지스트(도면 생략)를 도포하고, 노광 및 현상하여 패턴을 형성하고, 그 패턴이 형성된 포토레지스트를 식각 마스크로 하는 습식식각공정으로 상기 열산화막(7)의 일부를 식각하고, 그 열산화막이 식각되는 부분의 열산화막(6), 질화막(5), 열산화막(4)을 식각하여 상기 모스 트랜지스터(3)의 소스를 노출시킨다.Next, a photoresist (not shown) is applied to the upper portion of the thermally oxidized film 7 having a flat top, and exposed and developed to form a pattern, and the wet etching process uses the photoresist on which the pattern is formed as an etching mask. A portion of the thermal oxide film 7 is etched, and the thermal oxide film 6, the nitride film 5, and the thermal oxide film 4 in the portion where the thermal oxide film is etched are etched to expose the source of the MOS transistor 3.

이때, 상기 필드산화막(2)의 측면부인 새부리영역의 영향으로 콘택홀의 단면적이 작아지게 되며, 이에 따라 콘택홀이 정확히 형성되지 않는 콘택 낫 오픈(CONTACT NOT OPEN)현상이 발생하는 경우가 있다.At this time, the cross-sectional area of the contact hole is reduced due to the influence of the beak region, which is a side part of the field oxide film 2, and thus a contact sick open phenomenon may occur in which the contact hole is not formed accurately.

이후의 공정으로는 상기 노출된 소스에 콘택저항을 줄이기 위한 이온주입을 실시하고, 그 소스에 접속되는 캐패시터를 제조하게 된다.In the subsequent process, ion implantation is performed to reduce the contact resistance of the exposed source, and a capacitor connected to the source is manufactured.

상기한 바와 같이 종래 반도체 메모리의 콘택홀 형성방법은 필드산화막의 측면부인 새부리영역에 의해 콘택의 면적이 줄어들게 되어 모스 트랜지스터의 소스가 완전히 노출되지 않아 이후에 형성하는 캐패시터와의 콘택저항이 증가하거나, 심한 경우 접속이 이루어 지지 않아 반도체 메모리를 사용할 수 없는 문제점이 있었다.As described above, in the conventional method of forming a contact hole in a semiconductor memory, the contact area is reduced by a bird beak region, which is a side portion of the field oxide film, so that the source of the MOS transistor is not completely exposed, thereby increasing the contact resistance with a capacitor formed later. In severe cases, there was a problem that the semiconductor memory could not be used because the connection was not made.

이와 같은 문제점을 감안한 본 발명은 모스 트랜지스터의 소스를 원하는 면적만큼 용이하게 노출시키는 반도체 메모리의 콘택홀 형성방법을 제공함에 그 목적이 있다.In view of the above problems, an object of the present invention is to provide a method for forming a contact hole in a semiconductor memory which easily exposes a source of a MOS transistor by a desired area.

도1a 및 도1b는 종래 반도체 메모리의 콘택홀 제조공정 수순단면도.1A and 1B are cross-sectional views of a process for manufacturing a contact hole in a conventional semiconductor memory.

도2a 내지 도2c는 본 발명 반도체 메모리의 콘택홀 제조공정 수순단면도.2A to 2C are cross-sectional views of a process for manufacturing a contact hole in a semiconductor memory of the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

1:기판 2:필드산화막1: Substrate 2: Field Oxide

3:모스 트랜지스터 4,6,7:열산화막3: MOS transistor 4,6,7: thermal oxide film

5:질화막5: nitride film

상기와 같은 목적은 모스 트랜지스터가 제조된 기판의 상부에 제 1열산화막, 질화막, 제 2열산화막을 순차적으로 증착하는 ONO구조 절연층 형성단계와; 상기 제 2열산화막의 상부에 두꺼운 제 3열산화막을 증착하고, 사진식각공정을 통해 상기 제 3열산화막의 일부를 식각하여 상기 제 2열산화막의 일부를 노출시키는 ONO구조 절연층 노출단계와; 상기 노출된 제 2열산화막과 그 하부의 질화막, 제 1열산화막을 이온주입의 버퍼로 사용하는 이온주입공정으로 상기 모스 트랜지스터의 소스에 불순물이온을 주입하는 이온주입단계와; 상기 제 2열산화막, 질화막, 제 1열산화막을 선택적으로 식각하여 상기 모스 트랜지스터의 소스를 노출시키는 소스 노출단계로 구성되어 상기 제 1열산화막, 질화막, 제 2열산화막을 통해 콘택저항을 감소시키기 위한 불순물 이온을 주입하여 그 구조를 약화시켜, 이온주입의 버퍼로 사용되지 않은 제 1열산화막, 질화막, 제 2열산화막의 다른 부분들에 비해 쉽게 식각되도록 함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is an ONO structure insulating layer forming step of sequentially depositing a first thermal oxide film, a nitride film, a second thermal oxide film on the substrate on which the MOS transistor is manufactured; An ONO structure insulating layer exposing step of depositing a thick third thermal oxide film on the second thermal oxide film and etching a portion of the third thermal oxide film through a photolithography process to expose a portion of the second thermal oxide film; An ion implantation step of implanting impurity ions into the source of the MOS transistor by an ion implantation process using the exposed second thermal oxide film, a nitride film below it, and a first thermal oxide film as an ion implantation buffer; Selectively etching the second thermal oxide film, the nitride film, and the first thermal oxide film to expose a source of the MOS transistor to reduce contact resistance through the first thermal oxide film, the nitride film, and the second thermal oxide film. This is achieved by injecting impurity ions for the purpose of weakening the structure, and making it easier to etch than other parts of the first thermal oxide film, the nitride film, and the second thermal oxide film, which are not used as an ion implantation buffer. When described in detail with reference to the accompanying drawings as follows.

도2a 내지 도2c에 도시한 바와 같이 기판(1)의 상부에 필드산화막(2)을 형성하여 반도체 소자가 제조될 영역을 정의하고, 그 반도체 소자가 제조될 영역에 모스 트랜지스터(3)를 제조한 다음, 상기 필드산화막(2) 및 모스 트랜지스터(3)의 상부에 열산화막(4), 질화막(5), 열산화막(6)을 순차적으로 증착하는 단계(도2a)와; 상기 증착한 열산화막(6)의 상부에 두껍고 그 상부가 평탄한 열산화막(7)을 증착한 후, 사진식각공정을 통해 상기 열산화막(7)의 일부를 식각하여 상기 열산화막(6)의 일부를 노출시키고, 그 열산화막(6)과 하부의 질화막(5), 열산화막(4)을 이온주입의 버퍼로 사용하여 상기 모스 트랜지스터(3)의 소스에 이온을 주입하는 단계(도2b)와; 상기 노출된 열산화막(6)과 그 하부의 질화막(5), 열산화막(4)을 식각하여 상기 이온이 주입된 모스 트랜지스터(3)의 소스영역을 노출시키고, 상기 열산화막(7)을 제거하는 단계(도2c)로 이루어진다.2A to 2C, a field oxide film 2 is formed on the substrate 1 to define a region where a semiconductor device is to be manufactured, and a MOS transistor 3 is manufactured in the region where the semiconductor device is to be manufactured. Then depositing a thermal oxide film 4, a nitride film 5, and a thermal oxide film 6 sequentially on the field oxide film 2 and the MOS transistor 3 (FIG. 2A); After depositing a thermal oxide film 7 having a thick and flat top on the deposited thermal oxide film 6, a portion of the thermal oxide film 7 is etched through a photolithography process to etch a portion of the thermal oxide film 6. Exposing ions to the source of the MOS transistor 3 using the thermal oxide film 6, the lower nitride film 5 and the thermal oxide film 4 as ion implantation buffers (FIG. 2B); ; The exposed thermal oxide film 6, the nitride film 5 and the thermal oxide film 4 below are etched to expose the source region of the MOS transistor 3 into which the ions are implanted, and the thermal oxide film 7 is removed. It consists of a step (Fig. 2c).

이하, 상기와 같이 구성된 본 발명 반도체 메모리의 콘택홀 형성방법을 좀 더 상세히 설명한다.Hereinafter, a method of forming a contact hole in the semiconductor memory of the present invention configured as described above will be described in more detail.

먼저, 도2a에 도시한 바와 같이 기판(1)의 상부에 필드산화막(2)을 로코스(LOCOS)공정을 통해 제조한다. 이와 같이 로코스공정을 통해 필드산화막(2)을 증착하는 경우, 그 필드산화막(2)의 측면부는 새부리모양을 갖게 됨은 알려진 바와 같다.First, as shown in FIG. 2A, a field oxide film 2 is manufactured on a substrate 1 through a LOCOS process. As described above, when the field oxide film 2 is deposited through the LOCOS process, it is known that the side portion of the field oxide film 2 has a beak shape.

그 다음, 상기 필드산화막(2)의 사이에 노출된 기판에 모스 트랜지스터(3)를 제조하고, 그 모스 트랜지스터(3)의 게이트 형성과 동시에 필드산화막(2)의 상부에 게이트(부호생략)를 형성하며, 이는 모스 트랜지스터(2)의 게이트와 단차를 줄이는 역할을 하게 된다.Next, a MOS transistor 3 is fabricated on the substrate exposed between the field oxide films 2, and a gate (not shown) is formed on the field oxide film 2 at the same time as the gate of the MOS transistor 3 is formed. This serves to reduce the gate and the step of the MOS transistor 2.

그 다음, 상기 모스 트랜지스터(3)와 필드산화막(2) 및 그 필드산화막(2)의 상부에 형성한 게이트의 상부전면에 열산화막(4), 질화막(5), 열산화막(6)을 순차적으로 증착한다.Then, the thermal oxide film 4, the nitride film 5, and the thermal oxide film 6 are sequentially disposed on the MOS transistor 3, the field oxide film 2, and the upper surface of the gate formed on the field oxide film 2. To be deposited.

그 다음, 도2b에 도시한 바와 같이 상기 열산화막(6)의 상부에 열산화막(7)을 두껍게 증착하고, 그 상부를 평탄화시킨다.Then, as shown in Fig. 2B, a thermal oxide film 7 is thickly deposited on the thermal oxide film 6, and the top thereof is planarized.

그 다음, 상기 상부가 평탄한 열산화막(7)의 상부에 포토레지스트(도면 생략)를 도포하고, 노광 및 현상하여 패턴을 형성하고, 그 패턴이 형성된 포토레지스트를 식각 마스크로 하는 습식식각공정으로 상기 열산화막(7)의 일부를 식각하여 열산화막(6)의 일부를 노출시킨다.Next, a photoresist (not shown) is applied to the upper portion of the thermally oxidized film 7 having a flat top, and exposed and developed to form a pattern, and the wet etching process uses the photoresist on which the pattern is formed as an etching mask. A portion of the thermal oxide film 7 is etched to expose a portion of the thermal oxide film 6.

그 다음, 상기 노출된 열산화막(6)과 그 하부의 질화막(5), 열산화막(4)을 이온주입의 버퍼로 사용하는 이온주입공정으로 상기 모스 트랜지스터(3)의 소스에 불순물 이온을 주입한다. 이때 주입되는 불순물 이온은 소스의 타입과 동일한 것을 사용하며, 콘택저항을 줄이기 위해 고농도로 주입한다.Then, impurity ions are implanted into the source of the MOS transistor 3 by an ion implantation process using the exposed thermal oxide film 6, the nitride film 5 below and the thermal oxide film 4 as an ion implantation buffer. do. At this time, the implanted impurity ions are the same as the source type, and implanted at a high concentration to reduce contact resistance.

이와 같이 고농도의 불순물 이온주입공정을 실시하면 이온주입의 버퍼로 사용되는 상기 열산화막(6), 질화막(5), 열산화막(4) 적층구조는 이온주입에 의한 결합에 손상을 입게되어 약화된다.As a result of the high concentration impurity ion implantation, the thermal oxide film 6, nitride film 5, and thermal oxide film 4 stacked structures used as buffers for ion implantation are damaged and weakened by the ion implantation. .

그 다음, 도2c에 도시한 바와 같이 플라즈마 식각법을 이용하여 상기 결정구조에 손상이 생겨 약화된 열산화막(6), 질화막(5)을 플라즈마 식각법으로 식각하고, 열산화막(4)을 습식식각법으로 식각하여 상기 모스 트랜지스터(3)의 소스를 외부로 노출시키고, 상기 열산화막(7)을 모두 제거하여 콘택홀 형성을 완료한다. 이때, 이온주입버퍼로 사용한 열산화막(4)은 이온주입버퍼로 사용하지 않은 열산화막(4)에 비해 식각율이 좋아 선택적식각이 가능하며, 이에 따라 원하는 면적만큼의 소스를 노출시키게 된다.Then, as shown in FIG. 2C, the thermal oxide film 6 and the nitride film 5, which are damaged due to damage to the crystal structure by using the plasma etching method, are etched by the plasma etching method, and the thermal oxide film 4 is wetted. Etching is performed to expose the source of the MOS transistor 3 to the outside, and the thermal oxide film 7 is removed to complete contact hole formation. At this time, the thermal oxide film 4 used as the ion implantation buffer has a good etching rate compared to the thermal oxide film 4 not used as the ion implantation buffer, and thus selective etching is possible, thereby exposing a source having a desired area.

이와 같이, 상기 콘택홀을 형성한 이후의 공정은 캐패시터를 상기 노출된 소스에 접속되도록 형성한다. 이때 콘택저항을 줄이기 위한 이온주입공정은 생략된다.As such, the process after forming the contact hole forms a capacitor to be connected to the exposed source. At this time, the ion implantation process for reducing the contact resistance is omitted.

상기한 바와 같이 본 발명 반도체 메모리의 콘택홀 형성방법은 콘택저항을 줄이기 위한 이온주입을 열산화막, 질화막, 열산화막 적층구조를 이온주입 버퍼로 사용하여 실시하고, 그 이온주입으로 약화된 열산화막, 질화막, 열산화막을 선택적으로 식각함으로써, 원하는 면적의 소스를 노출시켜 이후에 형성하는 캐패시터와의 접속을 용이하게 하여 전체적인 반도체 메모리의 특성을 향상시키는 효과가 있다.As described above, in the method of forming a contact hole in the semiconductor memory of the present invention, ion implantation for reducing contact resistance is performed using a thermal oxide film, a nitride film, and a thermal oxide layer structure as an ion implantation buffer, and a thermal oxide film weakened by the ion implantation; By selectively etching the nitride film and the thermal oxide film, a source having a desired area is exposed to facilitate connection with a capacitor to be formed later, thereby improving the characteristics of the overall semiconductor memory.

Claims (4)

모스 트랜지스터가 제조된 기판의 상부에 제 1열산화막, 질화막, 제 2열산화막을 순차적으로 증착하는 ONO구조 절연층 형성단계와; 상기 제 2열산화막의 상부에 두꺼운 제 3열산화막을 증착하고, 사진식각공정을 통해 상기 제 3열산화막의 일부를 식각하여 상기 제 2열산화막의 일부를 노출시키는 ONO구조 절연층 노출단계와; 상기 노출된 제 2열산화막과 그 하부의 질화막, 제 1열산화막을 이온주입의 버퍼로 사용하는 이온주입공정으로 상기 모스 트랜지스터의 소스에 불순물이온을 주입하는 이온주입단계와; 상기 제 2열산화막, 질화막, 제 1열산화막을 선택적으로 식각하여 상기 모스 트랜지스터의 소스를 노출시키는 소스 노출단계로 이루어진 것을 특징으로 하는 반도체 메모리의 콘택홀 형성방법.An ONO structure insulating layer forming step of sequentially depositing a first thermal oxide film, a nitride film, and a second thermal oxide film on the substrate on which the MOS transistor is manufactured; An ONO structure insulating layer exposing step of depositing a thick third thermal oxide film on the second thermal oxide film and etching a portion of the third thermal oxide film through a photolithography process to expose a portion of the second thermal oxide film; An ion implantation step of implanting impurity ions into the source of the MOS transistor by an ion implantation process using the exposed second thermal oxide film, a nitride film below it, and a first thermal oxide film as an ion implantation buffer; And exposing the source of the MOS transistor by selectively etching the second thermal oxide film, the nitride film, and the first thermal oxide film. 제 1항에 있어서, 상기 이온주입단계에서 주입하는 불순물 이온은 상기 모스 트랜지스터와 동일한 형을 고농도로 주입하는 것을 특징으로 하는 반도체 메모리의 콘택홀 형성방법.The method of claim 1, wherein the impurity ions implanted in the ion implantation step are implanted at a high concentration with the same type as the MOS transistor. 제 1항에 있어서, 상기 소스 노출단계에서 제 2열산화막과 질화막은 플라즈마 식각방법을 사용하여 식각하는 것을 특징으로 하는 반도체 메모리의 콘택홀 형성방법.The method of claim 1, wherein in the source exposing step, the second thermal oxide layer and the nitride layer are etched using a plasma etching method. 제 1항에 있어서, 상기 소스 노출단계에서 제 1열산화막은 습식식각방법을 사용하여 식각하는 것을 특징으로 하는 반도체 메모리의 콘택홀 형성방법.The method of claim 1, wherein in the exposing of the source, the first thermal oxide layer is etched using a wet etching method.
KR1019970058509A 1997-11-06 1997-11-06 Contact hole formation method of semiconductor memory Expired - Fee Related KR100253344B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970058509A KR100253344B1 (en) 1997-11-06 1997-11-06 Contact hole formation method of semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970058509A KR100253344B1 (en) 1997-11-06 1997-11-06 Contact hole formation method of semiconductor memory

Publications (2)

Publication Number Publication Date
KR19990038682A KR19990038682A (en) 1999-06-05
KR100253344B1 true KR100253344B1 (en) 2000-04-15

Family

ID=19524286

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970058509A Expired - Fee Related KR100253344B1 (en) 1997-11-06 1997-11-06 Contact hole formation method of semiconductor memory

Country Status (1)

Country Link
KR (1) KR100253344B1 (en)

Also Published As

Publication number Publication date
KR19990038682A (en) 1999-06-05

Similar Documents

Publication Publication Date Title
US4295924A (en) Method for providing self-aligned conductor in a V-groove device
US4398964A (en) Method of forming ion implants self-aligned with a cut
JPH03101147A (en) Manufacture of semiconductor device
KR100253344B1 (en) Contact hole formation method of semiconductor memory
KR100244402B1 (en) Method of forming a trench isolation in a semiconductor device
KR0183718B1 (en) A manufacturing method of a semiconductor device having a device isolation structure including a conductive layer
KR100237007B1 (en) Manufacturing Method of Flash Memory Cell
KR960013943B1 (en) Thin film transistor manufacturing method
KR100215871B1 (en) Method for fabricating semiconductor device
KR100198637B1 (en) Method of manufacturing semiconductor device
KR100219069B1 (en) Semiconductor device manufacturing method
KR100525114B1 (en) Manufacturing method of semiconductor device
KR0134859B1 (en) Fabrication method of contact hole in semiconductor device
KR960002071B1 (en) Contact formation method of semiconductor device
KR100280537B1 (en) Semiconductor device manufacturing method
KR20040002121A (en) Method for Forming Field Area in Semiconductor Device
KR19990080191A (en) MOS transistor manufacturing method
KR0124643B1 (en) Forming method of isolation film in semiconductor device
KR100364794B1 (en) Method for fabricating of semiconductor device
KR960012574B1 (en) Manufacturing method of semiconductor device
KR100202655B1 (en) Fabrication method of eeprom memory cell
KR100460704B1 (en) SRAM's Bottom Gate Thin Film Transistor Manufacturing Method
KR100249150B1 (en) Field oxide film formation method
KR0148611B1 (en) Formation method of element isolation layer for semiconductor devices
KR100245087B1 (en) Device isolation insulating film formation method of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19971106

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19971106

Comment text: Request for Examination of Application

PG1501 Laying open of application
E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 19991220

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20000122

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20000124

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20021223

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20031219

Start annual number: 5

End annual number: 5

FPAY Annual fee payment

Payment date: 20041230

Year of fee payment: 6

PR1001 Payment of annual fee

Payment date: 20041230

Start annual number: 6

End annual number: 6

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee