KR100252928B1 - Method for forming metal line of semiconductor device - Google Patents
Method for forming metal line of semiconductor device Download PDFInfo
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- KR100252928B1 KR100252928B1 KR1019920021423A KR920021423A KR100252928B1 KR 100252928 B1 KR100252928 B1 KR 100252928B1 KR 1019920021423 A KR1019920021423 A KR 1019920021423A KR 920021423 A KR920021423 A KR 920021423A KR 100252928 B1 KR100252928 B1 KR 100252928B1
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- metal
- metal wiring
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- photosensitive film
- film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본발명은 반도체 장치의 금속배선 형성방법에 관한것으로 금속배선과 플러그를 동시에 형성한것이다.The present invention relates to a method for forming metal wiring in a semiconductor device, wherein the metal wiring and the plug are simultaneously formed.
종래에는 PR을 2층으로 코팅하여 두번 노광하기 때문에 공정이 복잡하고 PR의 선택비를 고려하여야만 했다.Conventionally, since the PR is coated with two layers and exposed twice, the process is complicated and the selectivity of the PR has to be taken into consideration.
본발명은 PR을 1층 코팅하고 두번노광한것으로 1차노광은 언더노광으로 금속콘택영역을 정의하고 2차노광은 금속배선을 노광하였다.According to the present invention, a single layer of PR was coated and exposed twice. The first exposure defined the metal contact region as the underexposure, and the second exposure exposed the metal wiring.
따라서 공정이 간단하다.Therefore, the process is simple.
Description
제1도는 종래의 대머신(DAMASCENE)방법을 이용한 금속배선 공정단면도.1 is a cross-sectional view of a metal wiring process using a conventional DAMASCENE method.
제2도는 본발명의 대머신 방법을 이용한 금속배선 공정단면도.2 is a cross-sectional view of a metallization process using the Great Machine method of the present invention.
〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
1 : 제1금속 2 : 절연막1: first metal 2: insulating film
5 : 제2금속 5a : 금속배선5: second metal 5a: metal wiring
5b : 플러그 6 : 감광막5b: plug 6: photosensitive film
본발명은 반도체 장치의 금속배선 형성방법에 관한것으로 특히 금속과 금속간의 연결공정에 적당하도록 대머신방법을 이용한 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring in a semiconductor device, and more particularly, to a method for forming metal wiring using a large machine method so as to be suitable for a metal-to-metal connection process.
종래의 대머신 방법을 이용한 금속배선 형성방법을 첨부된 도면을 참조하여 설명하면 다음과 같다.Referring to the accompanying drawings, a metal wiring forming method using a conventional machine method is as follows.
제1도는 종래의 대머신 방법을 이용한 금속배선공정 단면도로써, 제1도(a)와같이 제1금속(1)위에 산화막등의 평탄화용 절연막(2)을 증착하고 절연막(2)위에 제1감광막(3)을 증착하고 노광하여 금속콘택 영역을 정의하고 제1감광막(3)위에 제2감광막(4)을 증착하고 노광하여 금속배선 영역을 정의한다.FIG. 1 is a cross-sectional view of a metal wiring process using a conventional damascene method. As shown in FIG. 1 (a), a planarization insulating film 2 such as an oxide film is deposited on a first metal 1 and a first film is formed on the insulating film 2. The photosensitive film 3 is deposited and exposed to define a metal contact region, and the second photosensitive film 4 is deposited and exposed on the first photosensitive film 3 to define a metal wiring region.
제1도(b)와같이 제1감광막(3) 제2감광막(4)을 마스크로 이용하여 금속콘택영역의 절연막(2)을 제1금속(1)이 노출되지 않도록 에치시간을 조정하여 언더에치(UNDER ETCH)한다음 제1도(c)와 같이 제2감광막(4)을 마스크로 이용하여 제1감광막(3)을 에치한다.As shown in FIG. 1 (b), the etch time is adjusted so that the first metal 1 is not exposed to the insulating film 2 in the metal contact region using the first photosensitive film 3 and the second photosensitive film 4 as a mask. After etching, the first photosensitive film 3 is etched using the second photosensitive film 4 as a mask as shown in FIG.
제1도(d)와같이 제1,제2감광막(3,4)을 마스크로 이용하여 제1금속이 노출되도록 절연막(2)을 에치한다음 제1,제2감광막(3,4)을 제거한다.As shown in FIG. 1D, the insulating film 2 is etched to expose the first metal using the first and second photoresist films 3 and 4 as masks, and then the first and second photoresist films 3 and 4 are removed. Remove
제1도(e)와 같이 전면에 전면에 제2금속(5)을 증착하고 제1도(f)와같이 에치백하여 금속배선(5a)과 금속연결을 위한 플러그(5b)를 동시에 형성한다.As shown in FIG. 1 (e), the second metal 5 is deposited on the entire surface and etched back as shown in FIG. 1 (f) to simultaneously form the metal wiring 5a and the plug 5b for metal connection. .
그러나 이와같은 종래의 금속배선방법에 있어서는 금속배선과 플러그를 동시에 정의하기 위하여 마스크공정을 2개층으로 2회실시함으로써 공정이 복잡하고 두마스크가 좋은 시각 선택비를 갖어야 하므로 마스크 선정에 어려움이 있는등의 문제점이 있다.However, in the conventional metal wiring method, the mask process is performed twice in two layers in order to define the metal wiring and the plug at the same time. Therefore, the mask is difficult to select and the mask has a good visual selection ratio. There is such a problem.
본 발명은 이와같은 문제점을 해결하기 위하여 안출한 것으로 공정을 단순화하는데 그 목적이 있다.The present invention has been made in order to solve such a problem, and its object is to simplify the process.
이와같은 목적을 달성하기 위한 본발명은 한층의 마스크로 두번 노광하여 금속배선과 플러그를 형성한 것이다.The present invention for achieving the above object is to form a metal wiring and a plug by exposing twice with a single mask.
이를 첨부된 도면을 참조하여 보다 상세히 설명하면 다음과 같다.This will be described in more detail with reference to the accompanying drawings.
제2도에는 본발명의 금속배선 공정단면도로써, 제2도(a)와 같이 제1금속(1)을 증착하고 패터닝한뒤 그위에 산화막등의 평탄화용 절연막(2)과 감광막(6)을 차례로 증착하고 노광하여 금속콘택영역을 정의한다.FIG. 2 is a cross-sectional view of the metallization process of the present invention, in which the first metal 1 is deposited and patterned as shown in FIG. 2 (a), and the planarization insulating film 2 and the photosensitive film 6 such as an oxide film are disposed thereon. Deposition and exposure are in turn defined to define the metal contact region.
제2도(b)와 같이 감광막(6)을 마스크로 이용하고 절연막(2)을 제1금속(1)이 노출되지 않도록 에치시간을 조절하여 언더에치를 실시한다.As shown in FIG. 2 (b), underetching is performed by using the photosensitive film 6 as a mask and adjusting the etch time so that the first metal 1 is not exposed to the insulating film 2.
제2도(c)와같이 감광막(6)에 노광하여 금속배선 영역을 정의하고 제2도(d)와같이 감광막(6)을 마스크로 이용하고 절연막(6)을 에치하여 제1금속(1)이 노출되도록 금속콘택홀을 형성하고 금속배선영역을 형성한다.As shown in FIG. 2 (c), the metal wiring region is defined by exposing to the photosensitive film 6, and as shown in FIG. 2 (d), the photosensitive film 6 is used as a mask and the insulating film 6 is etched to form the first metal (1). ) To form a metal contact hole and to form a metal wiring region.
제2도(e)와같이 감광막(6)을 제거하고 제2도(f)와같이 전면에 제2금속(5)을 증착한다음, 제2도(g)와같이 제2금속(5)을 에치백하여 금속배선(5a)과 플러그(5b)을 형성한다.The photosensitive film 6 is removed as shown in FIG. 2 (e), and the second metal 5 is deposited on the entire surface as shown in FIG. 2 (f), and then the second metal 5 as shown in FIG. 2 (g). Is etched back to form the metal wiring 5a and plug 5b.
여기서 감광막(6) 대신 SOG(Spin On Glass)를 사용할수 있는데 감광막(5)을 사용할경우 첫번째 노광은 언더노광(Under Expouse)하여 금속콘택영역을 정의하고, 두번째 노광은 오버노광(Over Expouse)하여 금속배선 영역을 정의한다.In this case, the SOG (Spin On Glass) may be used instead of the photoresist film 6. When the photoresist film 5 is used, the first exposure is under exposed to define a metal contact region, and the second exposure is over exposed. Define the metallization area.
또한 SOG를 사용할경우는 금속콘택을 SOG를 사용할 경우는 금속콘택영역을 노광 하여 SOG를 변질시키고 변질된 부분만 에치할수 있는 화학물질을 이용하여 그부분을 제거한뒤 이를 마스크로 이용한다.In the case of using SOG, the metal contact is exposed. In the case of using SOG, the metal contact area is exposed to deteriorate the SOG, and a chemical substance which can only etch the deteriorated portion is removed and then used as a mask.
같은 방법으로 금속배선 영역도 노광하고 선택에치하여 마스크를 패터닝한다. 이상에서 설명한 바와같이 본발명의 금속배선 형성방법에 있어서는 마스크 공정을 줄일 수 있으며 마스크를 폭넓게 선택할수 있는 효과가 있다.In the same manner, the metallization region is also exposed and selectively etched to pattern the mask. As described above, in the metal wiring forming method of the present invention, the mask process can be reduced and the mask can be widely selected.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920021423A KR100252928B1 (en) | 1992-11-14 | 1992-11-14 | Method for forming metal line of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920021423A KR100252928B1 (en) | 1992-11-14 | 1992-11-14 | Method for forming metal line of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940012500A KR940012500A (en) | 1994-06-23 |
| KR100252928B1 true KR100252928B1 (en) | 2000-04-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920021423A Expired - Fee Related KR100252928B1 (en) | 1992-11-14 | 1992-11-14 | Method for forming metal line of semiconductor device |
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| Country | Link |
|---|---|
| KR (1) | KR100252928B1 (en) |
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- 1992-11-14 KR KR1019920021423A patent/KR100252928B1/en not_active Expired - Fee Related
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| Publication number | Publication date |
|---|---|
| KR940012500A (en) | 1994-06-23 |
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