KR100379530B1 - method for forming dual damascene of semiconductor device - Google Patents
method for forming dual damascene of semiconductor device Download PDFInfo
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- KR100379530B1 KR100379530B1 KR10-2000-0085289A KR20000085289A KR100379530B1 KR 100379530 B1 KR100379530 B1 KR 100379530B1 KR 20000085289 A KR20000085289 A KR 20000085289A KR 100379530 B1 KR100379530 B1 KR 100379530B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 32
- 230000009977 dual effect Effects 0.000 title claims abstract description 20
- 239000010410 layer Substances 0.000 claims abstract description 61
- 239000011229 interlayer Substances 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 230000004888 barrier function Effects 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000009792 diffusion process Methods 0.000 claims abstract description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 20
- 150000004767 nitrides Chemical class 0.000 description 6
- 239000010949 copper Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 듀얼 다마신 형성방법에 관한 것으로서, 반도체 기판상에 금속 배선을 형성하는 단계와, 상기 금속 배선을 포함한 반도체 기판의 전면에 확산 방지막을 형성하는 단계와, 상기 확산 방지막상에 제 1, 제 2 층간 절연막을 차례로 형성하는 단계와, 상기 제 2 층간 절연막상에 식각 방지막을 형성하는 단계와, 상기 식각 방지막상에 제 1 마스크 패턴을 형성하는 단계와, 상기 제 1 마스크 패턴의 일부 및 그에 인접한 식각 방지막이 노출되도록 상기 반도체 기판상에 상기 제 1 마스크 패턴과 식각비가 다른 제 2 마스크 패턴을 형성하는 단계와, 상기 제 2 마스크 패턴을 마스크로 이용하여 상기 제 1 층간 절연막의 소정 두께까지 노출된 제 1 마스크 패턴, 식각 방지막, 제 2 층간 절연막, 제 1 층간 절연막을 선택적으로 제거하는 단계와, 상기 제 2 마스크 패턴을 마스크로 이용하여 상기 금속 배선의 표면이 소정부분 노출되도록 상기 제 1 마스크 패턴, 식각 방지막, 제 2 층간 절연막, 제 1 층간 절연막, 확산 방지막을 선택적으로 제거하여 트랜치 및 콘택홀을 동시에 형성하는 단계를 포함하여 형성함을 특징으로 한다.The present invention relates to a method for forming dual damascene of a semiconductor device, comprising the steps of: forming a metal wiring on a semiconductor substrate, forming a diffusion barrier on the entire surface of the semiconductor substrate including the metal wiring; Forming a first and a second interlayer insulating film in order, forming an etch stop layer on the second interlayer insulating film, forming a first mask pattern on the etch stop layer, and forming a first mask pattern Forming a second mask pattern having an etch ratio different from the first mask pattern on the semiconductor substrate to expose a portion and an etch stop layer adjacent thereto, and using the second mask pattern as a mask to form a predetermined portion of the first interlayer insulating layer Selectively removing the first mask pattern, the etch stop layer, the second interlayer insulating layer, and the first interlayer insulating layer exposed to the thickness; Using the second mask pattern as a mask, trenches and contact holes may be selectively removed by selectively removing the first mask pattern, an etch barrier layer, a second interlayer dielectric layer, a first interlayer dielectric layer, and a diffusion barrier layer to expose a predetermined portion of the surface of the metal line. It characterized in that it comprises a step of forming at the same time.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 수직 트랜치(virtual trench)를 디파인(define)하는데 적당한 반도체 소자의 듀얼 다마신 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming dual damascene of a semiconductor device suitable for defining a vertical trench.
최근 알루미늄(Al)을 배선 재료로 사용한 반도체 소자의 한계성이 부각됨에 따라 배선 재료를 구리(Cu)로 대체해야 할 필요성이 절실해지고 있다.Recently, as the limit of the semiconductor device using aluminum (Al) as the wiring material is highlighted, the need to replace the wiring material with copper (Cu) is urgently needed.
한편, 구리는 건식 식각(dry etch)이 어려워 듀얼 다마신(dual damascene) 구조를 사용하는 것이 일반적이다.On the other hand, copper is difficult to dry etch (dry etch) it is common to use a dual damascene (dual damascene) structure.
이에 따라 듀얼 다마신 구조를 형성하는 많은 방법들이 발명되어 지고 있다.Accordingly, many methods for forming a dual damascene structure have been invented.
이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 듀얼 다마신 형성방법을 설명하면 다음과 같다.Hereinafter, a dual damascene formation method of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1d는 종래의 반도체 소자의 듀얼 다마신 형성방법을 나타낸 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of forming dual damascene of a conventional semiconductor device.
도 1a에 도시한 바와 같이, 반도체 기판(11)상에 금속막을 증착한 후, 포토 및 식각 공정을 통해 상기 금속막을 선택적으로 제거하여 금속 배선(12)을 형성한다.As shown in FIG. 1A, a metal film is deposited on the semiconductor substrate 11, and then the metal film is selectively removed through a photo and etching process to form a metal wiring 12.
이어, 상기 금속 배선(12)을 포함한 반도체 기판(11)의 전면에 절연막(13)을 형성하고, 상기 금속 배선(12)의 상부 표면을 앤드 포인트(end point)로 하여 상기 절연막(13)에 CMP 공정을 실시하여 평탄화시킨다.Next, an insulating film 13 is formed on the entire surface of the semiconductor substrate 11 including the metal wiring 12, and the upper surface of the metal wiring 12 is used as an end point to the insulating film 13. The CMP process is performed to planarize.
이어, 상기 금속 배선(12)을 포함한 반도체 기판(11)의 전면에 확산방지막(14)을 형성하고, 상기 확산 방지막(14)상에 제 1, 제 2 층간 절연막(15,16)을 차례로 형성한다.Subsequently, a diffusion barrier 14 is formed on the entire surface of the semiconductor substrate 11 including the metal wiring 12, and first and second interlayer insulating layers 15 and 16 are sequentially formed on the diffusion barrier 14. do.
그리고 상기 제 2 층간 절연막(16)상에 제 1 마스크용 질화막(17)을 형성하고, 포토 및 식각공정을 통해 상기 질화막(17)을 선택적으로 제거하여 트랜치 영역을 정의한다.In addition, a first mask nitride layer 17 is formed on the second interlayer insulating layer 16, and the trench layer is defined by selectively removing the nitride layer 17 through photo and etching processes.
이어, 상기 질화막(17)을 포함한 반도체 기판(11)의 전면에 제 2 마스크용 감광막(18)을 도포한 후, 노광 및 현상공정으로 상기 감광막(18)을 패터닝하여 콘택 영역을 정의한다.Subsequently, the second mask photoresist film 18 is coated on the entire surface of the semiconductor substrate 11 including the nitride film 17, and then the photoresist film 18 is patterned by an exposure and development process to define a contact region.
도 1b에 도시한 바와 같이, 상기 패터닝된 감광막(18)을 마스크로 이용하여 상기 금속 배선(12)상에 확산 방지막(14)의 표면이 소정부분 노출되도록 상기 제 2, 제 1 층간 절연막(16,15)을 선택적으로 제거하여 콘택홀(19)을 형성한다.As shown in FIG. 1B, the second and first interlayer insulating layers 16 are exposed using a portion of the patterned photoresist layer 18 as a mask so that a predetermined portion of the surface of the diffusion barrier layer 14 is exposed on the metal wiring 12. 15 is selectively removed to form the contact hole 19.
여기서 이후 트랜치를 형성하기 위해 형성된 상기 질화막(17)에 의해 콘택홀(19)의 크기는 작게 형성되어 상기 콘택홀(19)의 내부에 감광막 등의 이물질(도시되지 않음)이 잔류하게 된다.Here, the contact hole 19 is formed to have a small size by the nitride film 17 formed to form a trench, so that foreign matters (not shown) such as a photoresist film remain in the contact hole 19.
도 1c에 도시한 바와 같이, 상기 감광막(18)을 제거한다.As shown in Fig. 1C, the photosensitive film 18 is removed.
도 1d에 도시한 바와 같이, 상기 질화막(17)을 마스크로 이용하여 상기 제 2 층간 절연막(16)을 선택적으로 제거하여 트랜치(20)를 형성한다.As shown in FIG. 1D, the trench 20 is formed by selectively removing the second interlayer insulating layer 16 using the nitride film 17 as a mask.
여기서 상기 콘택홀(19)과 트랜치(20)에 의해 듀얼 다마신 구조를 형성하게 된다.Here, the dual damascene structure is formed by the contact hole 19 and the trench 20.
이후 공정은 도시하지 않았지만 상기 콘택홀(19) 및 트랜치(20)를 포함한 전면에 구리막을 증착한 후 선택적으로 제거하여 배선을 형성한다.Since the process is not shown, a copper film is deposited on the entire surface including the contact hole 19 and the trench 20, and then selectively removed to form wiring.
한편, 도 2는 종래의 트랜치 및 콘택홀을 형성하기 위해 사용되는 각 마스크간의 오버레이 마진 부족으로 인하여 발생하는 문제점을 나타낸 단면도이다.On the other hand, Figure 2 is a cross-sectional view showing a problem caused by the lack of overlay margin between each mask used to form a conventional trench and contact hole.
도 2에서와 같이, 질화막(17)과 감광막(18)의 오버레이 마진의 부족으로 인하여 콘택홀(19)이 좁아짐에 따라 콘택홀(19)내에 감광막(18)의 잔류물(residue)이 그대로 남아있게 되고, 이후 트랜치(20)를 형성할 때 디파인(define) 하기가 어려워진다.As shown in FIG. 2, as the contact hole 19 is narrowed due to the lack of overlay margin between the nitride film 17 and the photoresist film 18, the residue of the photoresist film 18 remains in the contact hole 19. It is then difficult to define when forming the trench 20.
즉, 콘택홀(19)을 먼저 형성한 후, 트랜치(20)를 형성하기 위한 감광막(18)을 패터닝할 때 콘택홀(19)내에 채워지는 감광막(18)이 식각에 방해를 주어서는 안되지만 콘택홀(19)과 트랜치(20)의 폭이 좁아서 발생되는 식각 부산물이 홀에 채워진 감광막 주위에 붙어 있게 된다.That is, when the contact hole 19 is first formed, and then the photoresist film 18 for forming the trench 20 is patterned, the photoresist film 18 filled in the contact hole 19 should not interfere with etching. Etch by-products generated by narrowing the widths of the holes 19 and trenches 20 are stuck around the photoresist film filled in the holes.
그러나 상기와 같은 종래의 반도체 소자의 듀얼 다마신 형성방법에 있어서 다음과 같은 문제점이 있었다.However, there is a problem in the method of forming dual damascene of the conventional semiconductor device as described above.
즉, 콘택홀을 먼저 형성한 후, 트랜치를 형성하기 위한 감광막을 패터닝할 때 콘택홀내에 채워지는 감광막이 식각에 방해를 주어서는 안되는데 콘택홀과 트랜치의 폭이 좁아서 발생되는 식각 부산물이 콘택홀에 채워져 트랜치를 디파인하기가 어렵게 된다.That is, when the contact hole is first formed, the photoresist film filled in the contact hole should not interfere with the etching when patterning the photoresist for forming the trench. This can make it difficult to define trenches.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 트랜치와 콘택홀간의 마스크 마진을 향상시킴으로서 잔류물이 발생하는 것을 방지하도록 한 반도체 소자의 듀얼 다마신 형성방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for forming a dual damascene of a semiconductor device to prevent the occurrence of residue by improving the mask margin between the trench and the contact hole to solve the conventional problems as described above. .
도 1a 내지 도 1d는 종래의 반도체 소자의 듀얼 다마신 형성방법을 나타낸 공정단면도1A to 1D are cross-sectional views illustrating a method of forming dual damascene in a conventional semiconductor device.
도 2는 종래의 트랜치 및 콘택홀을 형성하기 위해 사용되는 각 마스크간의 오버레이 마진 부족으로 인하여 발생하는 문제점을 나타낸 단면도2 is a cross-sectional view showing a problem caused by the lack of overlay margin between each mask used to form a conventional trench and contact hole.
도 3a 내지 도 3e는 본 발명에 의한 반도체 소자의 듀얼 다마신 형성방법을 나타낸 공정단면도3A to 3E are cross-sectional views illustrating a method of forming dual damascene of a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
31 : 반도체 기판 32 : 금속 배선31 semiconductor substrate 32 metal wiring
33 : 절연막 34 : 확산 방지막33 insulating film 34 diffusion barrier film
35 : 제 1 층간 절연막 36 : 제 2 층간 절연막35 first interlayer insulating film 36 second interlayer insulating film
37 : 식각 방지막 38 : 실리콘 질화막37: anti-etching film 38: silicon nitride film
39 : 제 1 감광막 40 : 제 2 감광막39: first photosensitive film 40: second photosensitive film
41 : 트랜치 42 : 콘택홀41: trench 42: contact hole
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 듀얼 다마신 형성방법은 반도체 기판상에 금속 배선을 형성하는 단계와, 상기 금속 배선을 포함한 반도체 기판의 전면에 확산 방지막을 형성하는 단계와, 상기 확산 방지막상에 제 1, 제 2 층간 절연막을 차례로 형성하는 단계와, 상기 제 2 층간 절연막상에 식각 방지막을 형성하는 단계와, 상기 식각 방지막상에 제 1 마스크 패턴을 형성하는 단계와, 상기 제 1 마스크 패턴의 일부 및 그에 인접한 식각 방지막이 노출되도록 상기 반도체 기판상에 상기 제 1 마스크 패턴과 식각비가 다른 제 2 마스크 패턴을 형성하는 단계와, 상기 제 2 마스크 패턴을 마스크로 이용하여 상기 제 1 층간 절연막의 소정 두께까지 노출된 제 1 마스크 패턴, 식각 방지막, 제 2 층간 절연막, 제 1 층간 절연막을 선택적으로 제거하는 단계와, 상기 제 2 마스크 패턴을 마스크로 이용하여 상기 금속 배선의 표면이 소정부분 노출되도록 상기 제 1 마스크 패턴, 식각 방지막, 제 2 층간 절연막, 제 1 층간 절연막, 확산 방지막을 선택적으로 제거하여 트랜치 및 콘택홀을 동시에 형성하는 단계를 포함하여 형성함을 특징으로 한다.The dual damascene forming method of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a metal wiring on the semiconductor substrate, forming a diffusion barrier on the entire surface of the semiconductor substrate including the metal wiring; Forming first and second interlayer insulating films on the diffusion barrier layer, forming an etch barrier layer on the second interlayer insulating layer, forming a first mask pattern on the etch barrier layer, Forming a second mask pattern having an etch ratio different from the first mask pattern on the semiconductor substrate to expose a portion of the first mask pattern and an etch stop layer adjacent thereto, and using the second mask pattern as a mask; Select the first mask pattern, the etch stop film, the second interlayer insulating film, and the first interlayer insulating film exposed to a predetermined thickness of the first interlayer insulating film. Selectively removing the first mask pattern, an etch stop film, a second interlayer insulating film, a first interlayer insulating film, and a diffusion barrier to expose a predetermined portion of the surface of the metal wiring using the second mask pattern as a mask. Forming a trench and a contact hole at the same time by removing to form.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 듀얼 다마신 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of forming dual damascene of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3e는 본 발명에 의한 반도체 소자의 듀얼 다마신 형성방법을 나타낸 공정단면도이다.3A to 3E are cross-sectional views illustrating a method of forming dual damascene of a semiconductor device according to the present invention.
도 3a에 도시한 바와 같이, 반도체 기판(31)상에 금속막을 증착한 후, 포토 및 식각 공정을 통해 상기 금속막을 선택적으로 제거하여 금속 배선(32)을 형성한다.As shown in FIG. 3A, a metal film is deposited on the semiconductor substrate 31, and then the metal film is selectively removed through a photo and etching process to form a metal wiring 32.
이어, 상기 금속 배선(32)을 포함한 반도체 기판(31)의 전면에 절연막(33)을 형성하고, 상기 금속 배선(32)의 상부 표면을 앤드 포인트(end point)로 하여 상기 절연막(33)에 CMP 공정을 실시하여 평탄화시킨다.Next, an insulating film 33 is formed on the entire surface of the semiconductor substrate 31 including the metal wiring 32, and the upper surface of the metal wiring 32 is used as an end point to the insulating film 33. The CMP process is performed to planarize.
이어, 상기 금속 배선(32)을 포함한 반도체 기판(31)의 전면에 확산 방지막(34)을 형성하고, 상기 확산 방지막(34)상에 제 1, 제 2 층간 절연막(35,36)을 차례로 형성한다.Subsequently, a diffusion barrier 34 is formed on the entire surface of the semiconductor substrate 31 including the metal wiring 32, and first and second interlayer insulating layers 35 and 36 are sequentially formed on the diffusion barrier 34. do.
이어, 상기 제 2 층간 절연막(36)상에 식각 방지막(37)을 형성하고, 상기 식각 방지막(37)상에 제 1 마스크용 실리콘 질화(Silicon nitride)막(38)을 증착한다.Next, an etch stop layer 37 is formed on the second interlayer insulating layer 36, and a first silicon nitride layer 38 for the first mask is deposited on the etch stop layer 37.
여기서 상기 실리콘 질화막(38) 대신에 실리콘 산화막, 티타늄 질화(titanium nitride)막, 티타늄 산화막, 실리콘 카바이드(silicon carbide) 등을 사용할 수 있다.Instead of the silicon nitride film 38, a silicon oxide film, a titanium nitride film, a titanium oxide film, silicon carbide, or the like may be used.
한편, 상기 실리콘 질화막(38)은 플라즈마(plasma)를 사용하는 CVD 또는 PVD로 증착하거나 코팅(coating) 공정을 형성한다.On the other hand, the silicon nitride film 38 is deposited by CVD or PVD using plasma (plasma) or to form a coating (coating) process.
또한, 상기 실리콘 질화막(38)은 상기 식각 방지막(37)을 형성하기 전에 형성할 수도 있다.In addition, the silicon nitride layer 38 may be formed before forming the etch stop layer 37.
이어, 상기 실리콘 질화막(38)상에 제 1 감광막(39)을 도포한 후, 노광 및현상 공정으로 제 1 감광막(39)을 패터닝한다.Subsequently, after the first photoresist film 39 is coated on the silicon nitride film 38, the first photoresist film 39 is patterned by an exposure and development process.
도 3b에 도시한 바와 같이, 상기 패터닝된 제 1 감광막(39)을 마스크로 이용하여 상기 실리콘 질화막(38)을 선택적으로 제거하여 실리콘 질화막 패턴(38a)을 형성하고, 상기 제 1 감광막(39)을 제거한다.As shown in FIG. 3B, the silicon nitride layer 38 is selectively removed by using the patterned first photoresist layer 39 as a mask to form a silicon nitride layer pattern 38a, and the first photoresist layer 39 is formed. Remove it.
도 3c에 도시한 바와 같이, 상기 실리콘 질화막 패턴(38a)을 포함한 반도체 기판(31)의 전면에 제 2 마스크용 제 2 감광막(40)을 도포한 후, 노광 및 현상공정으로 상기 실리콘 질화막 패턴(38a) 및 그에 인접한 식각 방지막(37)의 표면이 노출되도록 상기 제 2 감광막(40)을 패터닝하여 콘택 영역을 정의한다.As shown in FIG. 3C, after the second photosensitive film 40 for the second mask is applied to the entire surface of the semiconductor substrate 31 including the silicon nitride film pattern 38a, the silicon nitride film pattern ( The contact region is defined by patterning the second photoresist layer 40 so that the surface of the etch stop layer 37 adjacent thereto 38a) and the etch stop layer 37 are exposed.
도 3d에 도시한 바와 같이, 상기 패터닝된 제 2 감광막(40)을 마스크로 이용하여 상기 실리콘 질화막 패턴(38a), 식각 방지막(37), 제 2 층간 절연막(36)을 선택적으로 제거함과 동시에 상기 제 1 층간 절연막(35)을 표면으로부터 소정 두께만큼 식각한다.As shown in FIG. 3D, the silicon nitride layer pattern 38a, the etch stop layer 37, and the second interlayer insulating layer 36 are selectively removed by using the patterned second photoresist layer 40 as a mask. The first interlayer insulating film 35 is etched from the surface by a predetermined thickness.
여기서 상기 마스크로 사용된 제 2 감광막(40)도 상기 식각 공정에서 표면으로으로부터 식각이 진행되어 상기 실리콘 질화막 패턴(38a)의 상부 표면이 노출된다.Here, the second photoresist layer 40 used as the mask is also etched from the surface in the etching process to expose the upper surface of the silicon nitride film pattern 38a.
도 3e에 도시한 바와 같이, 상기 제 2 감광막(40)을 마스크로 이용하여 상기 실리콘 질화막 패턴(38a) 및 식각 방지막(37) 그리고 제 2 층간 절연막(36)을 선택적으로 제거하여 트랜치(41)를 형성함과 동시에 잔류하는 상기 제 1 층간 절연막(35)을 선택적으로 제거하여 콘택홀(42)을 형성한다.As shown in FIG. 3E, the trench 41 is formed by selectively removing the silicon nitride layer pattern 38a, the etch stop layer 37, and the second interlayer insulating layer 36 using the second photoresist layer 40 as a mask. The contact hole 42 is formed by selectively removing the remaining first interlayer insulating film 35 while forming a.
이어, 상기 제 2 감광막(40)을 제거함으로서 상기 콘택홀(42)과 트랜치(41)에 의해 듀얼 다마신 구조를 형성하게 된다.Subsequently, the second damascene film 40 is removed to form a dual damascene structure by the contact hole 42 and the trench 41.
이후, 공정은 도시하지 않았지만 상기 콘택홀(42)과 트랜치(41)를 포함한 전면에 구리막을 증착한 후 선택적으로 제거하여 배선을 형성한다.Thereafter, although not illustrated, a copper film is deposited on the entire surface including the contact hole 42 and the trench 41, and then selectively removed to form a wire.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 듀얼 다마신 형성방법은 다음과 같은 효과가 있다.As described above, the dual damascene formation method of the semiconductor device according to the present invention has the following effects.
첫째, 수직 트랜치 구조를 형성함으로서 마스크의 미스-얼라인이 100㎚이하일 때 100㎚의 선폭을 갖는 트랜치를 형성하여 듀얼 다마신을 형성할 수 있다.First, by forming a vertical trench structure, a trench having a line width of 100 nm may be formed when a mis-alignment of the mask is 100 nm or less to form dual damascene.
둘째, 미스-얼라인이 발생해도 콘택홀의 크기에는 변함이 없어 콘택홀 마스크 공정시 CD(Critical Dimension)의 불균일성을 줄일 수 있다.Second, even if a misalignment occurs, the size of the contact hole does not change, and thus the nonuniformity of the CD (critical dimension) may be reduced during the contact hole mask process.
셋째, 미스-얼라인이 발생해도 콘택홀의 크기에는 변함이 없어 콘택홀 마스크 공정시 재현성을 향상시킬 수 있다.Third, even if a misalignment occurs, the size of the contact hole does not change and thus the reproducibility may be improved during the contact hole mask process.
넷째, 콘택홀과 트랜치의 형성을 동시에 진행함으로서 감광막의 잔류물이 최소로 줄일 수 있다.Fourth, residues of the photoresist film can be minimized by simultaneously forming the contact holes and the trenches.
다섯째, 콘택홀 형성시 트랜치 마스크가 없는 것이나 동일함으로 콘택홀의 형성이 용이하며 공정을 단순화시킬 수 있다.Fifth, since the trench hole is not formed or the same, the contact hole may be easily formed and the process may be simplified.
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| US6060380A (en) * | 1998-11-06 | 2000-05-09 | Advanced Micro Devices, Inc. | Antireflective siliconoxynitride hardmask layer used during etching processes in integrated circuit fabrication |
| KR100265771B1 (en) * | 1998-07-09 | 2000-10-02 | 윤종용 | Method for metallization by dual damascene process using photosensitive polymer |
| US6156643A (en) * | 1998-11-06 | 2000-12-05 | Advanced Micro Devices, Inc. | Method of forming a dual damascene trench and borderless via structure |
| JP2000349152A (en) * | 1999-03-29 | 2000-12-15 | Sony Corp | Manufacture of semiconductor device |
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| KR100265771B1 (en) * | 1998-07-09 | 2000-10-02 | 윤종용 | Method for metallization by dual damascene process using photosensitive polymer |
| US6060380A (en) * | 1998-11-06 | 2000-05-09 | Advanced Micro Devices, Inc. | Antireflective siliconoxynitride hardmask layer used during etching processes in integrated circuit fabrication |
| US6156643A (en) * | 1998-11-06 | 2000-12-05 | Advanced Micro Devices, Inc. | Method of forming a dual damascene trench and borderless via structure |
| JP2000349152A (en) * | 1999-03-29 | 2000-12-15 | Sony Corp | Manufacture of semiconductor device |
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| US9087844B2 (en) | 2012-08-28 | 2015-07-21 | Samsung Electronics Co., Ltd. | Semiconductor device and fabricating method thereof |
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