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KR100252862B1 - Semiconductor package and method for fabricating the same - Google Patents

Semiconductor package and method for fabricating the same Download PDF

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Publication number
KR100252862B1
KR100252862B1 KR1019970077100A KR19970077100A KR100252862B1 KR 100252862 B1 KR100252862 B1 KR 100252862B1 KR 1019970077100 A KR1019970077100 A KR 1019970077100A KR 19970077100 A KR19970077100 A KR 19970077100A KR 100252862 B1 KR100252862 B1 KR 100252862B1
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South Korea
Prior art keywords
cap layer
heat dissipation
copper plate
thin film
semiconductor chip
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KR1019970077100A
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Korean (ko)
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KR19990057059A (en
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조용진
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: A semiconductor package and a manufacturing method thereof are provided to simplify manufacturing process and to improve heat dissipation. CONSTITUTION: The package includes a metallic cap layer(21) having both slanted sides, a paddle(22) formed on a central inside part of the metallic cap layer(21), a semiconductor chip(23) having pads(28) and attached to the paddle(22), a double-sided adhesive tape(24) adhered to inside faces of the both slanted sides of the metallic cap layer(21), copper lines(25) arranged on the adhesive tape(24) in a regular direction, silver plating portions(26) formed on inner ends of the copper lines(25), solder portions(27) formed on outer ends of the copper lines(25), wires(29) electrically connecting the pads(28) on the chip(23) and the silver plating portions(26) on the copper lines(25), and a molding resin(30) encapsulating all the elements disposed inside the metallic cap layer(21) except the solder portions(27).

Description

반도체 패키지 및 그의 제조방법Semiconductor package and manufacturing method thereof

본 발명은 반도체 패키지에 대한 것으로 특히, 공정을 단순화 하고 실장집적도를 높이며 핀피치를 높이고 열방출을 효과적으로 할 수 있는 반도체 패키지 및 그의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a semiconductor package and a method of manufacturing the same, which can simplify a process, increase mounting density, increase pin pitch, and effectively dissipate heat.

일반적으로 반도체 패키지 제조시에는 웨이퍼에 집적회로를 형성하는 FAB공정(Fabrication Process)을 완료한 후, 웨이퍼 상에 만들어진 각 칩을 서로 분리시키는 다이싱(Dicing), 분리된 각 칩을 리드 프레임(Lead Frame)의 패들(Paddle)에 안착시키는 칩본딩(Chip Borlding), 칩 위의 본딩패드(Bonding Pad)와 리드 프레임의 인너 리드(Inner Lead)를 전기적으로 접속시키는 와이어 본딩(Wire Bonding)을 순차적으로 수행한 후 회로를 보호하기 위해 몰딩(Molding)을 수행하게 된다.In general, in manufacturing a semiconductor package, after completing a FAB process (fabrication process) for forming an integrated circuit on a wafer, dicing and separating the chips formed on the wafer from each other, the lead frames are separated from each chip. Chip Bonding, which is seated on the Paddle of the Frame, and Wire Bonding, which electrically connects the Bonding Pad on the Chip and the Inner Lead of the Lead Frame, in sequence After the molding, molding is performed to protect the circuit.

또한 몰딩을 수행한 후에는 리드 프레임의 써포트 바(Support Bar) 및 댐 바(Dam Bar)를 자르는 트리밍(Trimming) 및 아웃 리드(Out Lead)를 소정의 형상으로 성형하는 포밍(Forming)을 차례로 수행하게 되며, 트리밍 및 포밍 완료 후에는 최종적으로 솔더링(Solding)을 실시하므로써 공정을 완료하게 된다.In addition, after molding, trimming to cut the support bar and the dam bar of the lead frame and forming the out lead to a predetermined shape are sequentially performed. After trimming and forming, the process is finally completed by soldering.

그러나 일반적인 QFP(Quad Flat Package)형 반도체 패키지는 도 1에 도시된 바와 같이 리드 프레임(Lead Frame)의 패들(1)위에 에폭시 본딩된 반도체칩(2)이 있고, 반도체칩(2)의 패드(3)와 외부전달단자인 리드프레임의 인너 리드(5)가 전기 전도성이 양호한 금(Au)으로 된 와이어(4)로 본딩되어 있다. 이에따라서 패드(3)와 인너리드(5)를 와이어(4)가 전기적으로 연결한다. 그리고 트리밍(trimming)과 포밍(Forming)되어진 아웃 리드(6)를 통해 반도체칩(2)의 기능이 외부로 전달되어 진다.However, a typical QFP (Quad Flat Package) type semiconductor package has an epoxy bonded semiconductor chip 2 on a paddle 1 of a lead frame, as shown in FIG. 1, and a pad of the semiconductor chip 2. 3) and the inner lead 5 of the lead frame, which is an external transmission terminal, are bonded with a wire 4 made of gold (Au) having good electrical conductivity. Accordingly, the wire 4 electrically connects the pad 3 and the inner lead 5. The function of the semiconductor chip 2 is transmitted to the outside through the trimming and forming the out lead 6.

이와같은 일반적인 반도체 패키지는 반도체칩(2)의 내부단자인 패드(3)를 통해 와이어(4)를 경유하여 리드프레임의 아웃리드(6)로 전달되어 실장시 그 기능을 수행한다.Such a general semiconductor package is transferred to the outlead 6 of the lead frame via the wire 4 through the pad 3, which is an internal terminal of the semiconductor chip 2, and performs its function when mounted.

상기와 같은 일반적인 반도체 패키지는 다음과 같은 문제가 있다.The general semiconductor package as described above has the following problems.

첫째, 칩의 열방출이 취약하여 열적 저항에 약하다.First, the chip's heat dissipation is weak, so it is weak to thermal resistance.

둘째, 리드프레임을 사용하므로 핀 피치에 한계가 있다.Second, the pin pitch is limited because of the use of leadframes.

셋째, 리드프레임 조립 공정이 많고, 아웃리드에 의한 실장면적이 크다.Third, there are many lead frame assembly processes, and the mounting area by the outlead is large.

본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 공정을 단순화 하고 실장집적도를 높이며 핀피치를 높이고 열방출을 효과적으로 할 수 있는 반도체 패키지 및 그의 제조방법을 제공하는 데 그 목적이 있다.An object of the present invention is to provide a semiconductor package and a method for manufacturing the same, which are designed to solve the above problems, simplify the process, increase the mounting density, increase the pin pitch, and effectively dissipate heat.

제1도는 종래 반도체 소자의 패키지를 나타낸 도면.1 is a view showing a package of a conventional semiconductor device.

제2a도는 본 발명 반도체 패키지를 나타낸 구조도.Figure 2a is a structural diagram showing a semiconductor package of the present invention.

제2b도는 본 발명 반도체 패키지를 나타낸 사시도.Figure 2b is a perspective view showing a semiconductor package of the present invention.

제3a도 내지 제3c도는 본 발명 반도체 패키지 내의 솔더막과 은도금막이 도금된 박막동판을 제조하기 위한 방법을 나타낸 도면.3A to 3C show a method for manufacturing a thin film copper plate plated with a solder film and a silver plated film in a semiconductor package of the present invention.

〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

21 : 열방출캡층 22 : 패들21: heat release cap layer 22: paddle

23 : 반도체칩 24 : 양면접착 절연테이프23 semiconductor chip 24 double-sided adhesive insulating tape

25 : 박막동판 26 : 은도금막25: thin film copper plate 26: silver plated film

27 : 솔더막 28 : 패드27: solder film 28: pad

29 : 와이어 30 : 몰딩수지29: wire 30: molding resin

상기와 같은 목적을 달성하기 위한 본 발명 반도체 패키지는 세면이 조합하여 움푹 패이도록 구성된 열방출캡층, 상기 열방출캡의 안쪽 하부면상에 접하고 있는 반도체칩, 상기 열방출 안쪽 측면 가장자리에 양면접착 절연테이프, 상기 양면접착 절연테이프와 접촉되도록 일방향으로 규칙적으로 배열된 박막동판, 상기 박막동판의 안쪽 가장자리상에 형성된 솔더막, 상기 박막동판 바깥쪽 가장자리상에 형성된 은도금막, 상기 반도체칩 가장자리 상에 패드, 상기 반도체칩의 패드와 상기 은도금막을 전기적으로 연결하는 와이어, 상기 은도금막을 제외한 상기 열방출캡층안쪽에 형성된 몰딩수지를 포함하여 구성되는 것을 특징으로 한다.The semiconductor package according to the present invention for achieving the above object is a heat dissipation cap layer configured to pit three surfaces in combination, a semiconductor chip in contact with the inner bottom surface of the heat dissipation cap, double-sided adhesive insulating tape on the inner side edge of the heat dissipation cap A thin film copper plate regularly arranged in one direction to contact the double-sided adhesive insulating tape, a solder film formed on an inner edge of the thin film copper plate, a silver plated film formed on an outer edge of the thin film copper plate, a pad on the edge of the semiconductor chip, And a molding resin formed inside the heat dissipation cap layer except for the silver plated film, and a wire for electrically connecting the pad of the semiconductor chip and the silver plated film.

상기와 같은 구성을 갖는 본 발명 반도체 패키지의 제조방법은 세면이 조합하여 움푹패인 구조를 갖는 열방출캡층을 준비하는 단계, 상기 열방출캡층의 안쪽일면에 반도체칩을 접촉하는 단계, 박막동판의 양가장자리에 각각 솔더막과 은도금막을 도금하는 단계, 상기 도금된 박막동판의 뒷면에 양면접착 절연테이프를 접착하는 단계, 상기 박막동판을 피치에 맞게 절단하는 단계, 상기 양면접착 절연테이프를 상기 열방출캡층의 안쪽 측면에 접착하는 단계, 상기 박막동판상에 도금된 은도금막과 반도체칩이 패드를 와이어로 연결하는 단계, 상기 솔더막을 제외한 상기 열방출캡층의 안쪽을 몰딩수지로 몰딩하는 단계를 포함하여 구성되는 것을 특징으로 한다.In the method of manufacturing a semiconductor package according to the present invention having the above configuration, the steps of preparing a heat dissipation cap layer having a concave structure by combining three surfaces, the step of contacting the semiconductor chip on the inner surface of the heat dissipation cap layer, the amount of thin film copper plate Plating a solder film and a silver plated film at edges, adhering a double-sided adhesive tape to the back side of the plated thin film copper plate, cutting the thin film copper plate to a pitch, and cutting the double-sided adhesive tape to the heat dissipation cap layer Bonding the inner side of the thin film copper plate and the silver plated film and the semiconductor chip to connect the pads with wires; and molding the inside of the heat dissipation cap layer except the solder film with a molding resin. It is characterized by.

첨부 도면을 참조하여 본 발명 반도체 패키지 및 그의 제조방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a semiconductor package and a method of manufacturing the present invention will be described.

본 발명 반도체 패키지는 도 2a와 도 2b에 도시한 바와 같이 열방출캡층(21) 안쪽의 소정영역상에 패들(22)이 있고, 상기 패들(22)상에 반도체칩(23)이 있다. 여기서 상기 열방출캡층(21)은 가장자리 상부가 2단으로 일정한 경사를 갖고 형성되었으며, 상기 열방출캡층(21)의 2단으로 각진 양측가장자리 상부에 양면접착 절연테이프(24)가 부착되어 있다. 그리고 상기 양면접착 절연테이프(24)상에는 박막동판(25)이 접착되어 있고, 상기 박막동판(25)의 안쪽 가장자리 상부에는 은도금막(26)이 형성되어 있고, 상기 박막동판(25)의 바깥쪽 가장자리 상부에는 솔더(solder)막(27)이 형성되어 있다. 그리고 상기 반도체칩(23)의 가장자리를 따라 패드(28)가 있고, 상기 패드(28)와 은도금막(26)은 와이어(29)로 연결되어 있다. 그리고 상기 솔더막(27)을 제외한 나머지 영역은 몰딩수지(30)로 몰딩되어 있다.In the semiconductor package according to the present invention, as illustrated in FIGS. 2A and 2B, the paddle 22 is disposed on a predetermined region inside the heat dissipation cap layer 21, and the semiconductor chip 23 is disposed on the paddle 22. Here, the heat dissipation cap layer 21 is formed with an inclined upper end at two stages, and a double-sided adhesive insulating tape 24 is attached to the upper edges of both sides of the heat dissipation cap layer 21 at two ends. A thin film copper plate 25 is adhered to the double-sided adhesive insulating tape 24, and a silver plated film 26 is formed on an inner edge of the thin film copper plate 25, and an outer side of the thin film copper plate 25 is formed. A solder film 27 is formed on the upper edge. A pad 28 is formed along the edge of the semiconductor chip 23, and the pad 28 and the silver plating layer 26 are connected by a wire 29. The remaining region except for the solder layer 27 is molded with the molding resin 30.

그리고 상기 열방출캡층(21)은 금속으로 형성되어 있으며 리드프레임(Lead Frame)의 패들과 몰드 캐비티(Mold Cavity)의 역할을 동시에 할 수 있고 열방출 능력이 탁월하다.In addition, the heat dissipation cap layer 21 is formed of a metal, and can simultaneously play a role of a paddle and a mold cavity of a lead frame, and has excellent heat dissipation capability.

상기와 같은 구성을 갖는 본 발명 반도체 패키지에서 열방출캡층(21)과 접촉되면서 양 가장자리 상부에 솔더막(27)과 은도금막(26)이 증착된 박막동판(25)을 포함한 부분의 제작방법에 대하여 설명하면 다음과 같다.In the method of manufacturing a portion including the thin film copper plate 25 in which the solder film 27 and the silver plated film 26 are deposited on both edges of the semiconductor package according to the present invention having the above configuration while being in contact with the heat dissipation cap layer 21. The description is as follows.

먼저 박막동판(25)상의 양 가장자리상부에 솔더막(27)과 은도금막(26)을 도금한다. 이후에 도금된 박막동판(25)의 반대면에 양면접착 절연테이프(24)를 붙인다. 그리고 도 2b와 같이 구성하기 위하여 박막동판(25) 및 양면접착 절연테이프(24)를 피치에 맞게 절단한다.First, the solder film 27 and the silver plated film 26 are plated on both edges of the thin film copper plate 25. Thereafter, a double-sided adhesive insulating tape 24 is attached to the opposite surface of the plated thin film copper plate 25. In addition, the thin film copper plate 25 and the double-sided adhesive insulating tape 24 are cut to fit the pitch as shown in FIG. 2B.

이후에 양면접착 절연테이프(24)를 상기 열방출캡층(21) 안쪽의 가장자리 상부에 접착시킨다.After that, the double-sided adhesive insulating tape 24 is bonded to the upper edge of the heat dissipation cap layer 21.

상기와 같은 본 발명 반도체 소자의 패키지는 다음과 같은 효과가 있다.The package of the semiconductor device of the present invention as described above has the following effects.

첫째, 리드프레임(Lead Frame)의 패들과 몰드 캐비티(Mold Cavity)의 역할을 동시에 할 수 있는 열방출캡층을 이용하므로 측면 및 상부로 열방출이 잘된다.First, the heat dissipation cap layer that can play the role of a paddle and mold cavity of the lead frame at the same time is well used to heat the side and top well.

둘째, 리드프레임을 사용하지 않으므로 아웃리드 트리밍 및 포밍공정이 필요없고 또한 리드 솔더링 공정도 하지 않아도 되므로 공정이 단순화된다.Second, the process is simplified because no leadframe is used, which eliminates the need for outlead trimming and forming processes and also eliminates lead soldering.

셋째, 박막동판을 사용하므로 핀피치를 구현하기가 용이하다.Third, since the thin film copper plate is used, it is easy to implement the pin pitch.

넷째, 리드프레임을 사용하지 않고 열방출캡층을 사용하므로 몰드 캐비티가 필요없고 초박형 및 실장의 집적도를 증대시킬 수 있다.Fourth, since the heat dissipation cap layer is used instead of the lead frame, the mold cavity is not required and the integration degree of the ultra-thin and mounting can be increased.

Claims (3)

세면이 조합하여 움푹 패이도록 구성된 열방출캡층, 상기 열방출캡의 안쪽 하부면상에 접하고 있는 반도체칩, 상기 열방출 안쪽 측면 가장자리에 양면접착 절연테이프, 상기 양면접착 절연테이프와 접촉되도록 일방향으로 규칙적으로 배열된 박막동판, 상기 박막동판의 안쪽 가장자리상에 형성된 솔더막, 상기 박막동판 바깥쪽 가장자리상에 형성된 은도금막, 상기 반도체칩 가장자리 상에 패드, 상기 반도체칩의 패드와 상기 은도금막을 전기적으로 연결하는 와이어, 상기 은도금막을 제외한 상기 열방출캡층안쪽에 형성된 몰딩수지를 포함하여 구성되는 것을 특징으로 하는 반도체 패키지.A heat dissipation cap layer configured to pit in combination with three surfaces, a semiconductor chip in contact with an inner lower surface of the heat dissipation cap, a double-sided adhesive tape on the inner side edges of the heat dissipation, and regular contact in one direction to contact the double-sided adhesive tape An arrayed thin film copper plate, a solder film formed on an inner edge of the thin film copper plate, a silver plated film formed on an outer edge of the thin film copper plate, a pad on the edge of the semiconductor chip, and electrically connecting the pad of the semiconductor chip and the silver plated film. And a molding resin formed inside the heat dissipation cap layer except for the silver plating layer. 제1항에 있어서, 상기 열방출캡층은 안쪽 측면이 이단의 스텝을 갖고 경사지도록 구성되는 것을 특징으로 하는 반도체 패키지.The semiconductor package according to claim 1, wherein the heat dissipation cap layer is configured such that an inner side surface is inclined with two steps. 세면이 조합하여 움푹패인 구조를 갖는 열방출캡층을 준비하는 단계, 상기 열방출캡층의 안쪽 일면에 반도체칩을 접촉하는 단계, 박막동판의 양가장자리에 각각 솔더막과 은도금막을 도금하는 단계, 상기 도금된 박막동판의 뒷면에 양면접착 절연테이프를 접착하는 단계, 상기 박막동판을 피치에 맞게 절단하는 단계, 상기 양면접착 절연테이프를 상기 열방출캡층의 안쪽 측면에 접착하는 단계, 상기 박막동판상에 도금된 은도금막과 반도체칩이 패드를 와이어로 연결하는 단계, 상기 솔더막을 제외한 상기 열방출캡층의 안쪽을 몰딩수지로 몰딩하는 단계를 포함하여 구성되는 것을 특징으로 하는 반도체 패키지의 제조방법.Preparing a heat dissipation cap layer having a concave structure by combining three surfaces, contacting a semiconductor chip with an inner surface of the heat dissipation cap layer, plating a solder film and a silver plated film on both edges of the thin film copper plate, and the plating Adhering a double-sided adhesive insulating tape to the back surface of the thin film copper plate, cutting the thin film copper plate to a pitch, adhering the double-sided adhesive insulating tape to an inner side surface of the heat dissipating cap layer, plating on the thin film copper plate The method of manufacturing a semiconductor package comprising the step of connecting the pad with a silver plated film and a semiconductor chip, the molding of the inside of the heat dissipation cap layer except the solder film with a molding resin.
KR1019970077100A 1997-12-29 1997-12-29 Semiconductor package and method for fabricating the same Expired - Fee Related KR100252862B1 (en)

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