JPH0333068Y2 - - Google Patents
Info
- Publication number
- JPH0333068Y2 JPH0333068Y2 JP1985146750U JP14675085U JPH0333068Y2 JP H0333068 Y2 JPH0333068 Y2 JP H0333068Y2 JP 1985146750 U JP1985146750 U JP 1985146750U JP 14675085 U JP14675085 U JP 14675085U JP H0333068 Y2 JPH0333068 Y2 JP H0333068Y2
- Authority
- JP
- Japan
- Prior art keywords
- heat dissipation
- resin
- stud
- packages
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
【考案の詳細な説明】
〔概要〕
半導体チツプの放熱性を向上するためにチツプ
を装着するステージの下部に放熱スタツドを設
け、プリント配線基板を通して放熱する構造。[Detailed explanation of the idea] [Summary] In order to improve the heat dissipation of semiconductor chips, a heat dissipation stud is provided at the bottom of the stage on which the chips are mounted, and the heat is dissipated through the printed wiring board.
本考案は放熱性を向上した半導体パツケージの
構造に関する。
The present invention relates to the structure of a semiconductor package with improved heat dissipation.
半導体チツプを格納するパツケージには金属ケ
ース或いはセラミツクケースを使用するハーメチ
ツクシール形のものと樹脂を使用する樹脂モール
ド形のものとがあるが、本考案は後者の改良に関
するものである。 There are two types of packages for storing semiconductor chips: hermetic seal type packages that use a metal case or ceramic case, and resin mold type packages that use resin.The present invention relates to an improvement of the latter type.
半導体素子の特性は微量な不純物や湿気の含有
によつて大幅に変化し、劣化することから信頼性
を保持するためにはこの影響を無くすることが必
要であり、当初は半導体チツプ（以下略してチツ
プ）をハーメチツクシールパツケージに格納して
湿気や不純物の侵入を遮断していた。 The characteristics of semiconductor elements change significantly and deteriorate due to the presence of small amounts of impurities and moisture, so it was necessary to eliminate this effect in order to maintain reliability. (chips) were stored in hermetically sealed packages to prevent moisture and impurities from entering.
然し、半導体素子へのパツシベーシヨン（不動
態化）技術の進歩によつて耐湿性の確保には必ず
しもパツケージを必要としなくなり、そのためハ
ーメチツクシールパツケージに代わつて樹脂モー
ルドパツケージが普遍化してきた。 However, with advances in passivation technology for semiconductor devices, packages are no longer necessary to ensure moisture resistance, and therefore resin molded packages have become commonplace in place of hermetically sealed packages.
第３図は従来の樹脂モールドパツケージの構造
と装着方法を示すものである。
FIG. 3 shows the structure and mounting method of a conventional resin molded package.
ここでチツプ１はリードフレームを構成するス
テージ２の上に例えば金シリコン（Au・Si）の
共晶ボンデイング或いは銀（Ag）ペーストを用
いて接着固定した後、チツプ１の周囲にパターン
形成されている多数のパツドとこれに対応してい
るインナーリード３の先端とをAu線４などを用
いてワイヤボンデイングする。 Here, the chip 1 is bonded and fixed onto the stage 2 constituting the lead frame using, for example, eutectic bonding of gold silicon (Au/Si) or silver (Ag) paste, and then a pattern is formed around the chip 1. Wire bonding is performed using Au wire 4 or the like to connect a large number of pads to the tips of the corresponding inner leads 3.
ここで図示を省略したリードフレームは鉄・ニ
ツケル・銅（Fe・Ni・Cu）合金からなる薄板を
打抜き成形して作られた帯状のもので、これには
チツプ１を搭載するステージ２と外部配線と接続
する多数のインナーリード２が打抜き成形されて
一列に並んでおり、これらは後でプレス切断で取
り除かれる多数の接続部でリードフレームに固定
されている。 The lead frame (not shown) is a belt-shaped piece made by punching and forming a thin plate made of iron, nickel, and copper (Fe, Ni, and Cu) alloy. A large number of inner leads 2 to be connected to the wiring are punched and formed and lined up in a row, and these are fixed to the lead frame with a large number of connection parts that are later removed by press cutting.
そしてチツプ１の装着の終わつたリードフレー
ムは樹脂注型用金型に位置決めして樹脂注型を行
うが、これにはエポキシ樹脂を低圧トランスフア
モールドしたものが多く用いられている。 After the chip 1 has been mounted, the lead frame is positioned in a resin casting mold and resin casting is performed, and low pressure transfer molding of epoxy resin is often used for this purpose.
次に硬化した樹脂成形体のついたリードフレー
ムは金型から取り出した後、ステージ２とインナ
ーリード３をリードフレームに固定している接続
部をプレス切断した後、インナーリード３を屈曲
することによりジユアルインライン構造をとる多
数の樹脂モールドパツケージが完成している。 Next, the lead frame with the cured resin molded body is taken out of the mold, the connection parts that fix the stage 2 and the inner leads 3 to the lead frame are press cut, and the inner leads 3 are bent. A number of resin molded package cages with dual in-line structures have been completed.
第３図はかかる樹脂モールドパツケージをプリ
ント配線基板５のスルーホール６に挿着した後、
フローソルダリング法などにより半田付けし、プ
リント配線基板上の配線パターン７に回路接続し
た状態を示している。 FIG. 3 shows that after the resin molded package is inserted into the through hole 6 of the printed wiring board 5,
The circuit is shown connected to the wiring pattern 7 on the printed wiring board by soldering using a flow soldering method or the like.
樹脂モールドパツケージ（以下略して樹脂パツ
ケージ）はこのようにして使用されており、ハー
メチツクシールパツケージに比較して低価格であ
るため広く一般に使用されているが、樹脂は熱伝
導度が低いために消費電力の大きなIC素子には
使えないと云う欠点があり、この解決が望まれて
いた。 Resin molded packages (hereinafter referred to as resin packages) are used in this way, and are widely used because they are cheaper than hermetically sealed packages, but because resin has low thermal conductivity. However, it has the disadvantage that it cannot be used for IC elements with large power consumption, and a solution to this problem has been desired.
以上記したように樹脂パツケージはメタルシー
ル或いはセラミツクシールパツケージと比較する
と低コストであり、パツシベーシヨン技術の進歩
によつて特性的にも充分に使用が可能であるが、
樹脂は熱抵抗が高いために消費電力の大きな素子
実装には向かないことが問題である。
As mentioned above, resin packages are lower in cost than metal seals or ceramic seal packages, and with advances in packaging technology, they can be used satisfactorily in terms of characteristics.
The problem is that resin has a high thermal resistance, making it unsuitable for mounting devices with large power consumption.
上記の問題は半導体チツプを装着する樹脂モー
ルドパツケージ用ステージの下部に放熱スタツド
を設け、該スタツドを放熱パターンを設けたプリ
ント配線基板のスルーホールに挿入して使用する
することを特徴とする半導体パツケージの使用に
より解決することができる。
The above problem can be solved by using a semiconductor package in which a heat dissipation stud is provided at the bottom of a resin mold package stage on which a semiconductor chip is mounted, and the stud is inserted into a through hole of a printed wiring board provided with a heat dissipation pattern. This can be solved by using .
本考案は樹脂パツケージの放熱性を改善する方
法としてステージに放熱スタツドを設け、これを
通して熱放散を行うことにより樹脂パツケージ全
体としての熱抵抗を低下させるものである。
The present invention is a method of improving the heat dissipation of a resin package by providing a heat dissipation stud on the stage, and by dissipating heat through this stud, the thermal resistance of the resin package as a whole is lowered.
第１図は本考案に係るICパツケージの装着状
態を示す断面図である。
FIG. 1 is a cross-sectional view showing the installed state of the IC package according to the present invention.
ここで従来と異なる所はチツプ１の装着が行わ
れるステージ２と裏面に放熱スタツド８が設けら
れていることと、この放熱スタツド８が挿着され
るプリント配線基板のスルーホールの周辺に放熱
パターン９が設けられていることである。 The difference from the conventional stage is that a heat dissipation stud 8 is provided on the back side of the stage 2 where the chip 1 is mounted, and a heat dissipation pattern is provided around the through hole of the printed wiring board into which the heat dissipation stud 8 is inserted. 9 is provided.
ここで放熱スタツド８は第２図Ａ，Ｂに斜視図
を示すようにステージとの接合面９は角状でもデ
イスク状の何れでもよく、また材質は熱伝導が良
く、酸化しにくい金属であれば何れでもよい。 As shown in perspective views in FIGS. 2A and 2B, the heat dissipation stud 8 may have a joint surface 9 with the stage either square or disc-shaped, and may be made of a metal that has good thermal conductivity and is resistant to oxidation. Anything is fine.
本実施例においてはリードフレームと同じ材料
であるFe・Ni・Cu合金を用い、チツプ１と同じ
５mmの角状で直径２mmのリード１０を備えたもの
を使用した。 In this example, the lead frame was made of Fe-Ni-Cu alloy, which is the same material as the lead frame, and had the same 5 mm square lead 10 as the chip 1 and a 2 mm diameter lead 10.
かかる放熱スタツド８はステージ２に鑞付けな
どの方法で融着固定されている。 The heat dissipation stud 8 is fused and fixed to the stage 2 by brazing or the like.
そして樹脂モールドはリード１０が一部突出し
た状態で従来どおりに行われ、第１図に示すよう
な樹脂パツケージができあがる。 Resin molding is then carried out in the conventional manner with the leads 10 partially protruding, and a resin package as shown in FIG. 1 is completed.
次にプリント配線基板５で放熱スタツド８のリ
ード１０の挿入が行われる部分のスルーホール６
にはこれと連続して配線パターンと同じ放熱パタ
ーン９があつて放熱を助けている。 Next, a through hole 6 in the part of the printed wiring board 5 into which the lead 10 of the heat dissipation stud 8 is inserted.
A heat dissipation pattern 9, which is the same as the wiring pattern, is continuous to this and helps in heat dissipation.
以上のように発熱するチツプ１に連続して放熱
スタツド８を設けることにより、従来はインナー
リード３を通してのみ放熱が行われていたのに較
べ、放熱効果は格段に改良された。 By providing the heat dissipation stud 8 continuously on the chip 1 which generates heat as described above, the heat dissipation effect is significantly improved compared to the conventional method where heat was dissipated only through the inner leads 3.
従来のセラミツクパツケージの綜合熱抵抗は約
30℃／Ｗであり、これに比較して樹脂パツケージ
の熱抵抗は20〜30％大きく、そのため消費電力が
2Wを越すチツプについては樹脂パツケージの使
用は困難であつたが、本考案の実施により約５
℃／Ｗの熱抵抗の低減が可能となり、そのため従
来のセラミツクパツケージと同様な使用が可能と
なつた。
The total thermal resistance of conventional ceramic packages is approximately
30℃/W, and compared to this, the thermal resistance of the resin package is 20 to 30% higher, which reduces power consumption.
It was difficult to use resin packages for chips exceeding 2W, but by implementing this invention, approximately 5
It has become possible to reduce the thermal resistance in degrees Celsius/W, and therefore it has become possible to use it in the same way as conventional ceramic packages.
第１図は本考案に係るICパツケージの装着状
態を示す断面図、第２図Ａ，Ｂは本考案に係る放
熱スタツドの斜視図、第３図は従来のICパツケ
ージの装着状態を示す断面図、である。
図において、１はチツプ、２はステージ、３は
インナーリード、５はプリント配線基板、６はス
ルーホール、７は配線パターン、８は放熱スタツ
ド、９は放熱パターン、である。
Fig. 1 is a cross-sectional view showing the mounted state of the IC package according to the present invention, Fig. 2 A and B are perspective views of the heat dissipation stud according to the present invention, and Fig. 3 is a cross-sectional view showing the mounted state of the conventional IC package. , is. In the figure, 1 is a chip, 2 is a stage, 3 is an inner lead, 5 is a printed wiring board, 6 is a through hole, 7 is a wiring pattern, 8 is a heat radiation stud, and 9 is a heat radiation pattern.
Claims (1)
ージ用ステージ２の下部に放熱スタツド８を設
け、該スタツド８を放熱パターン９を設けたプリ
ント配線基板５のスルーホール６に挿着して使用
することを特徴とする半導体パツケージ。 A heat dissipation stud 8 is provided at the lower part of the resin mold package stage 2 on which the semiconductor chip 1 is mounted, and the stud 8 is used by being inserted into a through hole 6 of a printed wiring board 5 provided with a heat dissipation pattern 9. semiconductor package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985146750U JPH0333068Y2 (en) | 1985-09-26 | 1985-09-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985146750U JPH0333068Y2 (en) | 1985-09-26 | 1985-09-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6255354U JPS6255354U (en) | 1987-04-06 |
| JPH0333068Y2 true JPH0333068Y2 (en) | 1991-07-12 |
Family
ID=31059500
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985146750U Expired JPH0333068Y2 (en) | 1985-09-26 | 1985-09-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0333068Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7772036B2 (en) * | 2006-04-06 | 2010-08-10 | Freescale Semiconductor, Inc. | Lead frame based, over-molded semiconductor package with integrated through hole technology (THT) heat spreader pin(s) and associated method of manufacturing |
-
1985
- 1985-09-26 JP JP1985146750U patent/JPH0333068Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6255354U (en) | 1987-04-06 |
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