KR100242389B1 - Voltage controlled oscillater - Google Patents

Abstract

The present invention relates to a voltage controlled oscillator, comprising an input and an output, an input bias signal, an output bias signal and a feedback signal, and a logic value of a plurality of first selection signals or a plurality of second selection signals, which are digital signals of binary logic values. And a plurality of delay units connected in series to form a plurality of delay groups so as to be mutually distinguishable based on the input first selection signal, and adjacent delay units of the plurality of delay unit groups. First switching means each connected to the middle of a feedback path formed between the groups, the first switching means being turned on when the first select signal activates any delay unit to connect the feedback path, In the two delay groups, the bias signal output at the last delay of the preceding delay group is trailing. A second switching means coupled between the bias signal inputs of the initial delay portion of the soft group, the second selection means being turned on together to connect the propagation path of the bias signal when the first select signal is selected and activated By using a predetermined selection signal, some or all of the plurality of delay means can be selectively activated to provide an effect of varying the frequency band of the output signal as necessary.

Description

Voltage controlled oscillator

The present invention relates to a voltage controlled oscillator, and more particularly, to a voltage controlled oscillator capable of varying an output frequency band by a combination of simple selection signals.

Generally, a phase-locked loop circuit (PLL) is a field in which voltage-controlled oscillators are frequently used. The phase locked loop circuit is a circuit for the purpose of compensating the phase difference between the two signals by comparing the frequency of the input signal with the frequency of the reference signal.

In FIG. 1, the configuration of the phase locked loop circuit is shown in block units.

In the frequency divider 1, the input signal is divided into a predetermined value N and transmitted to the phase frequency detector 2. The output signal of the phase frequency detector 2 is converted into a direct current signal while passing through the low pass filter 3 and transmitted to the voltage controlled oscillator 4. The output signal fout of the voltage controlled oscillator 4 is the output signal of the phase locked loop circuit, and this output signal fout is divided into a predetermined value M through another frequency divider 5 and thus the above-described phase. It is fed back to the frequency detector 2.

The phase frequency detector 2 to which the feedback signal is input detects the phase of the signal transmitted from the divider 1 and the phase of the feedback signal, and outputs a pulse signal having a pulse width proportional to the phase difference.

This pulse signal is converted into the DC signal by the low pass filter 3 described above and input to the voltage controlled oscillator 4.

Since the voltage controlled oscillator 4 generates an output signal which is inversely proportional to the voltage magnitude of the input signal fin, the gain of the voltage controlled oscillator 4 has a unit of frequency / voltage. That is, the gain is inversely proportional to the magnitude of the voltage and proportional to the magnitude of the frequency.

The pulse signal and pulse width output from the phase frequency detector 2 depend on the phase difference between the input signal and the reference signal fed back.

If the frequency of the input signal is greater than the frequency of the reference signal, the magnitude of the voltage input to the voltage controlled oscillator 4 will decrease. If the frequency of the input signal is less than the frequency of the reference signal, the input to the voltage controlled oscillator 4 The magnitude of the voltage becomes large.

Since the voltage controlled oscillator 4 generates a gain inversely proportional to the magnitude of the input voltage, the frequency of the feedback signal is inversely proportional to the magnitude of the input voltage to perform an operation of matching the magnitude of the reference voltage with the magnitude of the input voltage. .

A circuit commonly applied to such a voltage controlled oscillator 4 is a ring oscillator.

2 is a diagram showing a general configuration of a ring oscillator. As shown in FIG. 2, the ring oscillator 4 has a plurality of delay means D1 to D5 connected in series to delay the input signal fin to generate an output signal fout, and this output signal fout It feeds back to the input and forms a loop, causing oscillation.

The ring oscillator 4 also changes the frequency of the output signal fout according to the voltage of the input signal fin. The frequency band is determined by the number of delay means provided and the delay time of each delay means.

That is, the frequency of the output signal fout of the ring oscillator 4 is determined by the following equation.

[Equation 1]

In Equation 1 above, N is the number of delay means provided, and t _d is the delay time of each delay means.

Therefore, if the number of delay means or the delay time of each delay means is changed, the frequency of the output signal fout can be changed. However, the ring oscillator 4 as shown in FIG. 2 has a fixed number of delay means. This inevitably generates a single bandwidth of frequency.

In order to obtain frequency signals with various bandwidths, there are only a plurality of phase locked loop circuits having such ring oscillators.

However, if you have as many phase-locked loop circuits as you need, the circuitry will increase layout, consume power or increase, and if more frequency bands are needed, you will need to redesign the circuit to meet them. A problem arises.

Accordingly, an object of the present invention is to provide a voltage controlled oscillator capable of selectively activating a part or all of a plurality of delay means by using a predetermined selection signal and varying a frequency band of an output signal as necessary.

1 is a block diagram showing the configuration of a conventional phase locked loop circuit.

2 is a block diagram showing the configuration of a voltage controlled oscillator of a conventional phase locked loop circuit.

3 is a block diagram showing a voltage controlled oscillator of the present invention.

4 is a block diagram showing a delay unit of the voltage controlled oscillator of the present invention. FIG. 4 (a) shows a general configuration of a plurality of delay units. FIG. 4 (b) shows a final output signal among a plurality of delay units. Figure showing a delay to be made.

5 is a circuit diagram showing a switch of a delay unit of the present invention.

6 is a circuit diagram simplifying the configuration of the delay unit of the present invention.

7 is a circuit diagram showing a delay cell of a delay unit of the present invention.

* Explanation of symbols for main parts of the drawings

1,5 divider 2: phase frequency detector

3: low pass filter 4: voltage controlled oscillator

B: Divider control bit D1 ~ D7: Delay cell

fin, fin ′: input signal fout, fout ′: output signal

b, bin ′: Bias signal C1 to C3: Column signal

R1 to R3: Low signal R [j, k]: Delay

CTRL: Delay part control signal SW1 ~ SW9: Switch

Q1 to Q11: MOS transistor OR1, OR9: Or gate

An embodiment of the present invention will be described with reference to FIGS. 3 to 7 as follows.

3 is a block diagram showing a voltage controlled oscillator according to the present invention.

In one embodiment of the voltage controlled oscillator of the present invention shown in FIG. 3, nine delay units P [1,2] to P [17] having feedback paths are connected in series.

Each of the delay units P [1, 2] to P [17] has a predetermined input / output signal and a selection signal. FIG. 4 (a) shows a general configuration of a plurality of delay units. b) is a diagram showing a delay unit for generating a final output signal among a plurality of delay units, and other delay units P [3,4] to P [15,16] are the same and thus not shown.

The input signal has an input signal fin 'and an input bias signal bin', and the output signal has an output signal fout 'and an output bias signal bout', and the selection signal is a column signal C1 to C3. And low signals R1 to R3, and the delay units P [1,2] to P [17] generate feedback signals FB.

The first delay unit P [1,2] of the plurality of delay units P [1,2] to P [17] has an input signal fin and a bias signal b transmitted from the front end of the voltage controlled oscillator. Becomes the input signals fin 'and (bin'), and the output signal fout 'of the final delay unit P [17] is the output signal fout of the voltage controlled oscillator of the present invention and thus the voltage of the present invention. To the next stage of the control oscillator.

Each of the delay units P [1,2] to P [17] is grouped with three delay units selected by one column signal C at the same time, and each row signal R1 to R3 is selected as a delay unit. Select the first delay part, the second delay part, and the third delay part of the group, respectively.

That is, the first delay unit groups P [1,2] to P [5,6] are selected by the column signal C1 and the low signals R1 to R3, respectively, and the second delay unit group P [ 7,8] to P [11,12] are selected by another column signal C2 and low signal R1 to R3, and the third delay group P [13,14] to P [17]. Is selected by the column signal C3 and the low signals R1 to R3.

The feedback paths of the feedback signals FB generated in the respective delay units P [1, 2] to P [17] are also turned on / off by the switching means. In the case of the delay groups P [1,2] to P [5,6], the feedback is directly fed to the input terminal without the switching means.

That is, the feedback signal generated in the remaining delay group groups P [7,8] to P [11,12] except for the delay unit groups P [1,2] to P [5,6] described above is switched. Input signal of the first delay unit P [1,2] of the above-described delay unit groups P [1,2] to P [5,6] by being turned on and off by the in-enMOS transistor Q1. (fin ′) Feedback to the input.

The other delay unit groups P [13, 14] to P [17] are also controlled on and off by the NMOS transistor Q3, which is a switching means, so that the aforementioned delay unit groups P [7,8] to P [ 11, 12] is fed back to the input signal (fin ') input terminal of the delay unit (P [7, 8]).

In this way, the gates of the NMOS transistors Q1 and Q3 that control the feedback path on and off are controlled by the column signals C1 and C2, respectively. Therefore, the feedback between each delay group is made only when the column signals C1 (C2) D are at the high level, that is, the logical value "1".

The propagation path is controlled on and off by the switching means provided between the bias signals b in the grouped delay units.

That is, the output bias signal bout 'of the last delay unit P [5,6] of the delay unit groups P [1,2] to P [5,6] is turned on by the NMOS transistor Q2. It is controlled off and transmitted to the input bias signal bin 'input terminal of the first delay section P [7,8] of delay group P [7,8] -P [11,12].

In another delay group P [7,8] to P [11,12], the output bias signal bout 'of the last delay unit P [12] is turned on and off by the NMOS transistor Q4. It is controlled and transmitted to the input bias signal bin 'input terminal of the first delay units P [13, 14] of the delay units P [13, 14] to P [17].

In this way, the gates of the NMOS transistors Q2 and Q4 that control the bias voltage b transfer path on and off are controlled by the column signals C1 and C2, respectively. Therefore, the transfer of the bias signal between each delay group is made only when the column signals C1 and C2 are logical values "1".

Therefore, when the column signal C2 is the logic value "1", since the column signal C1 must also be the logic value "1", the voltage controlled oscillator of the present invention is provided with a column encoder having input / output characteristics as shown in Table 1 below. Generate a column signal to control.

The low signals R1 to R3 are also generated in the same manner as the above-described column signals C1 to C3. That is, the input / output characteristics of the row encoder for generating the row signals R1 to R3 are shown in Table 2 below.

As shown in Tables 1 and 2, the column signals C1 to C3 and the row signals R1 to C, depending on the combination of the input signals Ca and Cb of the column encoder and the input signals Ra and Rb of the row encoder. By generating R3), it is possible to generate both the required column signal and the low signal with all 4-bit signals.

Such a delay unit of the voltage controlled oscillator of the present invention will be described with reference to FIG.

FIG. 4 (a) shows the general configuration of the delay unit except the delay unit of the output stage among the delay units constituting the voltage controlled oscillator using the delay unit P [1, 2] of the input stage as an example. Shown is the last delay section P [17] connected to the output stage.

As shown in FIG. 4 (a), the input signal fin 'is input to the switch SW1 via the primary delay cell D1.

The switch SW1 generates two output signals OUT1 and OUT2 by the control signal CTRL, among which the output signal OUT1 is input of the secondary delay cell D2 and the remaining output signals OUT2. ) Becomes the feedback signal FB.

An output signal fout 'is generated in the secondary delay cell D2. An input bias signal bin' is input to the delay cells D1 and D2.

In this case, the NMOS transistor Q5, which is a switching element, is connected to a path through which the input bias signal bin ′ transmitted to the primary delay cell D1 is transmitted to the secondary delay cell D2. The NMOS transistor Q5 is controlled on and off by the control signal CTRL together with the switch SW1 described above. An input bias is input to the secondary delay cell D2 only when the NMOS transistor Q5 is turned on. The signal bin 'may be transmitted.

As such, the control signal CTRL of the switch SW1 and the NMOS transistor Q5 is generated as a result of the OR operation of the column signal C1 and the low signal R1. The column signal C1 and the low signal R1 are generated. Is input to the OR gate OR1, and the output signal is immediately the control signal CTRL.

Another delay unit P [17] shown in FIG. 4 (b) also has a structure similar to that of the delay units P [1,2] described above, but includes only one delay cell D17 and is a switching element. NMOS transistors are not needed.

The reason for having only one delay cell as described above is that only the feedback signal needs to be generated in the final delay part, and in order to obtain an output signal having an inverted phase of the input signal, an odd number of delay cells are required. This is because only one delay cell D17 that generates a feedback signal is sufficient.

Therefore, as shown in FIG. 4 (b), the input signal fin 'is input to the switch SW9 via the delay cell D17.

The switch SW9 generates two output signals OUT1 and OUT2 by the control signal CTRL, among which the output signal OUT1 is the output signal fout 'of the delay unit P [17]. The remaining output signal OUT2 becomes the feedback signal FB.

The input bias signal bin 'is input to the delay cell D17, and the control signal CTRL is input to the switch SW9. The control signal CTRL is generated as a result of OR operation of the column signal C3 and the low signal R3. The column signal C3 and the low signal R3 are input to the OR gate OR9, and the output signal thereof is inputted. Soon it becomes a control signal CTRL.

Among the common components of the delay units P [1, 2] to P [17] shown in FIGS. 4A and 4B, the switches SW1 and SW9 are configured as shown in FIG.

The control signal CTRL is input to the gates of the NMOS transistor Q6 and the PMOS transistor Q7, respectively.

The sources of the NMOS transistor Q6 and the PMOS transistor Q7 are connected to each other to form an input terminal, and the respective gates are controlled on and off by the control signal CTRL output from the OR gate OR1 so that each of them is controlled. In the drain, two different output signals OUT1 and OUT2 are alternately generated.

That is, when the control signal CTRL is at the high level, the NMOS transistor Q6 is turned on to generate the output signal OUT1. On the contrary, when the control signal CTRL is at the low level, the PMOS transistor Q7 is turned on. Is turned on to generate the output signal OUT2.

The input / output characteristics of the delay unit according to the present invention are classified into a case selected by the column and a row signal and a case that is not selected, and are described with reference to Table 3 below and FIG. 6 of the accompanying drawings.

Table 3 above shows the input / output characteristics of the delay unit of the present invention, and FIG. 6 of the accompanying drawings is a simplified and reconfigured part of the components of the delay unit P [1,2] of the present invention. The delay cells D1 and D2 are respectively represented as tristate inverters operated by an input bias signal bin 'and an output bias signal bout' to generate an output signal having an inverted phase of the input signal. In both cases of Tables 3 and 6, the delay unit P [1, 2] is taken as an example.

The detailed configuration of the delay cell of the delay unit of the present invention described above is shown in FIG.

The source of the NMOS transistor Q8 whose gate is controlled by the input bias signal bin 'is connected to the power supply voltage VDD terminal, and the NMOS transistor whose gate is controlled by the input bias signal bin' is also provided. The source of Q11) is grounded.

Between the two NMOS transistors Q8 and Q11 described above, a PMOS transistor Q9 and an NMOS transistor Q10 whose gate are controlled by an input signal fin ′ are connected in series to form an inverter. Cell D is formed.

As shown in Tables 3 and 6, if the logic value of the control signal CTRL is "0", the NMOS transistor Q5 is turned off and the output bias signal bout 'is not generated.

In addition, since the NMOS transistor Q6 is also turned off and the output bias signal bout 'does not occur as described above, the output signal fout' of the delay cell D2 does not occur.

However, the PMOS transistor Q7 is turned on so that the output signal of the primary delay cell D1 (that is, the input signal IN of the switch SW) is output as the feedback signal FB. At this time, the output feedback signal FB is input. It has a phase opposite to the signal fin '.

As described above, the occurrence of the PMOS transistor signal FB means that the primary delay cells of the respective delay units are activated and the secondary delay cells are not activated.

If the control signal CTRL is a logic value of "1", the NMOS transistor Q5 is turned on to generate an output bias signal bout ', and another NMOS transistor Q6 is also turned on to turn the third delay cell. The output signal fout 'is generated through D2.

However, the PMOS transistor Q7 is turned off so that the feedback signal FB is not generated.

Therefore, the delay unit constituting the voltage controlled oscillator of the present invention is activated when at least one of the input column signal (C1 ~ C3) and the low signal (R1 ~ R3) is a logic value "1", the input column signal It is not activated when both (C1 to C3) and the low signals (R1 to R3) are the logic value "0".

However, the nth delay unit P [n-1, starting from the delay unit P [1,2] of the input stage among the plurality of delay units P [1,2] to P [17] sequentially connected. 2n]), the n + 1th delay unit P [2n + 1,2n + 2] is the portion of the two delay cells provided with the primary delay cell is activated and the secondary delay cell is not activated As a result of the activation, the output signal fout 'and the output bias signal bout' are not generated, but only a feedback signal is generated.

It should be noted that the feedback signal generated as described above is the output signal fout of the voltage controlled oscillator of the present invention.

Referring to FIG. 3, the logic value of the column signal C1 is “1”, the logic value of the remaining column signals C2 and C3 is “0”, and the logic value of the low signal R1 is “1”. And the overall operation of the voltage-controlled oscillator of the present invention when the logic value of the remaining low signals R2 and R3 is “0” and their effects are as follows.

First, a delay unit in which one or more signals having a logic value “1” among the input column signals C1 to C3 or the low signals R1 to R3 is input will be described as follows.

That is, it can be seen that the column signal C1 having a logic value of “1” is input to the three delay units P [1, 2] to P [5, 6], and the remaining delay units P [7, 8] to P [17]), a low signal R1 having a logic value of “1” is input to the delay units P [7, 8].

In addition, the NMOS transistor Q5 which controls the bias signal transfer path between the first delay unit groups P [1,2] to P [5,6] by the column signal C1 having a logic value of “1” is provided. Turned on to allow the transfer of bias signals. Because when C1 or R1 signal is input as “1”, OR1, which is an OR gate, outputs high and CTRL signal becomes high, so Q5 is on and the bias signal path is on.

Also, the first delay group P [1,2] to P [5,6] and the second delay group P [7,8] to P [by the column signal C1 of the logic value “1”. 11, 12] NMOS transistor (Q2) for controlling the bias signal transfer path between is turned on to enable the transfer of the bias signal between the two groups.

In addition, since the NMOS transistor Q1 controlling the feedback path of the second delay group P [7,8] to P [11,12] is also turned on, the second delay group P [7,8] is turned on. ] To P [11, 12]) are secured so that feedback to the input terminal of the feedback signal generated by delay unit P [9, 10] is possible.

In other words, the feedback signal generated by the above-described delay unit P [9, 10] becomes the final output signal fout of the intended voltage controlled oscillator.

However, in the delay unit P [13,142], since the column signal C2 is at the low level of the logic value “0”, the NMOS transistor Q4 for controlling the transfer path of the bias signal on and off is turned off and biased. As a result, the signal b is not transmitted, and consequently, the delay parts P [13, 14] are not connected to the overall operation of the voltage controlled oscillator of the present invention when the column signal C1 and the low signal R1 are logic values "1". Does not affect

Since the oscillation operation conditions such as the bias signal transmission path and the feedback path are satisfied, the three delay units P [1, 2] to P [5, activated by the column signal C1 having a logic value of “1” are satisfied. 6]) and up to the ninth delay cell, which is the front delay cell of the delay unit P [7,8] and delay unit P [9,10], activated by the low signal R1 of logic value “1”. Oscillation operation can be made through.

In this case, referring to the number of delay cells operating, eight delay cells D1 to D8 provided in four delay units P [1,2] to P [7,8] and a delay unit P generating a feedback signal are provided. It can be seen that all nine (that is, odd) delay cells including the delay cells D9 of [9, 10] are operated.

If the column signals C1 to C3 and the low signals R1 to R3 are combined differently, the number of activated delay units will be different, and thus the number of delay cells to be operated will be different. Therefore, the column signals C1 to C3 and the low signal R1 are different. It is possible to vary the frequency of the output signal through a combination of ~ R3).

Looking at the variable range of the output frequency that can be generated in the voltage controlled oscillator of the present invention as follows.

First, the number of delay units activated according to the combination of the column signals C1 to C3 and the low signals R1 to R3 affecting the overall operation and the number of delay cells operating accordingly are as follows.

As can be seen in Table 4 above, the embodiments of the present invention shown in FIG. 3 can selectively generate output signals of all eight frequency bands.

Accordingly, the present invention has the effect of selectively activating some or all of the plurality of delay means by using a predetermined selection signal, thereby changing the frequency band of the output signal as necessary.

Claims (7)

In a voltage controlled oscillator having a plurality of delay parts and a feedback path to an input terminal, receiving an input signal and inverting the logic state first, and then inverting the second to output an output signal having the same logic state as the logic state of the input, The delay cell is activated to receive the input bias signal and perform the first inversion operation, control the transmission path of the input bias signal to output the output bias signal, branch the first inverted input signal to output the feedback signal, and A plurality of delay units configured to control the passage of the input bias signal according to the logic value of the first selection signal or the second selection signal and to selectively output the output signal by controlling the passage of the first inverted input signal Delay group; Connecting an output signal output from the last delay unit of the preceding delay unit group of the plurality of delay unit groups to an input terminal of the first delay unit of the next group; In the adjacent two delay group among the plurality of delay groups, a feedback signal output terminal of each delay unit of a subsequent delay unit group and an input terminal of the first delay unit of the preceding delay unit group are connected, so that the first selection signal is random. First switching means which is turned on when selecting and activating a delay unit to connect a transmission path of the feedback signal; In the adjacent two delay group among the plurality of delay groups, the first select signal is connected between the bias signal output terminal of the last delay unit of the preceding delay group and the bias signal input terminal of the first delay unit of the subsequent delay group. And second switching means which are turned on together to select and activate any delay to connect the propagation path of the bias signal. The signal output from the delay side output means of the delay unit that generates a feedback signal among a plurality of delay units activated by the first control signal and the second control signal to perform an oscillation operation. Specific voltage controlled oscillators. The display apparatus of claim 1, wherein the delay unit comprises: a first input signal; A first output signal; Three switching means provided between an input terminal and an output terminal of the bias signal and turned on by a control signal to form a bias signal transmission path; First delay means driven by the bias signal and outputting the first input signal by inverting the first input signal; Fourth switching means controlled by a control signal to select one of a first path and a second path for transmitting a signal output from the first delay means; Second delay means for driving the bias signal and inverting the signal transmitted through the first path in a second order; And a first or gate configured to receive the first selection signal and the second selection signal and perform a logical sum operation to generate the control signal. The display apparatus of claim 1, wherein the delay unit comprises: a second input signal; A second output signal; Third delay means which is driven by the bias signal and inverts and outputs the second input signal primarily; Fifth switching means controlled by a control signal to select one of a third path and a fourth path for transmitting a signal output from the third delay means; And a second cucumber gate configured to receive the first selection signal and the second selection signal and perform a logical sum operation to generate the control signal. 5. The voltage controlled oscillator of claim 4, wherein the delay unit is a last delay unit of the plurality of delay units connected in series. The method according to claim 3 or 4, wherein the first to third delay means have a predetermined delay time, and are driven by the bias signal and transmitted through the first to second input signals or the first path. A voltage controlled oscillator characterized in that it is a tri-state inverter that inverts and outputs a signal. The method of claim 3 or 4, wherein the fourth and fifth switching means is turned on by the control signal, and outputs the signal output from the first delay means or the third delay means to the first path. Sixth switching means for transmitting through; And a seventh switching means which is turned on by the control signal to transmit a signal output from the first delay means or the third delay means through the second path.

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