KR100238963B1 - A repair circuit of semiconductor memory device - Google Patents

Abstract

The present invention relates to a repair circuit for a semiconductor memory device for preventing a decoding defect from occurring due to a change in an external condition when the fuse is not electrically disconnected completely. According to this circuit, when the fuse is not electrically disconnected completely, the trip point changing means is implemented at the output terminal of the inverter as an inversion means in order to prevent decoding defects caused by changes in external conditions. The trip point of the inverter can be changed during normal operation of the semiconductor memory device and verification of the state where the fuse is cut by the control signal applied to the gate of the fourth MOS transistor of the trip point changing means. Accordingly, by changing the trip point, it is possible to reduce the sensing margin between the two operations, thereby preventing decoding defects from occurring.

Description

Repair circuit of semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a repair circuit for a semiconductor memory device for preventing decoding defects caused by changes in external conditions when the fuse is not completely electrically disconnected.

An electrical repair circuit of a semiconductor memory device of a semiconductor memory device is for repairing a defect in the semiconductor memory device in a package state. By repairing the defective semiconductor memory device through the electric repair circuit, the yield of the semiconductor memory device can be greatly improved. The electric repair uses a poly fuse and decodes it by using a break of the fuse when a strong current is applied to the fuse.

FIG. 1 is a circuit diagram showing a repair circuit of a conventional semiconductor memory device.

Referring to FIG. 1, first and second power supply voltages Vcc and Vss are input through first and second power supply terminals 1 and 2, respectively, and output signal S_OUT is provided through output terminal 3. [ Is output. A fuse F1 is connected between the first power supply terminal 1 and the second power supply terminal 2. The conductive path L1 is connected to one of the first power supply voltage Vcc transmitted through the first power supply terminal 1 and the second power supply voltage Vss transmitted through the fuse F1 Respectively. A source-drain channel is connected between the first power source voltage Vcc and the output terminal 3 of the first MOS transistor Q1 whose gate is connected to the conductive path L1. A source-drain channel is connected between the output terminal 3 and the second power source terminal 2 of the second MOS transistor Q2 having a gate connected to the conductive path L1. Here, when the signal charged in the conductive path L1 is at the low level, the high level is outputted through the first MOS transistor Q1. When the signal charged in the conductive path L1 is at the high level, And an inverter outputting a low level through the second MOS transistor Q2. Here, the first MOS transistor Q1 is a p-type conductivity type channel and the second MOS transistor Q2 is a n-type conduction type channel.

In the repair circuit of the semiconductor memory device shown in FIG. 1, the channel of the first MOS transistor Q1 is turned on before the fuse F1 is cut, and a high level signal is output to the output terminal 3. When the fuse F1 is cut, the channel of the second MOS transistor Q2 is turned on to output a low level signal. When the fuse F1 is completely cut electrically, no problem occurs. However, if the fuse F1 is not electrically disconnected completely, the circuit can be operated at a temperature, an operation speed, a supply voltage Vcc and a ground noise (GND noise) And the like. When the fuse F1 is not completely disconnected electrically, it has a resistance component R1, and an equivalent circuit of this state is shown in FIG. As shown in FIG. 2, when the fuse F1 shown in FIG. 1 is not electrically disconnected completely, the output signal of the inverter 10 composed of the first and second MOS transistors Q1 and Q2 S_OUT) has a value between the two levels that are not high level and low level. If a logically changing transition point (trip point) of the inverter 10 is Vcc / 2, a voltage higher by a predetermined level than Vcc / 2 is applied to the inverter 10 To the conductive path Ll of the first conductive layer. As a result, the output signal level of the inverter 10 becomes lower than Vcc / 2 by a predetermined level, and after passing through the logic gate, it is recognized as a low level.

However, according to the repair circuit of the semiconductor memory device as described above, when the fuse F 1 is not completely cut off electrically, it is possible to prevent the fuse F 1 from being damaged by a change in external conditions such as temperature, power supply voltage Vcc, Inverter 10 outputs a logically different result. Therefore, there is a problem that a decoding defect occurs according to the change of the external condition.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a repair circuit for a semiconductor memory device for preventing decoding defects caused by changes in external conditions when the fuse is not completely electrically disconnected, .

FIG. 1 is a circuit diagram showing a repair circuit of a conventional semiconductor memory device; FIG.

Figure 2 is a circuit diagram showing the problem of Figure 1;

FIG. 3 is a circuit diagram showing a circuit of a repair circuit of a semiconductor memory device according to a preferred embodiment of the present invention; FIG.

FIG. 4 is a circuit diagram showing a circuit of a repair circuit of a semiconductor memory device according to another preferred embodiment of the present invention. FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

1: first power terminal 2: second power terminal

4: control terminal 10: inverting means

20: trip point changing means

According to an aspect of the present invention, there is provided a power supply device comprising: a first power supply terminal receiving a first power supply voltage; A second power supply terminal to which a second power supply voltage is input; An output terminal for outputting an output signal; A control terminal to which a control signal is applied from the outside; A fuse connected between the first power terminal and the second power terminal; A conductive path charged at a voltage level of a first power supply voltage transmitted through the first power supply terminal and a second power supply voltage transmitted through the fuse; An inverting means for outputting a signal inverted in phase with a signal charged in the conductive path; And trip point changing means for changing a trip point of the inverting means in response to a control signal applied through the control terminal.

In a preferred embodiment of this circuit, the trip point changing means comprises: A third MOS transistor having a source-drain channel connected between the first power supply terminal and a connection point, and a gate connected to the conductive path; And a fourth MOS transistor having a source-drain channel connected between the connection point and the output terminal, and a gate connected to the control terminal.

In a preferred embodiment of this circuit, the third and fourth MOS transistors are p-type conductivity-type channels.

With such a circuit, it is possible to prevent the occurrence of decoding defects due to changes in external conditions by changing the logical change point of the inverter.

Referring to FIG. 3, a repair circuit of a novel semiconductor memory device according to the present invention includes a first power supply terminal 1 to which a first power supply voltage Vcc is input and a second power supply terminal 1 to which a second power supply voltage Vss is input A control terminal 4 to which a control signal CS is externally applied; a first power supply terminal 1 and a second power supply terminal 2; A first power supply voltage Vcc transmitted through the first power supply terminal 1 and a second power supply voltage Vcc passing through the fuse F1; Vss), inverting means (10) for outputting a signal inverted in phase with a signal to be charged in the conductive path (L1) And a trip point changing means 20 for changing a trip point of the inverting means 10 in response to a control signal CS applied through the inverting means 10.

According to this circuit, when the fuse F1 is not electrically disconnected completely, the output terminal 3 of the inverter 10 is connected to the trip point changing means 20 ). The control signal CS applied to the gate of the fourth MOS transistor Q4 of the trip point changing means 20 causes the inverter to operate normally when the semiconductor memory device is in operation and when the fuse is cut, 10) can be changed. Accordingly, by changing the trip point, it is possible to reduce the sensing margin between the two operations, thereby preventing decoding defects from occurring.

In FIGS. 3 to 4, the same reference numerals are used for components having the same functions as the components shown in FIGS. 1 to 2.

FIG. 3 is a circuit diagram showing a repair circuit of a semiconductor memory device according to a preferred embodiment of the present invention.

Referring to FIG. 3, a first power supply voltage Vcc and a second power supply voltage Vss are input through the first and second power supply terminals 1 and 2, respectively. (S_OUT) is output. A control signal CS is externally applied to the control terminal 4 and a fuse F1 is connected between the first power terminal 1 and the second power terminal 2. [ The conductive path L1 is connected to the first power supply voltage Vcc through the first power supply terminal 1 and the second power supply voltage Vss transmitted through the fuse F1, do. The inverting means 10 outputs a signal whose phase is inverted from the signal charged in the conductive path L1 and the trip point changing means 20 outputs a control signal CS applied through the control terminal 4 , Changes the trip point of the inverting means (10).

The inverting means 10 includes a first MOS transistor Q1 connected to a source-drain channel between the first power supply terminal 1 and the output terminal 3 and a gate connected to the conductive path L1, And a second MOS transistor Q2 having a source-drain channel connected between the output terminal 3 and the second power supply terminal 2 and a gate connected to the conductive path L1. In the trip point changing means 20, the third MOS transistor Q3 whose gate is connected to the conductive path L1 is connected between the first power supply terminal 1 and the node N1, Is connected. A fourth MOS transistor Q4 having a gate connected to the control terminal 4 has a source-drain channel connected between the node N1 and the output terminal 3. [ The first MOS transistor Q1 and the third and fourth MOS transistors Q3 and Q4 are p-channel transistors and the second MOS transistor Q2 is an n-channel transistor .

FIG. 4 is a circuit diagram showing a repair circuit of a semiconductor memory device according to another preferred embodiment of the present invention.

As shown in FIG. 4, this is another embodiment in which the components and positions of the trip point changing means 20 shown in FIG. 3 are changed. The trip point changing means 30 is connected between the output terminal 3 and the second connection point with a source-drain channel connected to the control terminal 5 to which a control signal CS is applied, A transistor Q5 and a sixth MOS transistor Q6 having a gate connected to the conductive path L1 and a source-drain channel connected between the second node N2 and the second power supply terminal 2 .

Hereinafter, reference will be made to FIGS. 3 to 4 according to a preferred embodiment of the present invention.

First, after electrically disconnecting the fuse F1 shown in FIG. 3, if it is verified whether or not the fuse F1 is electrically disconnected completely, the control of the trip point changing means 20 By applying a low level signal to the terminal 4, the trip point of the inverter 10 is raised. As described above, when the trip point of the inverter 10 is changed, the logic is not changed in the verify operation when the fuse F1 is cut off with the resistance component R1, so that the electric fuse F1 can be cut again A verification function can be performed. If cutting is performed in a state where the logic is slightly changed at the time of verification, a high level signal is applied to the control terminal 4 of the trip point changing means 20 in actual operation to give a margin. Therefore, it is possible to reduce the possibility of occurrence of decoding defects according to changes in external conditions. 4, by applying a high-level signal to the control terminal 5 to which the control signal CS is externally applied in normal operation and a low-level signal in the electric repair verification mode, The same result as in the third step can be obtained.

As described above, when the fuse is not electrically disconnected completely, the trip point changing means is implemented at the output terminal of the inverter as inverting means in order to prevent decoding defects caused by changes in external conditions. The trip point of the inverter can be changed during normal operation of the semiconductor memory device and verification of the state where the fuse is cut by the control signal applied to the gate of the fourth MOS transistor of the trip point changing means. Accordingly, by changing the trip point, it is possible to reduce the sensing margin between the two operations, thereby preventing decoding defects from occurring.

Claims (3)

A first power source terminal 1 to which a first power source voltage Vcc is input; A second power supply terminal 2 to which a second power supply voltage Vss is input; An output terminal 3 for outputting an output signal S_OUT; A control terminal 4 to which a control signal CS is externally applied; A fuse F1 connected between the first power supply terminal 1 and the second power supply terminal 2; A conductive path L1 charged with a voltage level of a first power voltage Vcc transmitted through the first power terminal 1 and a second power voltage Vss transmitted through the fuse F1, Wow; Inverting means (10) for outputting a signal inverted in phase with a signal to be charged in the conductive path (L1); And trip point changing means (20) for changing a trip point of said inverting means (10) in response to a control signal (CS) applied through said control terminal (4). 2. The apparatus of claim 1, wherein the trip point changing means (20) comprises: A third MOS transistor Q3 having a source-drain channel connected between the first power supply terminal 1 and the node N1 and having a gate connected to the conductive path L1; And a fourth MOS transistor (Q4) having a source-drain channel connected between the node (N1) and the output terminal (3) and a gate connected to the control terminal (4). 3. The repair circuit of claim 2, wherein said third and fourth MOS transistors (Q3, Q4) are p-channel transistors.