KR100238870B1 - Ferro-electric capacitor manufacturing method for keeping steep slope of etching surface - Google Patents

Abstract

A method of manufacturing a ferroelectric capacitor in which steep etch surfaces are maintained. In order to achieve high density of memory cells, a method of manufacturing a ferroelectric capacitor for maintaining a steep etched surface of a capacitor even after completion of a cell fabrication process includes forming a lower electrode layer, a ferroelectric layer, an upper electrode layer, and a masking film on top of the insulating film. After stacking the material, patterning the material of the masking film by a photolithography process to form the masking film, patterning the upper electrode layer and the ferroelectric layer together using the masking film as a mask, and after removing the masking film And forming a protective film in close contact with the sidewalls of the upper electrode layer and the ferroelectric layer by applying an adhesive strengthening and diffusion preventing material on the patterning structure, and etching the entire surface, and patterning the lower electrode layer.

Description

FERRO-ELECTRIC CAPACITOR MANUFACTURING METHOD FOR KEEPING STEEP SLOPE OF ETCHING SURFACE}

TECHNICAL FIELD The present invention relates to the field of manufacturing a semiconductor memory, and more particularly, to a method of manufacturing a ferroelectric capacitor for a ferroelectric semiconductor memory cell.

In general, semiconductor memory manufacturing technology has been developed to increase device performance while minimizing chip size by increasing integration of memory cell devices. As one of the methods for improving the performance of the device, a ferroelectric semiconductor memory device employing a ferroelectric capacitor having nonvolatile properties has been disclosed in the art. Such a memory device employs a ferroelectric capacitor having a ferroelectric material between an upper electrode and a lower electrode instead of a storage capacitor in a conventional DRAM, thereby freeing the problem of disappearance of information due to leakage current as in a DRAM. Therefore, the ferroelectric semiconductor memory device has an advantage of not requiring a refresh operation. In addition, the ferroelectric semiconductor memory device stores information by using polarization inversion and residual polarization characteristics of the ferroelectric material, and thus has an advantage of performing read and write operations at high speed. Since the polarization reversal is caused by the dipole spin in the material, the operating speed of the ferroelectric semiconductor memory device is about 10 ⁴ to 10 ⁵ times that of another nonvolatile semiconductor memory device such as EEPROM or Flash-EEPROM. Fast enough Such operating speeds can be faster in an optimal design and are comparable to those of conventional DRAMs. Moreover, the voltage required for polarization reversal is about 2 to 5 volts, allowing operation at relatively low voltages.

1 shows an equivalent circuit diagram showing a unit cell of a conventional ferroelectric semiconductor memory device. The unit cell typically includes one access transistor TR connected to the bit line B, and a ferroelectric capacitor C connected to one side of the access transistor TR. When the terminal of the access transistor TR connected to the bit line B is a drain D, the terminal of the transistor TR connected to one plate of the ferroelectric capacitor C becomes a source S. The gate G of the transistor TR is connected to the word line W, and the other plate of the ferroelectric capacitor C is connected to the plate line P.

The unit cell of FIG. 1 is typically manufactured on the semiconductor substrate 1 as shown in FIG. 2. FIG. 2 is a vertical cross-sectional view of a unit cell manufactured according to the prior art, in which the access transistor TR is disposed between field oxide films 6 and the ferroelectric capacitor C is disposed generally on top of the field oxide film 6 on the right side of the drawing. Structure. In FIG. 2, the region 5 in contact with the bit line B through the contact hole becomes the drain D of FIG. 1, and the layer 3 surrounded by the first interlayer insulating layer 7 on the gate oxide film 2 It becomes the gate G of FIG. 1, and the area | region 4 becomes the source S. FIG. In the case where the substrate 1 is a P-type semiconductor substrate, n-type impurity ions are implanted into the drain 5 and source regions, so that the transistor TR is an N-type MOS field effect transistor. Becomes A second interlayer insulating layer 13 is usually stacked on the first interlayer insulating layer 7. The ferroelectric capacitor C includes a lower electrode layer 8, a ferroelectric layer 9, and an upper electrode layer 10 that are sequentially stacked on the first interlayer insulating layer 7. The lower electrode layer 8, the ferroelectric layer 9, and the upper electrode layer 10 may be formed of platinum (Pt), fiji (PZT), and platinum or aluminum (Al), respectively. In FIG. 2, the upper electrode layer 10 is connected to the source region 4 through the metal line 12 passing through the contact hole, but the lower electrode layer 8 may be replaced with the position where the upper electrode layer 10 is formed. . In such a case, the lower electrode layer 8 located below becomes the upper electrode layer. A second interlayer insulating layer 13 is stacked on top of the first interlayer insulating layer 7 so as to surround the inclined sidewalls of the layers 8, 9, and 10. In FIG. 2, the lower electrode layer 8 corresponds to the other plate of FIG. 1, and the upper electrode layer 10 corresponds to the one plate.

In FIG. 2, the manufacturing of the access transistor TR is performed by a conventional CMOS transistor manufacturing process. After the access transistor TR is manufactured on the substrate 1, the production of the ferroelectric capacitor C is usually performed. First, the first interlayer insulating film 7 coated on the field oxide film 6 is planarized by a planarization process such as a CMP process. Then, a material for forming the lower electrode layer 8, the ferroelectric layer 9, and the upper electrode layer 10 is sequentially applied on the insulating layer 7, and then the photolithography process is performed using a photoresist as a mask. The layers 8, 9 and 10 are patterned in turn, respectively. Here, it can be seen that the photolithography process for the patterning is all performed three times. When the photolithography process is performed with the photoresist mask, a gentle etching slope appears on the sidewalls of the layers of the ferroelectric capacitor. Although it is preferable that a steep etch slope is obtained, plasma etching using a photoresist mask is attributable to the characteristics of the photoresist, which is a soft mask material, and the chemical resistance of the platinum (Pt) and piji (PZT) materials. Does not achieve steep anisotropic etching. In this case, the upper and lower electrode layers 8 and 10 formed of the platinum material have a gentle sidewall slope than the ferroelectric layer 9 formed of the PV material. The reason for this is that the chemical resistance of platinum is greater than that of Fiji.

3 shows an enlarged sidewall slope for the layers of the ferroelectric capacitor according to FIG. 2. In FIG. 3, the lower length B2 and the thickness of the upper electrode layer 10 made of platinum are 3.08 µm and 2100 µs, respectively, and the lower length B1 and the thickness of the ferroelectric layer 9 on the lower electrode layer 8 having a thickness of 3200 µs are shown. Assuming that the plasma etching is performed sequentially by using a photoresist mask at 3.48 μm and 2800 μs, respectively, the etching slope A2 of the upper electrode layer 10 is about 31 °, and the ferroelectric layer 9 The etching slope A1 is represented by about 58 °. Therefore, as the etching slope is gentler, the capacity of the capacitor is smaller. Therefore, in order to increase the capacity in a limited area, it is understood that it is necessary to have an etching surface of a steep slope. In other words, the etched surface of the steep slope is advantageous for high integration of the memory cell.

As described above, the sidewalls of the layers of the ferroelectric capacitor manufactured by the prior art have a gentle slope, which is disadvantageous in high concentration. In addition, the manufacturing process of the capacitor is also relatively complicated, there is a disadvantage that the manufacturing cost increases. Furthermore, there is a problem that the inherent characteristics of the ferroelectric material may deteriorate when the sidewalls of the material of the ferroelectric layer are protected by the interlayer insulating film 13 made of an oxide film. Such deterioration of characteristics can degrade the reliability of the memory cell.

Accordingly, an object of the present invention is to provide a method of manufacturing a ferroelectric capacitor for a ferroelectric semiconductor memory cell that can solve the above-described conventional problems.

Another object of the present invention is to provide a method capable of producing steep slopes of sidewalls of layers of a ferroelectric capacitor.

Another object of the present invention is to provide a method of manufacturing a ferroelectric semiconductor memory device which can simplify the manufacturing process of a capacitor.

It is still another object of the present invention to provide a method of increasing the reliability of devices by improving the deterioration of characteristics of ferroelectric materials generated in the manufacturing process of ferroelectric memory devices.

1 is an equivalent circuit diagram showing a unit cell of a conventional ferroelectric semiconductor memory device.

2 is a vertical cross-sectional view of a unit cell manufactured according to the prior art.

3 is an enlarged view of the sidewall slope for the layers of the ferroelectric capacitor according to FIG.

4 is a vertical sectional view of ferroelectric memory cells fabricated in accordance with an embodiment of the present invention.

5 through 9 are vertical cross-sectional views showing a process sequence for manufacturing the ferroelectric capacitor of the ferroelectric memory cell in FIG.

According to the present invention for achieving the above object, a method of manufacturing a ferroelectric capacitor, the lower electrode layer, the ferroelectric layer, the upper electrode layer, and the material to form a masking film in sequence on top of the insulating film, and then the photolithography process of the masking film Patterning a material to form the masking film; patterning the upper electrode layer and the ferroelectric layer together using the masking film as a mask; applying a material for preventing adhesion and diffusion on the patterning structure after removing the masking film; Forming a passivation layer on the sidewalls of the upper electrode layer and the ferroelectric layer by etching the entire surface; and patterning the lower electrode layer.

In addition, in the method of manufacturing a memory cell of a ferroelectric semiconductor memory device, an interlayer insulating film is coated on a substrate on which a transistor is manufactured by a CMOS process, and then a contact is made to contact the source region of the transistor through the interlayer insulating film. Forming a; Depositing a material to form a lower electrode layer, a ferroelectric layer, an upper electrode layer, and a masking film on top of the metal line and the interlayer insulating film, and then forming a masking film by patterning a material of the masking film by a photolithography process; Simultaneously patterning the upper electrode layer and the ferroelectric layer together using a masking film as a mask; Removing the masking film and applying a material for preventing adhesion and diffusion to the patterning structure and spacer etching to form a protective film in close contact with sidewalls of the upper electrode layer and the ferroelectric layer; And after patterning the lower electrode layer, forming an metal line as a plate line connected to the upper electrode layer by applying an oxide film as a whole and contacting the upper electrode layer.

Hereinafter, a method of manufacturing a ferroelectric semiconductor memory device according to a preferred embodiment of the present invention will be described with the accompanying drawings. The same layers as each other in the accompanying drawings are labeled with the same or similar reference numerals for ease of understanding. In the following description, specific details are set forth by way of example and in detail in order to provide a more thorough understanding of the present invention. However, for those skilled in the art, the present invention may be practiced only by the above description without these details. In addition, the characteristics and physical operations of manufacturing processes so well known in the art are not described in detail in order not to obscure the subject matter of the present invention.

In the following description, a preferred embodiment of the present invention will be described by way of example only and with reference to the accompanying drawings.

4 is a vertical cross-sectional view of ferroelectric memory cells fabricated in accordance with an embodiment of the present invention. First, referring to FIG. 4, it can be seen that two transistors and two capacitors are formed between the field oxide films 6 formed on the substrate 1. Thus, Figure 4 shows two memory cell structures together. Here, the two transistors share the drain region 5 in contact with the bit line 30, and each of the source regions 4 respectively corresponds to the lower electrode 8 of the corresponding capacitor through the metal line 12. Note that each is connected. Similar to FIG. 2, in FIG. 4, the common region 5, which is in contact with the bit line 30 and the contact hole 30a, becomes the drain D of FIG. 1, and the first interlayer insulating layer is formed on the gate oxide layer 2. The layer 3 surrounded by (7) becomes the gate G of FIG. 1, and the region 4 becomes the source S of each transistor. When the substrate 1 is a P-type semiconductor substrate, n-type impurity ions are implanted into the drain 5 and source regions, so that the transistors are all N-type field effect transistors. Becomes A second interlayer insulating layer 13 is usually stacked on the first interlayer insulating layer 7. The ferroelectric capacitors include a lower electrode layer 8, a ferroelectric layer 9, and an upper electrode layer 10 that are sequentially stacked on the second interlayer insulating layer 13. The layers 8, 9, and 10 may in turn be made of platinum (Pt), fiji (PZT), and platinum or aluminum (Al), respectively. Unlike the structure of FIG. 2, the upper electrode layer 10 in FIG. 4 is connected to the metal line 17 passing through the contact hole 16, and the lower electrode layer 8 passes through the contact hole 20. It is connected to the metal line (12). Here, the metal line 17 is a plate electrode. A third interlayer insulating film 40 made of an oxide film or the like is stacked on the second interlayer insulating film 13 in a form surrounding the capacitors.

4, the lower electrode layer 8, the ferroelectric layer 9 and the upper electrode layer 10 of the ferroelectric capacitors all have a steep etch surface. This is the core idea of the present invention. In addition, a spacer-type protective film that is in close contact with the steep inclined sidewalls of the upper electrode layer 10 and the ferroelectric layer 9 of the capacitor and is not in contact with the bottom of the ferroelectric layer 9 among the upper parts of the lower electrode layer 8. Note (11). The protective film 11 formed after patterning the upper electrode layer 10 and the ferroelectric layer 9 with an oxide mask is used for strengthening adhesion of the capacitor layers and preventing diffusion and degradation of the ferroelectric material.

Next, with reference to FIGS. 5 to 9, a method of manufacturing a ferroelectric capacitor having an example structure as shown in FIG. 4 will be described in detail. 5 through 9 are vertical cross-sectional views sequentially illustrating a process sequence of manufacturing a ferroelectric capacitor of a ferroelectric memory cell in FIG. 4. For convenience of illustration, only one capacitor is fabricated on the second interlayer insulating film 13 on which the contact plug 12 (metal line) is formed. However, the present invention is not limited thereto, and it is found that a capacitor can be selectively formed on the field oxide film 6 or on the device active region, and can be formed directly on the first interlayer insulating film 7. Put it.

Referring to FIG. 5, the second interlayer insulating layer 13 is formed of reflow glass. The contact plug 12 is formed on the insulating layer 13. The plug 12 is located in the contact 20 of FIG. 4, which is present for electrical connection between the upper portion of the source region 4 of FIG. 4 and the lower electrode layer 8 to be formed on the insulating layer 13. do. The lower electrode layer 8, the ferroelectric layer 9, the upper electrode layer 10, and the material layer 15 to form a masking film are sequentially stacked on the second interlayer insulating layer 13. In this case, the material layer 15 may be formed of, for example, an oxide film material. In this case, TiO ₂ , PE-SiH 4 Oxide, or O ₃ -TEOS may be formed by low temperature sputtering to be deposited on the upper electrode layer 10. can do. The oxide film can also be deposited by the plasma method. In the present embodiment, the lower electrode layer 8 and the upper electrode layer 10 are 3200 Å and 2100 Å thick Pt layers, respectively, and the ferroelectric layer 9 is 2800 Å thick crystallized in an oxygen atmosphere for about 30 minutes. PZT.

Referring to FIG. 6, the material layer 15 is patterned to a set width. The patterning is accomplished by applying a photoresist on the material layer 15 and by a conventional plasma method. When the photoresist is removed, only the patterned oxide film 15 is present on the upper electrode layer 10 as shown in FIG. 6. The oxide film 15 as the material layer is used as a hard mask to obtain an etching surface of steep slope. When the upper electrode layer 10 and the ferroelectric layer 9 are etched together using the oxide film 15 as a mask, and then the oxide film 15 is removed, a structure as shown in FIG. 7 is obtained. As such, when the layers 10 and 9 are simultaneously etched using a hard mask, sidewalls of steep slope are obtained more than the etching of the conventional method using a photoresist as a soft film. In addition, the two layers are patterned by one etching process to simplify the manufacturing process.

FIG. 8 shows a structure in which an adhesion strengthening and diffusion preventing material such as TiO 2 layer 11a is deposited on the layer structure of FIG. 7. The layer 11a may be deposited by sputtering. The layer 11a is used to enhance adhesion of the ferroelectric capacitor layers and to prevent diffusion and deterioration of the ferroelectric material. That is, the titanium oxide (TiO 2) layer 11a functions as a capping layer to prevent PbO volatilization in the ferroelectric layer 9, and the material component of the third interlayer insulating film 40 to be deposited in a subsequent process is a ferroelectric layer. (9) prevents infiltration and keeps the side walls of steep slopes intact.

Fig. 9 shows the structure of the result of performing the entire etch back using the film 11a of Fig. 8 as a mask. The protective film 11 in the form of a spacer is in close contact with the steep inclined sidewalls of the upper electrode layer 10 and the ferroelectric layer 9 of the capacitor and is not in contact with the lower portion of the ferroelectric layer 9 in the upper portion of the lower electrode 8. It can be seen that it is in close contact.

In the subsequent process, a SiO2 layer having a thickness of about 4500 kPa is formed as the interlayer insulating film 40 of FIG. 4, and the metal line 17 passing through the contact hole 16 of FIG. 4 is performed. Accordingly, the upper electrode layer 10 is in electrical contact with the plate electrode.

According to the present invention as described above, since the sidewalls of the layers of the ferroelectric capacitor are manufactured at a steep slope, there is a more advantageous effect on high integration. In addition, since the manufacturing process of the capacitor can be simplified, the manufacturing cost is reduced, and the deterioration of characteristics of the ferroelectric material generated in the manufacturing process can be improved, thereby increasing the reliability of the device.

Although the above-described invention has been described and limited by way of example with reference to the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention.

Claims (7)

A method of manufacturing a ferroelectric capacitor for a ferroelectric semiconductor memory cell; After patterning the upper electrode layer and the ferroelectric layer of the capacitor with an oxide mask, a protective film that is in close contact with the steep inclined sidewalls of the upper electrode layer and the ferroelectric layer of the capacitor and not in contact with the lower portion of the ferroelectric layer of the lower electrode. Forming a method comprising the step of forming. The method of claim 1, wherein the protective film is a titanium oxide film. Forming a lower layer, a ferroelectric layer, an upper electrode layer, and a material layer to form a masking layer on top of the insulating layer, and then patterning the material layers by a photolithography process to form a masking layer; Simultaneously patterning the upper electrode layer and the ferroelectric layer together using the masking film as a mask; Removing the masking layer, applying a material for strengthening adhesion and diffusion prevention on the patterned upper electrode layer and the ferroelectric layer, and etching the entire surface to form a passivation layer in close contact with the sidewalls of the upper electrode layer and the ferroelectric layer; And Patterning the lower electrode layer, characterized in that it comprises a ferroelectric capacitor manufacturing method. The method of claim 3, wherein the protective film is a titanium oxide film. The method of claim 3, wherein the insulating film is an oxide film. The method of claim 3, wherein the masking film is an oxide film. In a method of manufacturing a memory cell of a ferroelectric semiconductor memory device: Manufacturing a transistor using a CMOS process, applying an interlayer insulating film over the substrate, and forming a contact with the source region of the transistor through the interlayer insulating film to form a metal line; Forming a lower electrode layer, a ferroelectric layer, an upper electrode layer, and a material layer to be a masking layer in order on the metal line and the interlayer insulating layer, and then patterning the material layers by a photolithography process to form a masking layer; Simultaneously patterning the upper electrode layer and the ferroelectric layer together using the masking film as a mask; Removing the masking layer and applying a material for preventing adhesion and diffusion to the patterning structure and spacer etching to form a protective film in close contact with the sidewalls of the upper electrode layer and the ferroelectric layer; And After patterning the lower electrode layer, forming a metal line as a plate line connected to the upper electrode layer by applying an oxide film as a whole and contacting the upper electrode layer.

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