KR100190362B1 - Forming method of self aligned contact - Google Patents
Forming method of self aligned contact Download PDFInfo
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- KR100190362B1 KR100190362B1 KR1019950005973A KR19950005973A KR100190362B1 KR 100190362 B1 KR100190362 B1 KR 100190362B1 KR 1019950005973 A KR1019950005973 A KR 1019950005973A KR 19950005973 A KR19950005973 A KR 19950005973A KR 100190362 B1 KR100190362 B1 KR 100190362B1
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000010410 layer Substances 0.000 claims abstract description 72
- 125000006850 spacer group Chemical group 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 19
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- 239000011229 interlayer Substances 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 230000000694 effects Effects 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 8
- 238000009413 insulation Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 하부 소자와 이후 형성될 층과의 절연을 위하여 전체구조 상부에 층간절연층(12)을 형성하는 단계를 포함하는 반도체 소자 제조시 자기정렬 콘택(Self-aligned contact)방법에 있어서, 상기 층간 절연층(12) 표면에 소정 장벽층(13)을 형성한 후, 전체구조 상부에 평탄화층(14)을 형성하는 단계, 상기 평탄화층(14)의 예정된 부위를 제거한 후, 제거된 평탄화층(14)의 측벽에 제1스페이서(15)를 형성하는 단계, 및 전체구조 상부에 제2스페이서(17) 형성을 위한 절연층(16) 형성 후, 에치백 공정을 수행하는 단계를 포함하는 것을 특징으로 하며, 스페이서 형성을 위한 에치백 공정시의 식각정도가 하부 소자에 미치는 영향을 최소화할 수 있으며, 동시에 콘택저하값을 감소시킬 수 있고, 이에 따라 디자인 룰(Design rule)을 감소시켜 제조수율을 향상시킬 수 있는 자기정렬 콘택홀 형성방법에 관한 것이다.The present invention provides a method of self-aligned contact in manufacturing a semiconductor device, including forming an interlayer insulating layer 12 over an entire structure to insulate an underlying device from a layer to be formed later. After the predetermined barrier layer 13 is formed on the surface of the interlayer insulating layer 12, the planarization layer 14 is formed on the entire structure. After the predetermined portion of the planarization layer 14 is removed, the planarization layer is removed. Forming a first spacer 15 on the sidewall of the surface 14 and performing an etch back process after forming the insulating layer 16 for forming the second spacer 17 on the entire structure. It is possible to minimize the effect of the etching degree during the etch back process for forming the spacer on the lower device, and at the same time to reduce the contact drop value, thereby reducing the design rule (manufacturing yield) Who can improve The present invention relates to a method for forming a predetermined contact hole.
Description
제1a도 내지 제1d도는 종래기술에 따른 자기정렬 콘택홀 형성 과정도.1A to 1D are views illustrating a process of forming a self-aligned contact hole according to the prior art.
제2a도 내지 제2d도는 본 발명에 따른 자기정렬 콘택홀 형성 과정도.2a to 2d is a process chart of forming a self-aligned contact hole according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 실리콘 기판 12, 16 : 산화층11 silicon substrate 12, 16 oxide layer
13 : Si3N4층 14 : BPSG(BoroPhospho Silicate Glass)층13 Si3N4 layer 14 BPSG (BoroPhospho Silicate Glass) layer
15, 17 : 스페이서15, 17: spacer
본 발명은 반도체 소자 제조시 자기정렬 콘택(Self-aligned contact)홀 형성방법에 관한 것이다.The present invention relates to a method of forming a self-aligned contact hole in manufacturing a semiconductor device.
제1a도 내지 제1d도는 종래기술에 따른 자기정렬 콘택홀 형성 과정도로서, 이를 참조하여 종래기술을 살펴본다.1A to 1D illustrate a process of forming a self-aligning contact hole according to the prior art, and the prior art will be described with reference thereto.
종래에는 먼저, 제1a도에 도시된 바와 같이 실리콘 기판(1) 상에 MOS(Metal-Oxide-Semiconductor) 트랜지스터를 포함하는 예정된 소자를 형성한 다음, 이후 형성될 층과의 절연을 위하여 전체구조 상부에 층간절연층인 층간산화층(2)을 형성한다. 이어 전체구조 상부에 평탄화층인 BPSG(BoroPhospho Silicate Glass)층(3)을 형성한다.Conventionally, first, a predetermined device including a metal-oxide-semiconductor (MOS) transistor is formed on a silicon substrate 1, as shown in FIG. 1A, and then the upper portion of the entire structure for insulation from a layer to be formed later. An interlayer oxide layer 2 is formed on the interlayer insulating layer. Subsequently, a BPSG (BoroPhospho Silicate Glass) layer 3 is formed on the entire structure.
이어서, 제1b도에 도시된 바와 같이 콘택홀 형성을 위해 전체 중 상부에 감광층(4) 패턴을 형성하고, 이를 이용하여 BPSG층(3)의 노출된 부위를 식각한다.Subsequently, as shown in FIG. 1B, a photosensitive layer 4 pattern is formed on the upper part of the whole to form a contact hole, and the exposed portion of the BPSG layer 3 is etched using the pattern.
계속해서, 제1c도에 도시된 바와 같이 전체구조 상부에 산화층(5)을 형성한 다음, 에치백(Etch-back)고정을 수행함으로써 제1d도에 도시된 바와 같은 스페이서(6)를 형성한다.Subsequently, the oxide layer 5 is formed on the entire structure as shown in FIG. 1c, and then the spacer 6 as shown in FIG. 1d is formed by performing etch-back fixing. .
그러나, 상기와 같은 과정으로 이루어지는 종래기술은 스페이서 형성을 위한 에치백 공정 수행시 하부 MOS 트랜지스터의 게이트 전극의 보호 및 콘택을 위한 전도층과 단락 방지를 위하여 식각정도를 세밀하게 조정해야 하는 불편함이 있었다. 즉, 에치백의 식각정도가 적으면 콘택면적이 감소하게 되고, 이에 따라 콘택저항 값이 증대되고, 반면 에치백의 식각정도가 지나치면 하부 게이트 전극과의 절연성에 문제가 발생한다.However, the prior art made of the above process is inconvenient to finely adjust the etching degree in order to prevent the short-circuit and the conductive layer for the protection and contact of the gate electrode of the lower MOS transistor when performing the etch back process for forming the spacer. there was. In other words, if the etching degree of the etch back is small, the contact area decreases, thereby increasing the contact resistance value. On the other hand, if the etching degree of the etching back is excessive, a problem occurs in the insulation with the lower gate electrode.
따라서, 상기 문제점을 해결하기 위하여 안출된 본 발명은 식각률이 상이한층을 층간절연층과 평탄화층 사이에 형성함으로써, 스페이서 형성을 위한 에치백 공정시의 식각정도가 하부 소자에 미치는 영향을 최소화할 수 있으며, 동시에 콘택홀 저항값을 감소시킬 수 있는 자기정렬 콘태홀 형성방법을 제공하는데 그 목적이 있다.Therefore, the present invention devised to solve the above problems by forming a layer having a different etching rate between the interlayer insulating layer and the planarization layer, it is possible to minimize the effect of the degree of etching on the lower element during the etch back process for forming the spacer. It is also an object of the present invention to provide a method for forming a self-aligning contact hole that can reduce the contact hole resistance.
상기 목적을 달성하기 위하여 본 발명은, 하부 소자와 이후 형성될 층과의 절연을 위하여 전체구조 상부에 형성되는 층간절연층을 포함하는 반도체 소자의 자기정렬 콘택(Self-aligned contact)방법에 있어서, 상기 층간절연층 표면에 식각장벽층을 형성한 후, 전체구조 상부에 평탄화층을 형성하는 단계, 상기 콘택부위에 위치한 평탕화층을 제거하여 상기 장벽층을 노출시키고, 제거된 평탄화층의 측벽에 제1스페이서 형성하는 단계, 노출된 상기 식각장벽층을 제거하는 단계, 및 전체 구조 상부에 절연층 형성 후, 상기 절연층 및 상기 층간절연층을 비등방성 식각하여 상기 절연층 측벽에 제2스페이서를 형성함과 동시에 콘택 개구부를 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention, in the self-aligned contact method of a semiconductor device comprising an interlayer insulating layer formed on the entire structure for the insulation of the lower device and the layer to be formed later, Forming an etch barrier layer on the surface of the interlayer insulating layer, and then forming a planarization layer on the entire structure, exposing the barrier layer by removing the planarization layer located on the contact portion, and After forming the first spacer, removing the exposed etch barrier layer, and forming an insulating layer on the entire structure, anisotropically etching the insulating layer and the interlayer insulating layer to form a second spacer on the sidewall of the insulating layer. And forming a contact opening at the same time as forming.
이하, 첨부된 도면 제2a도 내지 제2d도를 참조하여 본 발명의 일실시예를 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings 2A to 2D.
제2a도 내지 제2d도는 본 발명의 일실시예에 따른 자기정렬 콘택홀 형성 공정도이다.2A through 2D are flowcharts of forming a self-aligned contact hole according to an exemplary embodiment of the present invention.
본 발명은 먼저, 제2a도에 도시된 바와 같이 실리콘 기판(11) 상에 MOS 트랜지스터를 포함하는 예정된 소자를 형성한 다음, 이후 형성될 층과의 절연을 위하여 전체구조 상부에 층간절연층인 층간산화층(12)을 형성한다. 이어서, 식각장벽층으로서, 전체구조 표면에 Si3N4층(13)을 얇게 형성한 다음, 그 상부에 평탄화층인 BPSG층(14)을 형성한다. 여기서, 상기 Si3N4층(13)은 그 식각률이 스페이서(15)(주로 산화층)의 식각률보다 작으며, 스페이서(15)(주로 산화층)보다 식각률이 작은 다른 어떠한 물질도 Si3N4층(13)과 대체 가능하다.The present invention firstly forms a predetermined device including a MOS transistor on a silicon substrate 11 as shown in FIG. 2A, and then an interlayer insulating layer on top of the entire structure for insulation from the next layer to be formed. The oxide layer 12 is formed. Subsequently, as an etch barrier layer, a thin Si 3 N 4 layer 13 is formed on the entire structure surface, and then a BPSG layer 14, which is a planarization layer, is formed thereon. Here, the Si 3 N 4 layer 13 has an etch rate smaller than that of the spacer 15 (mainly an oxide layer), and any other material having an etch rate smaller than that of the spacer 15 (mainly an oxide layer) may be Si 3 N 4 layer. Can be replaced with (13).
이어서, 제2b도에 도시된 바와 같이 콘택홀 형성을 위해 예정된 부위의 BPSG층(14)을 식각을 다음, BPSG층(14)의 측벽에 스페이서(15)를 형성한다. 이때, 즉 상기 스페이서(15) 형성을 위한 에치백 공정시 노출되는 Si3N4츠(13)도 동시에 제거된다. 이때, Si3N4층(13)은 그 식각률이 스페이서(15)의 식각률보다 작기 때문에 스페이서(15) 하부에 돌출된 형상을 가지며 식각된다.Subsequently, as shown in FIG. 2B, the BPSG layer 14 is etched at the predetermined portion for forming the contact hole, and then the spacer 15 is formed on the sidewall of the BPSG layer 14. At this time, the Si 3 N 4 Ts 13 exposed during the etch back process for forming the spacer 15 are also removed at the same time. In this case, since the etching rate of the Si 3 N 4 layer 13 is smaller than the etching rate of the spacer 15, the Si 3 N 4 layer 13 may be etched with a protruding shape under the spacer 15.
계속해서, 제2c도에 도시된 바와 같이 전체구조 상부에 산화층(16)을 형성한 다음, 제2d도에 도시된 바와 같이 에치백 공정을 수행하여 스페이서(17)를 형성한다. 상기 스페이스(17) 형성을 위한 에치백 공정시 돌출된 형상을 갖는 Si3N4층(13) 및 그 주위에 형성된 두꺼운 산화층(16)이 횡방향으로의 식각을 억제하기 때문에 콘택저항을 감소시키기 위한 과도한 에치백 공정에서도 하부 게이트 전극에 미치는 영향을 최소화할 수 있게 된다.Subsequently, as shown in FIG. 2C, the oxide layer 16 is formed on the entire structure, and then the spacer 17 is formed by performing an etch back process as shown in FIG. 2D. Since the Si 3 N 4 layer 13 having the protruding shape and the thick oxide layer 16 formed around the space 17 suppress the etching in the lateral direction during the etch back process for forming the space 17, the contact resistance is reduced. In the case of excessive etch back process, the influence on the lower gate electrode can be minimized.
상기와 같이 이루어지는 본 발명은 스페이서 형성을 위한 에치백 공정시의 식각정도가 하부 소자에 미치는 영향을 최소화할 수 있으며, 동시에 콘택저항 값을 감소시킬 수 있고, 이에 따라 디자인 룰(Design rule)을 감소시켜 제조수율을 향상시킬 수 있는 특유의 효과가 있다.The present invention as described above can minimize the effect of the etching degree on the lower element during the etch back process for forming the spacer, and at the same time can reduce the contact resistance value, thereby reducing the design rule (Design rule) There is a distinctive effect that can be improved to improve the production yield.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950005973A KR100190362B1 (en) | 1995-03-21 | 1995-03-21 | Forming method of self aligned contact |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950005973A KR100190362B1 (en) | 1995-03-21 | 1995-03-21 | Forming method of self aligned contact |
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| Publication Number | Publication Date |
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| KR100190362B1 true KR100190362B1 (en) | 1999-06-01 |
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| KR1019950005973A Expired - Fee Related KR100190362B1 (en) | 1995-03-21 | 1995-03-21 | Forming method of self aligned contact |
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- 1995-03-21 KR KR1019950005973A patent/KR100190362B1/en not_active Expired - Fee Related
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