KR100186318B1 - First-in, first-out device for general purpose I / O interface - Google Patents

Abstract

The present invention relates to a first-in-first-out (FIFO) device of a general-purpose input / output (I / O) interface, wherein a synchronous dynamic RAM (SDRAM) of a conventional device is initially given a row address and a column address, and thus the first data. It takes a similar time to read a general dynamic RAM (DRAM), but the next data can be read every clock as long as it is in the same page, but I / O using first-in-first-out (FIFO) In the interface, if a first-in, first-out word is empty, data is unconditionally requested in memory. In most cases, data is received from the memory as soon as requested, so data transfer from the memory to first-in-first-out is 1 It is a word transfer, and accesses a new page every time even using a conventional input / output interface, so there is no effect of using the synchronous dynamic RAM. As a result, the present invention improves the conventional I / O interface first-in, first-out structure, and the page size of the synchronous dynamic RAM is 1K words in general, and if the consecutive data is smaller than 1K words, it is more likely to be in the same page. When multiple words are read or written at the same time in one request, the second data can be read and written every clock, thereby increasing the efficiency of the synchronous dynamic RAM.

Description

First-in-first-out (FIFO) device of general-purpose input / output (I / O) interface

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a first-in first-out (FIFO) device of a general-purpose input / output (I / O) interface. In particular, when the synchronous dynamic RAM (SDRAM) is used as main memory in a computer system, the synchronization is performed. The present invention relates to a first-in first-out (FIFO) device of a general-purpose input / output (I / O) interface for increasing the efficiency of a dynamic RAM.

1 is a block diagram of a conventional microprocessor system, which includes a microprocessor (μ-processor) 10 which actually executes micro instructions as shown therein; A memory 11 capable of retrieving the entirety from the given data, the data about it, or a portion of the data, preserving the given information at a certain time as its corresponding physical state, and restoring the information later when needed; When performing data transfer in a direct storage approach, a direct storage device that forms a transmission circuit (channel) independent of the central processing unit so that data exchange can be performed directly to the memory 11 and the external period. A direct memory access controller (DMA controller) 12; Under the control of the direct storage device access controller 12, it is composed of an input / output (I / O) interface 13 of a peripheral device for exchanging data with the memory 11 or exchanging data with the microprocessor 10, An operation process of the conventional apparatus configured as described above will be described.

FIG. 2 is a first-in-first-out (FIFO) block diagram of an input / output (I / O) interface of a conventional peripheral device, and as shown therein, a write control logic unit 20 for generating a write pointer; A read control logic section 21 for generating a read pointer; A dual-port random access memory (Dual Port RAM) 22 which selects either one by a control signal specifying whether the inlet of the write data and the outlet of the read data are shared, and whether to record or read; And a comparator 23 for comparing the write pointer with the read pointer and outputting a full signal or an empty signal in the same case. FIG. 3 shows an input / output (I / O) interface block of a conventional peripheral device. As shown in the figure, First In First Out (FIFO) 30 is a full signal indicating that the first in First Out (FIFO) 30 is full as a control signal, and the first in first out. If the FIFO 30 has an empty signal indicating that it is empty and sequential data is output to the outside, the first-in first-out (FIFO) is empty in the memory 11 if the current state is not full. (EMPTY) sends a request for data to retrieve data from the memory 11, the normal speed of the host interface is significantly faster than the speed of the external interface, so the first Elected (FIFO, 30) to be filled soon To send a full signal to the memory 11 and no longer require data, and the data at the bottom of the first-in first-out (FIFO) 30 is externally connected via a parallel input serial output (PISO) interface 31. The output signal of the first-in-first-out (FIFO) 30 is deactivated again to request additional data from the memory 11, and the process is performed in the memory 11. Repeat until you have output all the data.

When reading the sequential data and storing it in the memory 11, the serial input parallel output (SIPO) interface 32 reads the sequential data from the outside and stores the sequential data in the first-in first-out 30 orderly. ) Generates a full signal and requests data to be read out when there is a difference, in which case the requested memory 11 reads a word and the first-in-first-out 30 is empty. Continue reading until it is present.

If a first-in-first-out (FIFO) 30 is used, data is requested from the memory 11, but the first-in-first-out (FIF) may not be provided in time (for example, a multitasking system). Since FIFO, 30) plays a buffer role, the data output to the outside is normally output.

As described above, in the conventional apparatus, when the synchronous dynamic RAM (SDRAM) is used as a memory, it is similar to the general dynamic RAM (DRAM) until the first data is read by giving a row address and a column address. Although it takes time, the next data can be read every clock as long as it is in the same page, but the first-in-first-out (FIFO) is 1 in the input / output (I / O) interface using the first-in-first-out (FIFO). If a word is empty, data is unconditionally required in memory. In most cases, data is received from the memory immediately upon request, so data transfer from the memory to first-in-first-out (FIFO) is one word. The synchronous dynamic RAM (SDRAM) is used because it is a transmission and there is a high possibility of accessing a new page every time even if the conventional input / output (I / O) interface is used. There is a problem you can not see the effect.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and improves the FIFO structure of the conventional input / output (I / O) interface to improve the efficiency of the synchronous dynamic RAM (SDRAM). The purpose is to provide.

1 is a block diagram of a conventional microprocessor system

2 is a first-in-first-out (FIFO) block configuration diagram of an input / output (I / O) interface of a conventional peripheral device.

3 is a block diagram of an input / output (I / O) interface of a conventional peripheral device

4 is a first-in-first-out (FIFO) block diagram of the present invention general-purpose input / output (I / O) interface.

5 is a block diagram of a general-purpose input / output (I / O) interface device using the present invention

* Explanation of symbols for main parts of the drawings

10: microprocessor 11: memory

12: direct storage device access controller 13, 50: input and output interface

20: recording control logic 21: fundog control logic

22: dual port RAM 23,41: comparator

30, 51: First-in-first-out (FIFO) 31: Parallel input serial output interface

32: serial input parallel output interface 40: offset generator

4 is a block diagram of a first-in, first-out (FIFO) device of the general-purpose input / output (I / O) interface of the present invention. As shown in FIG. 4, a write pointer is generated. A recording control logic section 20; A read control logic section 21 for generating a read pointer; Dual port random access memory (Dual Port), which selects either one by a control signal that specifies whether the inlet of the write data and the outlet of the read data are shared and to write or read. An offset output unit 40 for outputting an offset value to a conventional first-in first-out (FIFO) device which is a RAM (22); The comparator 41 outputs a half-full signal in the same case by comparing the write pointer and the read pointer with reference to the offset value, which will be described in detail with reference to the accompanying drawings.

Fig. 5 is a block diagram of a general-purpose input / output (I / O) interface device using the present invention. As shown in the figure, when sequential data is output to the outside when the first-in first-out (FIFO) 50 is ½ empty, That is, if the depth is 16 words, when 8 words remain in the first-in, first-out 50, new data is requested from the memory 11, where the first-in-first-out 50 is one. Instead of receiving only the word of word from the memory 11, the word 8 of the data for refilling the first-in, first-out 50 is received from the memory 11 at once, and the first-in, first-out 50 is Once again, the first-in, first-out 50 does not require data from the memory 11 until eight words remain in the first-in, first-out 50.

When reading sequential data and storing it in the memory 11, the serial input parallel output (SIPO) interface 32 reads sequential data from the outside and stores the sequential data in the first-in, first-out order 50, and the first-in-first-out 50 In the case where half is full, a half-full signal is generated to request data to be read. At this time, the requested memory 11 reads eight words at once instead of one word. The first-in, first-out 50 is emptied again, generating a read request when half full.

As described above, the first-in-first-out (FIFO) device of the general-purpose input / output (I / O) interface of the present invention reads and writes one word of data each time a request is made, and then the synchronous dynamic Although the difference between the RAM and the dynamic RAM is not much, the page size of the synchronous dynamic RAM is 1K words, and the continuous data is smaller than 1K words. If you read or write several words at once in one request, you can read and write every second clock from the second data. The efficiency of the synchronous dynamic RAM (SDRAM) is increased.

Claims (1)

A write control logic section for generating a write pointer; A read control logic for generating a read pointer; Dual port random access memory (Dual Port), which selects either one by a control signal that specifies whether the inlet of the write data and the outlet of the read data are shared and to write or read. An offset output unit for outputting an offset value to a conventional first-in first-out (FIFO) device composed of a RAM; The first input of the universal input / output (I / O) interface comprising a comparator configured to compare the write pointer and the read pointer with reference to the offset value, and output a half-full signal in the same case. FIFO device.