491970 A7 B7 五、發明說明（\) 發明領域 (請先閱讀背面之注意事項再填寫本頁) 本發明係關於一電腦系統的記憶體存取，更具體而 言，係關於一於電腦系統中用以增進記憶體存取操作性能 的記憶頁收集器。 發明背景 電腦系統依靠記憶體系統以儲存處理器所處理的指示 以及資料，記憶體裝置的儲存容量以及速度二者都有驚人 的進展。然而，記憶體裝置的速度尙未能夠跟上現行微處 理器速度增加的腳步，結果導致最先進電腦系統的速度受 限於資料以及指示從記憶體裝置存取的速度。 於一典型的電腦系統中，處理器經由處理器匯流排以 及記憶體控制器與記憶體溝通，典型的記憶體系統包括單 列式記憶體模組（single in-line memory module，SIMM) 以及雙列式記憶體模組（dual in-line memory module， DIMM)。記憶體模組典型包括一或多庫（bank)並行連 接的記憶體晶片，並於記憶庫（memory bank)的一個記 憶體位址儲存一個字元組資料。 經濟部智慧財產局員工消費合作社印製 典型記憶體模組中存取延遲的理由之一，是每一個記 憶體晶片包括一或多個資料線，處理資料寫入至記憶體晶 片以及從記憶體晶片讀取資料。同樣地，相對應的記憶體 控制器包括一資料匯流排，處理從每一個記憶體晶片的資 料寫入以及讀取，或者，記憶體晶片的資料匯流排可以直 4SIS/200001TW, 89pl0 1 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 491970 A7 B7 五、發明說明 接連接到處理器資料匯流排的一部份。因此，每一次記憶 體切換的存取，無論從讀取操作切換至寫入操作，或者從 寫入操作切換至讀取操作，資料係以相反方向從資料匯流 排傳輸。等待記憶體匯流排完成、以及可能相對應於前一 次存取的記憶體控制器匯流排所需要的時間，一般稱作匯 流排反轉時間（bus turn-around time)，通常延遲至少一 個工作時脈週期（clock cycle)。 於一典型動態隨機存取記憶體（DRAM)之記憶體系 統中，每一個記憶體晶片包含一陣列的記憶體儲存格 (memory cell)，藉由水平線（列）以及垂直線（行）而 互相連接。每一個記憶體儲存格儲存單一個位元，並且藉 由記憶體位址而存取，記憶體位址包含索引記億體陣列之 一列的列位址、以及索引記憶體陣列之一行的行位址。因 此，每一個記憶體位址指向由列位址所指定的列與由行位 址所指定的行，所交接處的記憶體儲存格。491970 A7 B7 V. Description of the invention (\) Field of invention (please read the notes on the back before filling out this page) The present invention relates to the memory access of a computer system, more specifically, it relates to a computer system Memory page collector to improve the performance of memory access operations. BACKGROUND OF THE INVENTION Computer systems rely on memory systems to store instructions and data processed by processors, as well as amazing advances in both the storage capacity and speed of memory devices. However, the speed of memory devices has not been able to keep pace with the increase in current microprocessor speeds. As a result, the speed of state-of-the-art computer systems is limited to the speed of data and instructions for accessing from memory devices. In a typical computer system, the processor communicates with the memory via a processor bus and a memory controller. A typical memory system includes a single in-line memory module (SIMM) and a dual-rank memory module. Dual in-line memory module (DIMM). A memory module typically includes one or more banks of memory chips connected in parallel, and stores one byte of data at a memory address of the memory bank. One of the reasons for the access delays in the printing of typical memory modules by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs is that each memory chip includes one or more data lines that process data written to and from the memory chip. Chip read data. Similarly, the corresponding memory controller includes a data bus that handles the writing and reading of data from each memory chip, or the data bus of the memory chip can be directly 4SIS / 200001TW, 89pl0 1 paper Standards are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm). Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 491970 A7 B7. 5. Description of the invention A part of the data bus connected to the processor. Therefore, every time a memory switch accesses, whether it is from a read operation to a write operation, or from a write operation to a read operation, data is transferred from the data bus in the opposite direction. The time required to wait for the memory bus to complete and the memory controller bus that may correspond to the previous access, is commonly referred to as the bus turn-around time, and is usually delayed by at least one operation Clock cycle. In a typical dynamic random access memory (DRAM) memory system, each memory chip includes an array of memory cells, which are interconnected by horizontal lines (columns) and vertical lines (rows). connection. Each memory cell stores a single bit and is accessed by a memory address. The memory address includes a row address of a row of the index memory array and a row address of a row of the index memory array. Therefore, each memory address points to the memory cell where the row specified by the column address and the row specified by the row address meet.
爲了要限制大小，每一個記憶體晶片通常只包括足夠 的位址接腳（pin)，以於不同的時間，也就是並非同時， 指定列位址以及行位址。因此，典型的記憶體控制器是先 傳輸列位址，然後傳輸行位址，以依序存取一記憶體位置。 更特定而言，記憶體位址控制器將列位址放置到記憶體定 址匯流排上、觸發一列位址選擇（row address select， RAS)信號、然後將行位址放置到記憶體定址匯流排上、 以及觸發一行位址選擇（column address select, CAS)信 號。爲了確保適當的時間安排，記憶體控制器於觸發RAS 4SIS/200001TW, 89pl0 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------------^訂---------線 (請先閱讀背面之注意事項再填寫本頁) β 經濟部智慧財產局員工消費合作社印製 叼 1970 A7 -------- 五、發明說明（3) 與觸發CAS之間延遲一短暫時間，也就是RAS/CAS延遲 (RAS/CAS delay )。 一種被稱爲記憶頁模式（page mode)的技術被發展 出來，以消除連續存取相同記憶體列時的RAS/CAS延遲。 因爲大多數的程式執行本質上是連續的，程式執行常常沿 著記憶體的一列而進行。當在記憶頁模式中時，記憶體控 制器中的列比較器將現行存取中之記憶體位置的列位址， 與下一次記憶體存取的列位址做比較，如果列位址相同， 稱爲記憶頁命中（page hit)，則列比較器使得記憶體控制 器繼續在現行匯流排週期的結束處觸發RAS信號。由於 被存取的記憶體是由正確的列位址所導引，新的行位址立 即轉移到記憶體，而不會有RAS/CAS延遲。 另一種記憶體延遲，稱爲預充電延遲（pre-charge delay)，通常發生在每一次記憶體讀取運作之後。一動態 隨機存取記憶體位置的記憶體讀取，是將記憶體儲存格部 分充電或放電、然後將記憶體儲存格完全再次充電或放 電。預充電延遲指的是完成這些充電以及放電週期所需要 的時間。 # 預充電延遲的次數可以藉由將一記憶系統分開成爲二 個記憶庫、以及將連續的記憶體位置交錯（interleave) 安排於這二記憶庫中而降低。交錯意指將連續的資料字元 組儲存於交替的記憶庫中，例如，將所有複數位址的資料 字元組儲存於第一記憶庫，以及將所有單數位址的資料字 元組儲存於第二記憶庫。當使用一交錯的記憶體結構 4SIS/200001TW, 89pl0 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 外 1970 A7 ---------------- 五、發明說明（1) (intedeaved memory architecture)來連貫讀取被連貫定 址之資料字元組時，第二資料字元組可以在當第一記憶庫 於第一資料字元組從第一記憶庫讀取之後預充電時，從第 二記憶庫顏出來。難，預充賴遲酶—次—資料字 元組從不同於前一次資料字元組所存取之記憶庫的記憶庫 讀取時被隱藏起來，其中該記憶庫是不同於前一次資料字 元組所存取的記憶庫。 雖然上述討論的先前技術降低於記億體中存取資料的 延遲，然而延遲依然經常發生。特別是’從讀取切換至寫 入時仍然會發生讀取/寫入切換延遲，反之亦然。RAS/CAS 延遲於存取之記憶列改變時也會發生’而且於連貫讀取至 相同的記憶庫時也依然會發生預充電延遲。當一或多個記 憶體要求同時從一^繪圖控制器以及系統處理窃：提父日己隱體 要求時，情況會更加惡化。先前技術記憶體控制器只是利 用一種輪流的優先權方法，其中能夠提交記憶體要求的記 憶體存取要求器於每一個記憶體要求之後切換，這樣的輪 流的優先權方法降低收取連貫讀取或寫入要求至相周記億 列的機會，但是增加讀取/寫入切換的數目以及連貫要求 至相同記憶庫的數目，因此增加於一些情況下的記憶體存 取延遲。 習知記憶體系統包括圖1所例示的動態隨機存取記憶 體π，經過記憶體控制器I5藉由處理器13所存取。處 理器Π透過第一匯流排I2發出要求至記憶體控制器15， 而這些記憶體要求若非讀取要求即是寫入要求。記憶體控 4SIS/200001TW, 89ρ10 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------------------訂---------線赢 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 491970 A7 B7 五、發明說明) 制器15透過第一匯流排14連接至動態隨機存取記憶體 11 〇 發明槪述 本發明的記憶頁收集器暫時保留寫入要求並且轉送讀 取要求’使得g買取要求預先發出以增進系統性能。 記憶頁收集器置於記憶體控制器以及處理單元之間。 記憶頁收集器接收一連串的記憶體要求，並且能夠保留寫 入要求。每一個寫入要求包括一具有記憶頁指示資訊的位 址。記憶頁收集器包括一用以重新編排寫入要求順序的控 制器，將具有相同記憶頁的寫入要求分組歸類在一起。換 句話說’具有符合之列部分的寫入要求被保留且分組歸類 在一起。所產生重新編排過的寫入要求接著被提供至記憶 體控制器。藉由將具有相同記憶頁的寫入要求分組歸類在 一起，可以減少記憶體存取時記憶頁錯失的不利結果。 記憶頁收集器具有三個特徵以增進記憶體存取的性 能。第一是其暫時保留寫入要求並且立即通過讀取要求， 其准許處理器單元更早讀取回資料。第二是其將寫入要求 分組歸類至相同的記憶頁，然後當符合一預設的標準時將 它們依序傳送。第三是其保持資料的連貫性，使其提供如 同快取一般的功能以降低記憶體儲存格存取的數目。 圖式簡單說明 圖1係一簡化的方塊圖，說明與記憶體控制器一起的 4SIS/200001TW, 89pl0 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------------------t--------- (請先閱讀背面之注意事項再填寫本頁) ^197〇In order to limit the size, each memory chip usually only includes enough address pins to specify the column address and the row address at different times, that is, not simultaneously. Therefore, a typical memory controller first transmits a column address and then a row address to sequentially access a memory location. More specifically, the memory address controller places the row address on the memory addressing bus, triggers a row address select (RAS) signal, and then places the row address on the memory addressing bus. , And trigger a row address select (CAS) signal. In order to ensure proper timing, the memory controller triggers RAS 4SIS / 200001TW, 89pl0 2 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ----------- ------- ^ Order --------- line (please read the notes on the back before filling out this page) β Printed by the Consumer Consumption Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 叼 1970 A7 ---- ---- 5. Description of the invention (3) There is a short time delay between the triggering of CAS and the RAS / CAS delay. A technique called page mode was developed to eliminate RAS / CAS delays when continuously accessing the same memory bank. Because most program execution is continuous in nature, program execution often follows a line of memory. When in memory page mode, the row comparator in the memory controller compares the row address of the memory location in the current access with the row address of the next memory access. If the row addresses are the same Called page hit, the column comparator causes the memory controller to continue to trigger the RAS signal at the end of the current bus cycle. Since the accessed memory is guided by the correct row address, the new row address is immediately transferred to the memory without RAS / CAS latency. Another type of memory delay, called a pre-charge delay, usually occurs after each memory read operation. A dynamic RAM reads the memory location by charging or discharging a portion of the memory cell, and then fully recharging or discharging the memory cell. The precharge delay is the time required to complete these charge and discharge cycles. # The number of pre-charge delays can be reduced by dividing a memory system into two banks and arranging consecutive memory locations interleaved in the two banks. Interleaved means that consecutive data bytes are stored in alternate memories, for example, all data bytes of plural addresses are stored in the first memory, and all data bytes of singular addresses are stored in Second memory bank. When using an interleaved memory structure 4SIS / 200001TW, 89pl0 3 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ----------------- --- Order --------- line (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1970 A7 ---------- ------ V. Description of the invention (1) (intedeaved memory architecture) When reading data bytes that are consecutively addressed, the second data word group can be used as the first memory word in the first data word. When the tuple is precharged after reading from the first memory bank, it comes out from the second memory bank. It is difficult to pre-charge the late-enzyme-time-data character group when it is read from a memory bank different from the memory bank accessed by the previous data character bank, which is different from the previous data word The memory accessed by the tuple. Although the previous techniques discussed above reduce the latency of accessing data in the memory, latency often occurs. In particular, a read / write switch delay still occurs when switching from read to write, and vice versa. RAS / CAS delays also occur when the access memory bank changes' and pre-charge delays can still occur when consecutively reading to the same memory bank. The situation is exacerbated when one or more memories request simultaneous handling of theft from the graphics controller and the system: the request of the Father ’s Day hidden body. The prior art memory controller only uses a rotating priority method, in which a memory access requester that can submit a memory request switches after each memory request. Such a rotating priority method reduces the charge for consecutive reading or The write request has the opportunity to record hundreds of millions of columns, but the number of read / write switches and the number of consecutive requests to the same memory bank are increased, thus increasing the memory access latency in some cases. The conventional memory system includes the dynamic random access memory π illustrated in FIG. 1 and is accessed by the processor 13 through the memory controller I5. The processor UI sends requests to the memory controller 15 through the first bus I2, and these memory requests are write requests unless they are read. Memory control 4SIS / 200001TW, 89ρ10 4 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) --------------------- Order --------- Line Win (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 491970 A7 B7 V. Description of the invention) Controller 15 passes through the first bus 14 is connected to the dynamic random access memory 11. The invention describes that the memory page collector of the present invention temporarily retains the write request and forwards the read request, so that the purchase request is issued in advance to improve system performance. The memory page collector is placed between the memory controller and the processing unit. The memory page collector receives a series of memory requests and is able to retain write requests. Each write request includes an address with memory page designation information. The memory page collector includes a controller for rearranging the order of write requests, grouping together write requests having the same memory page. In other words, 'Write requirements with a compliant portion are preserved and grouped together. The resulting reprogrammed write request is then provided to the memory controller. By grouping write requests with the same memory page together, the adverse effects of memory page misses during memory access can be reduced. The memory page collector has three features to improve memory access performance. The first is that it temporarily holds the write request and passes the read request immediately, which allows the processor unit to read back the data earlier. The second is to group the write requests into the same memory page, and then transfer them sequentially when a preset standard is met. The third is that it maintains the coherence of the data, so that it provides the same functions as caching to reduce the number of memory cell accesses. Brief description of the drawing Figure 1 is a simplified block diagram illustrating the 4SIS / 200001TW, 89pl0 together with the memory controller. 5 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ---- ----------------- t --------- (Please read the notes on the back before filling this page) ^ 197〇
經濟部智慧財產局員工消費合作社印製 五、發明說明（G) 一習知記憶體系統。 圖2說明一記憶體系統的方塊圖’一記憶體控制器與 一本發明所提供之記憶頁收集器。 圖3詳細說明併有一*介面線路之S te頁收集益。 • 圖4詳細說明圖3所示之收集裝置。 圖5詳細說明圖4所示之緩衝器與一比較線路合作。 圖6顯示記憶頁收集器的控制器如何運作。 發明詳細說明 本發明之一較佳具體實施例係如圖2所示’將一獨立 的記憶頁收集器24置於一處理器22與一記憶體控制器26 之間。或者，記憶頁收集器24的功能可以倂入記憶體控 制器26或設計於處理器22中。 記憶頁收集器24，如同以下所述會更加明顯，在記憶 體要求順序進入記憶體控制器26之前重新安排其順序， 此重新安排的運作加速記憶體存取。尤其，記憶頁收集器 24的功能之一是盡可能久地保留寫入要求，並且將讀取 要求盡可能快地送至記憶體控制器26。記憶頁收集器24 的另一功能是，使用多個緩衝器以將寫入要求分組歸類至 相同的記憶頁，使得記憶頁錯失的不利結果降低。再者， 記憶頁收集器24同時提供如同快取一般的機制以維持資 料的連貫性。 如同圖3所例示，記憶頁收集器24包括一介面線路 30、一記憶頁收集器控制器32、以及一收集裝置34。介 4SIS/200001TW，89plO 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------------------訂---------線 1^" (請先閲讀背面之注意事項再填寫本頁) 491970 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（q ) 面線路3〇分別經由一第一匯流排31以及一第二匯流排33 連接至處理器線路22以及記憶體控制器線路26。介面線 路30從處理器線路22處收到一記憶體讀取要求之後，記 憶頁收集器24檢查其能否提供資料。如果記憶頁收集器 24具有需要的資料，介面線路3〇藉由收集裝置34以及 控制器32的協助，將所需要的資料反送回處理器線路22。 另一方面’如果記憶頁收集器24沒有該資料，讀取要求 被實質上立即且無延遲地轉送至記憶體控制器線路26。 於記憶體控制器線路26存取動態隨機存取記憶體28且獲 得該資料後，介面線路30接著將該資料傳送到處理器線 路22 〇 如果有空間儲存對應至要求的位址以及資料，則寫入 要求被儲存於記憶頁收集器24中，否則，記憶頁控制器 24必須送出一些懸而未決且已經儲存於收集裝置34中的 寫入要求。這些懸而未決的寫入要求，其係個別地分組歸 類至相同的記憶頁，依序被送到記憶體控制器線路26。 除了介於介面控制器30與控制器32間之信號線39 上的一些介面信號以外，REQ、ADDR、以及DATA信 號也被用來作爲介面線路30與記憶頁控制器32間的溝 通。從介面線路30而來的記憶體要求包括例如要求類型 (REQ)、記憶位址（ADDR)以及資料（DATA)等資訊。 其它用在信號線39上的介面信號全部視設計選擇以及設 計的複雜程度，例如，於一雙庫記憶體系統中（dual-bank memory system)，記憶位址（ADDR)信號可能包括一具 4SIS/200001TW，89pl0 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------------訂---------線 (請先閱讀背面之注音？事項再填寫本頁) 491970 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（s) 有十五位元的列位址値、一具有一位元的庫値（bank value)、以及一具有八位元的行位址値，且列位址値與庫 値共同組成存取記憶體的記憶頁値。 當記憶頁收集器控制器32送出信號以控制 收集裝置34的動作時，控制器32同樣也送出位址以及資 料資訊。從控制器32的位址輸出分成二個信號，以 及Mg。而hrfex的功能是選取收集裝置34中所提供的所 有緩衝器40中的其中之一，其在後文敘述中會更加淸楚。 也就是，記憶頁收集器24的控制器32,回應REQ、ADDR 以及DATA信號，產生包括、Mg/w以及 “ία/η等信號以操作收集裝置34。例如，控制器32可能 使用列位址値的較低二位元，以及ADDR信號線上的信 號値，也就是對於前文所述之雙庫記憶體系統而言總共三 個位元，以構成信號。其餘的位元，也就是21個 位元，一起構成Mg信號。當採用這樣的方法時，收集裝 置34具有八個緩衝器。控制器32從收集裝置34接收狀 態信號，包括、/w//、Mgowi以及信號。於一 較佳具體實施例中，comma以包括MATCH、APPEND、 UPDATE、或OUTPUT信號。如後所述，每一個緩衝器包 括多個儲存格，每一個儲存格具有一標籤欄位（tag field) 以及一資料欄位（data field)，以分別對應於一寫入要求 而儲存一標籤値以及一資料値。記憶體要求的分組歸類係 透過hdex信號的安排而達成。每一次控制器32發出一 指令，從控制器3 2之位址輸出內進來的信號，與 4SIS/200001TW, 89pl0 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------------丨丨訂“·--------線f (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 491970 A7 B7 五、發明說明（q) 儲存於由信號所選取之緩衝器的每一個儲存格中的 標籤値進行比較，如果比較結果是相符合’則觸發（assert) 一對應於該儲存格的命中位元（hit_bit)。接著將這命中 位元輸入到對應的儲存格’以根據指令的類型致動儲存格 的操作。所有的命中位元一起進行「或」的邏輯運算以產 生命中信號輸入到控制器32。從收集裝置34而來的/w// 信號表示，收集裝置34的每一個緩衝器內所有的儲存格 儲存著有效的資料’而且沒有儲存格可以用來作爲更進一 步的儲存。 圖4說明收集裝置34的一較佳具體實施例，其包括 數個緩衝器40。信號以及心係被 輸入到所有的緩衝器40。如前所述，/«Αχ信號只選取其 中之一緩衝器40,被/以^選取的緩衝器40根據c〇mm㈣ 的類型處理以及心MM。每一個緩衝器40輸出多 數個有效位元，個別對應於緩衝器40中的多數個儲存格， 並且輸出一 信號、一 以及一心信號。每一 個緩衝器40中的儲存格輸出其中的標籤値到比較線路 42，比較線路42同樣也輸入Mg/«信號。每一個儲存格 的標籤値與MgM信號的比較結果以命中位元代表，輸入 到每一個對應的儲存格。如前所述，所有的命中位元一起 作「或」的邏輯運算以產生命中信號輸入到控制器32， 將以及（iWaow(信號輸入到控制器32。於一較佳 具體實施例中，comma以包括MATCH、APPEND、UPDATE 或OUTPUT信號。MATCH指令使得緩衝器40檢查儲存 4SIS/200001TW, 89pl0 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------------丨-訂---------線t (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 491970 A7 B7 五、發明說明（（〇 ) 格中是否有一標籤與信號線Mg/〃上進來的標籤相符合， 如果有一符合者，則觸發一對應的命中位元信號以及以7 信號，且當其爲一讀取(READ)要求時從緩衝器40讀取資 料，否則，使命中位元信號失效（de-asserted)。當觸發/πΎ 信號時，命中位元信號的値被轉換成位址値以儲存至一 Update指標暫存器53，以下會進一步說明Update指標暫 存器53。根據信號，MATCH指令選擇性地使用剛提 到的位址値設定Update指標暫存器53，並且於如果有一 命中情況時將資料送回。APPEND指令使一組標籤（位址） 以及資料以附加的方式儲存於緩衝器中。UPDATE指令取 代或更新儲存格中的資料，該儲存格係藉由心M/n信號 上的値由Update指標暫存器53所表示。OUTPUT指令使 得一組資料以及標籤從緩衝器輸出。所要註明的是，由指 令所操作的儲存格，是具有與MgM信號上之進來的標籤 値相同位址値的儲存格。 圖5說明緩衝器40的一較佳具體實施例、與比較線 路42。緩衝器40包括複數個儲存格50，以及指示緩衝器 中要進行存取之儲存格的位置的三個指標暫存器。於該較 佳具體實施例中，該複數個儲存格50是以一環狀緩衝器 結構（ring buffer structure)的形式安排，每一個儲存格 50包括一資料欄位以及一標籤（位址）欄位，且緩衝器40 中之儲存格50的位置是分別由前端指標暫存器（Head pointer register) 51、尾端指標暫存器（Tail pointer register) 55 以及更新指標暫存器（Update pointer register) 4SIS/200001TW, 89pl0 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） --------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 491970 A7 B7 五、發明說明（u) 53所表示。前端指標暫存器51指向要在下一次將資料以 及位址讀取出來的儲存格，尾端指標暫存器55指向位址 以及資料要被附加至其中的儲存格，更新指標暫存器53 指向資料以及位址値可以被更新的儲存格。如同稍前所 述，當信號被觸發時，命中位元信號被轉換成一位址 値，以被儲存到更新指標暫存器53，且UPDATE指令取 代儲存格中的資料，該儲存格係藉由心信號上的値 由更新指標暫存器53所表示。這三個指標暫存器係對於 從控制器32而來的信號而運作。 緩衝器40中具有二個有效位元以及命中位元的陣列， 有效位元表示相對應的儲存格是否儲存一有效資料，且命 中位元表示相對應的儲存格是否儲存一標籤値與出現在 Mg/«信號線上進來的標籤値相同。所有的命中位元信號 一起進行「或（OR)」的邏輯運算，以形成命中信號，而 所有的有效信號進行「及（AND)」的邏輯運算，以形成 /w//信號。 比較線路42包括數個AND、OR線路以及相較 (Compare)線路54。每一個相較線路54用以比較從一 個相對應儲存格所輸出之標籤値與Mg/«信號線上的標籤 値，比較結果輸入至一個相對應的AND線路，另一個AND 線路的輸入是一相對應於儲存格50的有效位元（valid bit)。AND線路的輸出是前述的命中（hit)位元信號。 當控制器32發出一 MATCH指令時，每一個由&dex 所選取之緩衝器中的標籤，只要相對應於儲存格的有效位 4SIS/200001TW, 89pl0 11 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------------訂---------線^1- (請先閱讀背面之注意事項再填寫本頁) 491970 經濟部智慧財產局員工消費合作社印製 A7 B7Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of Invention (G) A memory system. Fig. 2 illustrates a block diagram of a memory system ', a memory controller and a memory page collector provided by the present invention. Figure 3 details the Ste page collection benefit with a * interface line. • Figure 4 details the collection device shown in Figure 3. FIG. 5 illustrates the cooperation of the buffer shown in FIG. 4 with a comparison circuit. Figure 6 shows how the controller of the memory page collector works. Detailed Description of the Invention A preferred embodiment of the present invention is shown in Fig. 2 'which places an independent memory page collector 24 between a processor 22 and a memory controller 26. Alternatively, the function of the memory page collector 24 may be incorporated in the memory controller 26 or designed in the processor 22. The memory page collector 24, as will be more apparent below, rearranges the order of the memory before the memory request sequence enters the memory controller 26. This rescheduling operation speeds up memory access. In particular, one of the functions of the memory page collector 24 is to retain the write request as long as possible and send the read request to the memory controller 26 as quickly as possible. Another function of the memory page collector 24 is to use multiple buffers to group write requests into the same memory page, so that the adverse effect of memory page miss is reduced. Furthermore, the memory page collector 24 also provides a cache-like mechanism to maintain data consistency. As illustrated in FIG. 3, the memory page collector 24 includes an interface circuit 30, a memory page collector controller 32, and a collection device 34. 4SIS / 200001TW, 89plO 6 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) --------------------- Order- ------- line 1 ^ " (Please read the precautions on the back before filling out this page) 491970 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (q) Line 3 Connected to the processor circuit 22 and the memory controller circuit 26 via a first bus 31 and a second bus 33. After the interface circuit 30 receives a memory read request from the processor circuit 22, the memory page collector 24 checks whether it can provide data. If the memory page collector 24 has the required data, the interface circuit 30 returns the required data to the processor circuit 22 with the assistance of the collecting device 34 and the controller 32. On the other hand, if the memory page collector 24 does not have the data, the read request is forwarded to the memory controller circuit 26 substantially immediately and without delay. After the memory controller circuit 26 accesses the dynamic random access memory 28 and obtains the data, the interface circuit 30 then transmits the data to the processor circuit 22. If there is room to store the address and data corresponding to the request, then The write request is stored in the memory page collector 24, otherwise, the memory page controller 24 must send out some pending write requests that have been stored in the collection device 34. These pending write requests are individually grouped into the same memory page and sequentially sent to the memory controller circuit 26. In addition to some interface signals on the signal line 39 between the interface controller 30 and the controller 32, the REQ, ADDR, and DATA signals are also used as the communication between the interface line 30 and the memory page controller 32. The memory request from the interface line 30 includes information such as a request type (REQ), a memory address (ADDR), and data (DATA). The other interface signals used on the signal line 39 all depend on the design choice and complexity of the design. For example, in a dual-bank memory system, the ADDR signal may include a 4SIS / 200001TW, 89pl0 7 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -------------------- Order ----- ---- Line (Please read the note on the back? Matters before filling out this page) 491970 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (s) There are 15-digit column addresses 値, A bank value with one bit (bank value) and a row address with eight bits, and the column address 値 and the bank together form a memory page 存取 which accesses the memory. When the memory page collector controller 32 sends a signal to control the operation of the collecting device 34, the controller 32 also sends out the address and data information. The address output from the controller 32 is divided into two signals, and Mg. The function of hrfex is to select one of all the buffers 40 provided in the collecting device 34, which will be more eloquent in the following description. That is, the controller 32 of the memory page collector 24 responds to the REQ, ADDR, and DATA signals, and generates signals including, Mg / w, and “ία / η” to operate the collection device 34. For example, the controller 32 may use a column address The lower two bits of ， and the signal 値 on the ADDR signal line, that is, for the dual-bank memory system described above, a total of three bits constitute the signal. The remaining bits are 21 bits Yuan, together form the Mg signal. When this method is used, the collecting device 34 has eight buffers. The controller 32 receives status signals from the collecting device 34, including / w //, Mgowi, and signals. In the embodiment, the comma includes MATCH, APPEND, UPDATE, or OUTPUT signals. As described later, each buffer includes a plurality of cells, and each cell has a tag field and a data field. (Data field) to store a tag 値 and a data 分别 respectively corresponding to a write request. The grouping of memory requirements is achieved through the arrangement of the hdex signal. Each time the controller 32 issues an instruction , The signal coming from the address output of the controller 32, and 4SIS / 200001TW, 89pl0 8 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) --------- -------- 丨 丨 Order "· -------- line f (Please read the phonetic on the back? Matters before filling out this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 491970 A7 B7 V. Description of the invention (q) The tags stored in each cell of the buffer selected by the signal are compared, and if the comparison result is consistent, then an assert is made corresponding to the hit bit of the cell (Hit_bit). This hit bit is then entered into the corresponding cell ' to actuate the operation of the cell according to the type of instruction. All the hit bits are logically ORed together to generate a life signal to the controller 32. The / w // signal from the collection device 34 indicates that all the cells in each buffer of the collection device 34 store valid data 'and that no cells can be used for further storage. FIG. 4 illustrates a preferred embodiment of the collection device 34, which includes a plurality of buffers 40. As shown in FIG. The signal and the heart system are input to all the buffers 40. As mentioned earlier, the / «Aχ signal selects only one of the buffers 40, and the buffers 40 selected by / are processed according to the type of comm and the MM. Each buffer 40 outputs a plurality of significant bits, each corresponding to a plurality of cells in the buffer 40, and outputs a signal, a and a heart signal. The cell in each buffer 40 outputs a label therein to the comparison circuit 42, and the comparison circuit 42 also inputs the Mg / «signal. The comparison result between the label 値 of each cell and the MgM signal is represented by the hit bit, and it is input to each corresponding cell. As mentioned above, all the hit bits are logically ORed together to generate a hit signal and input to the controller 32, and the (iWaow) signal is input to the controller 32. In a preferred embodiment, comma To include MATCH, APPEND, UPDATE or OUTPUT signals. The MATCH instruction enables the buffer 40 to check and store 4SIS / 200001TW, 89pl0 9 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------ ------------ 丨 -Order --------- line t (Please read the precautions on the back before filling out this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 491970 A7 B7 V. Description of the invention (whether there is a label in the (0) grid that matches the label coming from the signal line Mg / 〃, if there is a match, then a corresponding hit bit signal and a 7 signal are triggered, and when it Data is read from the buffer 40 when a READ request is made, otherwise the mission bit signal is de-asserted. When the / πΎ signal is triggered, the 値 of the hit bit signal is converted into an address 値To the Update indicator register 53. The Update instruction will be further explained below. Mark register 53. According to the signal, the MATCH instruction selectively uses the address just mentioned to set the Update index register 53 and send the data back if there is a hit. The APPEND instruction causes a set of tags (bits Address) and the data is stored in the buffer in an additional way. The UPDATE command replaces or updates the data in the cell, which is indicated by the Update indicator register 53 by the 上 on the M / n signal. OUTPUT The instruction causes a set of information and labels to be output from the buffer. It should be noted that the cell operated by the instruction is a cell with the same address (the same address) as the label coming in on the MgM signal. Figure 5 illustrates the buffer 40 And a comparison circuit 42. The buffer 40 includes a plurality of cells 50, and three index registers indicating the positions of the cells in the buffer to be accessed. In this preferred embodiment, In the embodiment, the plurality of cells 50 are arranged in a ring buffer structure. Each cell 50 includes a data field and a label (address) field. And the position of the cell 50 in the buffer 40 is respectively the head pointer register 51, the tail pointer register 55, and the update pointer register 4SIS / 200001TW, 89pl0 10 This paper size is applicable to China National Standard (CNS) A4 (210 χ 297 mm) -------------------- Order ---- ----- line (please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 491970 A7 B7 V. Indication of Invention (u) 53. The front-end pointer register 51 points to the cell where the data and address will be read out next time, the tail-end pointer register 55 points to the cell where the address and data are to be appended, and the updated pointer register 53 points Data and address: cells that can be updated. As mentioned earlier, when the signal is triggered, the hit bit signal is converted into a bit address to be stored in the update pointer register 53, and the UPDATE instruction replaces the data in the cell. The chirp on the heart signal is indicated by the update index register 53. These three index registers operate on signals from the controller 32. The buffer 40 has an array of two valid bits and a hit bit. The valid bit indicates whether the corresponding cell stores a valid data, and the hit bit indicates whether the corresponding cell stores a tag. The labels coming in on the Mg / «signal line are the same. All hit bit signals are logically ORed together to form a hit signal, and all valid signals are logically ANDed to form a / w // signal. The comparison circuit 42 includes several AND, OR circuits, and a comparison circuit 54. Each comparison line 54 is used to compare the label 値 output from a corresponding cell with the label on the Mg / «signal line. The comparison result is input to a corresponding AND line, and the input of the other AND line is a phase Corresponds to the valid bit of cell 50. The output of the AND line is the aforementioned hit bit signal. When the controller 32 issues a MATCH instruction, each label in the buffer selected by & dex, as long as it corresponds to the valid bit of the cell 4SIS / 200001TW, 89pl0 11 This paper standard applies to China National Standard (CNS) A4 specification (210 X 297 mm) ------------------- Order --------- line ^ 1- (Please read the precautions on the back first (Fill in this page again) 491970 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7
五、發明說明（\D 元係被觸發的（asserted)，則分別與進來的標籤値進行比 較。比較結果可能是命中或者未命中（miss)，這個結果 於必要時用來控制UPDATE動作。如果控制器32發出一 UPDATE指令，進來的資料被寫入至其命中位元係被觸發 的儲存格50。當控制器32發出一 APPEND指令，緩衝器 40將心M/w信號線上的資料値、以及信號線上的 標籤値，儲存到由尾端指標暫存器55所指向的儲存格50， 並且，尾端指標暫存器55·接著增加或者減少以指向下一 個儲存格。當控制器32發出一 OUTPUT指令，緩衝器40 將前端指標暫存器51所指向之儲存格50中所儲存的資料 以及標籤送出，並且，前端指標暫存器51接著增加或者 減少以指向下一個儲存格。 圖6說明本發明之記憶頁收集器24操作所根據之流 程圖。總而言之，當記憶頁收集器24從處理器22收到一 記憶體要求之後，記憶頁收集器24首先檢查其中所儲存 的位址値，是否有與記憶體要求所指定的位址値相等者。 如果有符合者而且牽涉到讀取運算，記憶頁收集器24從 本身取得資料並且將資料送回處理器22。否則，也就是 要求係爲寫入時，記憶頁收集器24藉由發出一如上所述 之UPDATE指令以更新儲存於相對應儲存格中的値。 當沒有相符合的位址、且要求係爲讀取時，記憶頁收 集器24僅將讀取要求送到（發出至）記憶體控制器26而 沒有任何內部動作。另一方面，如果記憶體要求爲寫入， 且收集裝置34中的緩衝器並未滿載（full)時，記憶頁 4SIS/200001TW, 89pl0 12 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂---------線秦 經濟部智慧財產局員工消費合作社印製 491970 A7 B7 五、發明說明03) 收集器24將對應於該要求的資料以及位址（標籤）値， 附加至一儲存格中，其中該儲存格是尾端指標暫存器55 値所指向的且具有一失效的（de-asserted)有效位元。另 一方面，如果緩衝器已經滿載，記憶頁收集器24首先將 緩衝器中所有的寫入要求發送至記憶體控制器26,然後 將相對應於現行寫入要求的資料以及位址値附加至一儲存 格中。 元件符號說明 11.動態隨機存取記憶體 12.第一匯流排 13.處理器 14.第二匯流排 15·記憶體控制器 22處理器 24.記憶頁收集器 26.記憶體控制器 28.動態隨機存取記憶體 33.第二匯流排 30.介面線路 39.信號線 32.記憶頁收集器控制器 34.收集裝置 31.第一匯流排 40.收集緩衝器 42.比較線路 择 50.儲存格 51.前端指標暫存器 $ 55.尾端指標暫存器 ^ % 53.更新指標暫存器 54.線路 4SIS/200001TW, 89pl0 13 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） V·* --------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁)V. Description of the invention (\ D element is asserted, then it is compared with the incoming tag 値. The comparison result may be a hit or a miss. This result is used to control the UPDATE action if necessary. If The controller 32 issues an UPDATE instruction, and the incoming data is written into the cell 50 whose trigger bit system is triggered. When the controller 32 issues an APPEND instruction, the buffer 40 sends the data on the M / w signal line. And the label 値 on the signal line is stored in the cell 50 pointed to by the tail pointer register 55, and the tail pointer register 55 · then increases or decreases to point to the next cell. When the controller 32 issues An OUTPUT instruction, the buffer 40 sends the data and labels stored in the cell 50 pointed by the front-end index register 51, and the front-end index register 51 then increases or decreases to point to the next cell. Figure 6 Describes the flowchart on which the memory page collector 24 of the present invention operates. In summary, when the memory page collector 24 receives a memory request from the processor 22, the memory page collection 24 First check whether the address 値 stored therein is equal to the address 指定 specified by the memory request. If there is a match and it involves a read operation, the memory page collector 24 obtains data from itself and sends the data Return to the processor 22. Otherwise, when the request is a write, the memory page collector 24 updates the frame stored in the corresponding cell by issuing an UPDATE instruction as described above. When there is no matching address When the request is a read, the memory page collector 24 only sends (sends) the read request to the memory controller 26 without any internal action. On the other hand, if the memory request is a write and collects When the buffer in the device 34 is not full, the memory page 4SIS / 200001TW, 89pl0 12 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before (Fill in this page) Order --------- Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the Qin Dynasty Printed 491970 A7 B7 V. Invention Description 03) The collector 24 will correspond to the required information and address (label )value Attached to a cell, where the cell is the tail pointer register 55 points and Zhi (de-asserted) having a valid bit failure. On the other hand, if the buffer is full, the memory page collector 24 first sends all write requests in the buffer to the memory controller 26, and then appends the data and address corresponding to the current write request to In a cell. Component symbol description 11. Dynamic random access memory 12. First bus 13. Processor 14. Second bus 15 Memory controller 22 Processor 24. Memory page collector 26. Memory controller 28. Dynamic random access memory 33. Second bus 30. Interface line 39. Signal line 32. Memory page collector controller 34. Collection device 31. First bus 40. Collection buffer 42. Comparison line selection 50. Cell 51. Front-end indicator register $ 55. Tail-end indicator register ^% 53. Update indicator register 54. Line 4SIS / 200001TW, 89pl0 13 This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) V · * -------------------- Order --------- line (Please read the precautions on the back before filling in this page)