KR0179755B1 - Semiconductor device manufacturing method - Google Patents

Abstract

The present invention relates to a semiconductor device and a method of manufacturing the same. By forming a plurality of trenches in the lower portion of the gate electrode, the length and width of the gate electrode can be widened by the bending of each trench, and the size of the gate electrode according to the number of the trenches. Since it can be reduced, it is very advantageous for high integration, and even when the hot carrier is injected from the drain side, the electric field in the Y direction is lessened by the height difference of the gate electrode, thereby preventing the characteristic degradation caused by the hot carrier.

Description

Semiconductor device manufacturing method

1 is a schematic layout diagram of a semiconductor device according to the prior art.

2 is a cross-sectional view of a semiconductor device according to the prior art.

3 is a cross-sectional view of another semiconductor device according to the prior art.

4 is a layout diagram of a semiconductor device according to the present invention.

5 is a cross-sectional view of the manufacturing process of Example 1 of the semiconductor device according to the present invention;

6 is a sectional view of Embodiment 2 of a semiconductor device according to the present invention.

* Explanation of symbols for main parts of the drawings

11,14: 1st, 2nd oxide film 12: nitride film

13 photo etching mask 16 gate electrode

17: source / drain region 18: spacer

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for reducing the size of a gate without degrading the characteristics of the transistor.

In general, in the case of an NMOS transistor, as shown in FIG. 2, a transistor includes a gate oxide film 2 on a semiconductor substrate 100 and polycrystalline silicon doped with impurities, for example, as a conductive material. A gate electrode 3 formed by photolithography to have a layout as shown in FIG. 1 after coating to a thickness, a spacer 4 formed on both sides of the gate electrode 3, the gate electrode 3, and Source / drain regions 1 formed by injecting N ⁺ -type impurities into the semiconductor substrate 100 by applying the spacer 4 as a mask and channel forming impurities 5 formed in the semiconductor substrate under the gate electrode 3. ).

However, in the case of using the gate electrode 3 as described above, the resistivity is preferably low, but as the semiconductor device becomes finer and faster, the conventional gate electrode is used as it is, so that the wiring resistance and capacity increase. In order to solve this problem, a method of changing the material forming the gate electrode or changing the structure of the gate electrode has been attempted.

More specifically, in the former case, a method of using a high melting point metal silicide having a lower resistance value than a polysilicon generally used has been developed, but this method has a low chemical resistance and oxidation resistance compared to polysilicon. In the latter case, a method of forming a V-shaped groove in a semiconductor substrate under the gate electrode 3 using a photolithography mask is developed, as shown in FIG. The effect can be widened, but only one groove was formed, so the effect was limited.

Accordingly, an object of the present invention is to manufacture a semiconductor device that can effectively extend the length and width of the gate electrode by the bending of each trench by forming a plurality of trenches in the lower portion of the gate electrode in order to solve the above problems. To provide.

The method of manufacturing a semiconductor device of the present invention for achieving the above object is a step of sequentially forming a first oxide film and a nitride film on a semiconductor substrate, and by applying, exposing and developing a photoresist on the nitride film to form a photo etching mask Forming a plurality of trenches on the semiconductor substrate by etching the nitride film, the first oxide film, and the semiconductor substrate by applying the photolithography mask; and removing the photoetch mask, nitride film, and first oxide film. Forming a second oxide film on the entire surface of the resultant after removing the first oxide film, and implanting impurities on the semiconductor substrate etched through the second oxide film to a predetermined depth; Forming a gate electrode by applying a conductive material and then etching the photo; applying the gate electrode as a mask By implanting impurities on the conductive substrate characterized in that the manufacture, including a step of forming a source / drain region.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

First, in the structure of the semiconductor device of the present invention, a plurality of trenches are formed in the channel length L direction or trenches are formed in the width W direction so that the channel length can be increased several times on the layout as shown in FIG. As shown in (c) and 6 of FIG. 5, the trenches in the lower portion of the gate electrode are located below the source / drain regions, or vice versa, above the source / drain regions. Is as follows.

First, in the first embodiment, when the trench under the gate electrode is located below the semiconductor substrate where the source / drain regions are formed, as shown in FIG. 5A, the semiconductor substrate 100 is formed. After forming the first oxide film 11 and the nitride film 12 in a predetermined thickness, a photoresist mask 13 for forming a trench is formed by applying, exposing and developing a photoresist on the nitride film 12. .

In this case, the portion where the gate electrode is not formed is protected from etching by the photolithography mask 13.

In FIG. 2B, the photolithography mask 13 is applied to etch the nitride film 12, the first oxide film 11, and the semiconductor substrate 100 to a predetermined depth to form a plurality of trenches at predetermined intervals. Thereafter, after the nitride layer 12 and the first oxide layer 11 are removed, the second oxide layer 14 is formed on the entire surface of the resultant product from which the nitride layer 12 and the first oxide layer 11 are removed, and then the gate electrode is formed. Impurity ions are implanted into the semiconductor substrate of the portion to be formed to form the impurity region 15.

In (c), a polysilicon doped with, for example, an impurity doped as a conductive material is deposited on the entire surface of the resultant, and then patterned, whereby a plurality of trenches are positioned below the source / drain region 17. The gate electrode 16 is formed, the spacer 18 is formed on both sides of the gate electrode 16, and the gate electrode 16 and the spacer 18 are applied as a mask to the inside of the semiconductor substrate 100. The source / drain regions 17 are formed by implanting impurities.

On the other hand, in Example 2, as shown in FIG. 6, a plurality of trenches are formed by forming a photolithography mask with a photoresist only at a portion where the gate electrode is to be formed and applying the same, and differently from Example 1, a gate electrode is formed. Etching the part that will not be done will result in the location of the trench above the source / drain area when forming the source / drain area by a subsequent process.

Subsequently, after the formation of the plurality of trenches, the second oxide layer 14 and the polysilicon are coated on the entire surface of the resultant, and then the polycrystalline silicon is patterned to form a plurality of trenches above the source / drain region 17 by a subsequent process as described above. A gate electrode 16 is formed.

The subsequent steps are the same as those in Example 1, so refer to FIG. 5C.

As described above, according to the present invention, it is possible to reduce the size of the gate electrode according to the number of the plurality of trenches, which is very advantageous for high integration, and the difference in height of the gate electrode even when the hot carrier is injected at the drain side. The electric field in the Y direction is less likely to have a deterioration in characteristics caused by the hot carrier.

Claims (3)

Sequentially forming a first oxide film and a nitride film on the semiconductor substrate, forming a photolithography mask by applying, exposing and developing a photoresist on the nitride film, and applying the photolithography mask to the nitride film, Forming a plurality of trenches on the semiconductor substrate by etching the oxide film and the semiconductor substrate, removing the photolithography mask, nitride film, and first oxide film, and removing the second oxide film on the entire surface of the resultant after removing the first oxide film. Forming a gate electrode; and implanting an impurity to a predetermined depth on the semiconductor substrate etched through the second oxide film; and applying a conductive material to the entire surface of the resultant after implanting the impurity, and then etching the photo to form a gate electrode. And implanting impurities on the semiconductor substrate by applying the gate electrode as a mask to form source / drain regions. Method of manufacturing a semiconductor device, characterized in that comprising including positive. The method of claim 1, wherein the forming of the plurality of trenches protects the semiconductor substrate, except for the region in which the gate electrode is to be formed, with the photolithography mask so that the source / drain regions are positioned higher than the plurality of trenches. A semiconductor device manufacturing method characterized in that. The method of claim 1, wherein the forming of the plurality of trenches forms the photolithography mask only in a predetermined region where the gate electrode is to be formed, thereby etching the semiconductor substrate of the remaining region, thereby forming the plurality of trenches. Method for manufacturing a semiconductor device characterized in that the lower position.