KR0177745B1 - Transmission line interconnection method of semiconductor memory device - Google Patents
Transmission line interconnection method of semiconductor memory device Download PDFInfo
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- KR0177745B1 KR0177745B1 KR1019950024729A KR19950024729A KR0177745B1 KR 0177745 B1 KR0177745 B1 KR 0177745B1 KR 1019950024729 A KR1019950024729 A KR 1019950024729A KR 19950024729 A KR19950024729 A KR 19950024729A KR 0177745 B1 KR0177745 B1 KR 0177745B1
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Abstract
1. 청구범위에 기재된 발명이 속하는 기술 분야 :1. The technical field to which the invention described in the claims belongs:
본 발명은 반도체 메모리 장치의 전송라인접속법에 관한 것이다.The present invention relates to a transmission line connection method of a semiconductor memory device.
2. 발명이 해결하려고 하는 기술적 과제 :2. The technical problem to be solved by the invention:
종래의 경우 전송라인들은 공정상의 어려움으로 인하여 각기 다른 평면적 구조로 형성되었고, 이로 인하여 발생되는 전송라인들간의 임피던스가 매칭이 되지 않으므로 해서 고속의 신호전달에 커다란 장애가 되었다.In the conventional case, transmission lines are formed in different planar structures due to process difficulties, and therefore, impedances between transmission lines generated by the transmission lines are not matched, which is a great obstacle to high-speed signal transmission.
3. 발명의 해결방법의 요지 :3. Summary of the solution of the invention:
본 발명에서는 전송라인들을 동일 평면상에 형성시키고 이를 실버에 폭시공정을 사용하여 접속하므로써 상기 전송라인들간의 임피던스를 매칭되게 하였다.In the present invention, the transmission lines are formed on the same plane and connected to the silver using a foxy process to match the impedances between the transmission lines.
4. 발명의 중요한 용도 :4. Important uses of the invention:
이러한 본 발명에 따른 전송라인형성방법이 제공되므로써 고속의 신호전달이 가능한 반도체 메모리장치가 구현된다.By providing the transmission line forming method according to the present invention, a semiconductor memory device capable of high-speed signal transmission is realized.
Description
제1도는 종래의 전송라인접속법을 보여주는 도면.1 is a view showing a conventional transmission line connection method.
제2도는 본 발명의 일실시예에 따른 전송라인접속법을 보여주는 도면.2 is a view showing a transmission line connection method according to an embodiment of the present invention.
제3도는 본 발명의 다른 실시예에 따른 전송라인접속법을 보여주는 도면.3 is a view showing a transmission line connection method according to another embodiment of the present invention.
제4도는 본 발명의 실시예에 따른 실버 에폭시공정을 보여주는 도면.4 is a view showing a silver epoxy process according to an embodiment of the present invention.
제5도는 본 발명의 또 다른 실시예에 따른 전송라인접속법을 보여주는 도면.5 is a view showing a transmission line connection method according to another embodiment of the present invention.
본 발명은 반도체 메모리장치에 관한 것으로, 특히 소자들간에 유통되는 신호들을 전송하기 위한 전송라인들간의 접속방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a connection method between transmission lines for transmitting signals distributed between devices.
반도체 소자의 제조공정 및 설계기술의 눈부신 발전에 힘입어 반도체 소자들의 동작특성은 끊임없이 개선되어 왔다. 이러한 발전에 힘입어 오늘날의 컴퓨터는 다기능화되어 가고 있으며, 이에 따라 현재의 정보사회는 점점 더 고도화되어 가고 있다. 상기와 같은 반도체 소자의 성능개선은 크게 두가지 분야의 발전에 의해서 주로 이루어져 왔다. 첫째, 공정기술의 발달로 인한 소자들의 집적화이다. 이러한 집적화기술의 발달로 인하여 값싼 반도체 소자들을 대량으로 공급할 수 있게 되었고 현재와 같은 컴퓨터 및 전자기기의 대량보급이 가능하게 되었다. 둘째, 반도체 소자들의 기능개선으로 인한 신호처리속도의 향상이다. 이와 같은 두 분야의 비약적인 발전을 바탕으로 집적화된 소자들간에 고속으로 동작하는 반도체 메모리장치의 출현이 가능하게 되었다. 이에 따라 단위시간당 정보처리속도는 획기적으로 증가되고 있다. 그러나 처리하거나 유통해야할 정보의 양은 아직도 끊임없이 증가하고 있으며 상기 정보를 더욱 더 신속하게 처리하고자 하는 필요성은 예전보다 더 많이 증대되고 있다. 이에 따라 유통신호들을 고속으로 전송하기 위한 연구들이 지속적으로 진행되고 있다. 전송라인들간의 임피던스를 매칭(matching)시키는 것은 상기 신호를 고속으로 전송하기 위한 필수적인 방법이나 서로 다른 구조, 예를 들면 입체적으로 구성되는 전송라인들간의 임피던스를 매칭시키는 데는 어려움이 많이 따른다.Thanks to the remarkable development of semiconductor device manufacturing process and design technology, the operation characteristics of semiconductor devices have been constantly improved. Thanks to these developments, today's computers are becoming more and more versatile, and the information society of today is becoming more and more sophisticated. Performance improvement of the semiconductor device as described above has been largely made by the development of two fields. First is the integration of devices due to the development of process technology. The development of such integration technology has made it possible to supply inexpensive semiconductor devices in large quantities and to enable mass distribution of computers and electronic devices as they are today. Second, the signal processing speed is improved due to the functional improvement of semiconductor devices. The rapid development of these two fields allows the emergence of semiconductor memory devices that operate at high speed between integrated devices. As a result, the information processing speed per unit time has increased dramatically. However, the amount of information to be processed or distributed is still increasing and the need to process the information more rapidly is increasing more than ever before. Accordingly, researches for transmitting distribution signals at high speed have been continuously conducted. Matching impedances between transmission lines is an essential method for transmitting the signal at high speed, but it is difficult to match impedances between transmission lines having different structures, for example, three-dimensionally.
제1도는 종래의 전송라인접속법을 보여주는 도면이다.1 is a view showing a conventional transmission line connection method.
제1도를 참조하며, 전송라인(12)은 도시되지 아니한 마더보더(mother board)상에 형성되어 있고, 상기 전송라인(12)의 일단은 리드프레임(lead frame)(14)에서 패캐지의 외부로 도출된 부분인 빔리드(beam lead)와 접속된다. 상기 리드프레임(14)의 다른쪽 부분은 본딩와이어(16)를 통하여 본딩패드(18)와 접속된다. 상기 본딩패드(18)는 칩(20)상에 형성되고 상기 칩(20)은 칩캐리어(22)상에 접착된다.Referring to FIG. 1, the transmission line 12 is formed on a mother board (not shown), and one end of the transmission line 12 is external to the package in a lead frame 14. It is connected to the beam lead (beam lead) which is a part derived from. The other part of the lead frame 14 is connected to the bonding pads 18 through the bonding wires 16. The bonding pads 18 are formed on the chip 20 and the chips 20 are bonded onto the chip carrier 22.
상기와 같은 방법으로 전송라인들이 배치된 구조에 있어서, 상기 전송라인들을 단면적으로 보면, 각각 다른 평면상에 배치되고 각 부분의 전송라인이 구조적으로 다른 형태를 지니고 있다. 이와 같이 각기 다른 평면상에 배치되는 각기 다른 구조에서 상기 전송라인들간의 임피던스를 매칭시키기란 대단히 어려운 사안이다. 이러한 임피던스의 미스매칭(mismatching)에 따라 상기 전송라인들간의 신호전달속도는 제약을 받게 되고, 상기 임피던스의 미스매칭에 따라 전력손실이 커지게 되고 신호파형의 일그러짐이 발생하게 된다. 이러한 임피던스의 미스매칭에 따른 문제를 최소화하기 위하여, 상기 리드프레임 및 본딩와이어의 규격이 정해지고 있다. 따라서 패키징(packaging) 및 마더보더위의 회로설계기술은 점점 더 까다로와 지고 있으며 이러한 규격을 만족시킨다 하더라도 전송라인들간의 임피던스 미스매칭에 따른 전력손실을 줄이는 문제와 신호전달의 속도감소는 피할 수 없게 된다.In the structure in which the transmission lines are arranged in the above manner, when the transmission lines are viewed in cross-section, they are arranged on different planes and the transmission lines of the respective parts have structurally different shapes. As such, it is very difficult to match impedances between the transmission lines in different structures arranged on different planes. According to the mismatching of the impedance, the signal transmission speed between the transmission lines is restricted, and the power loss increases due to the mismatching of the impedance, and distortion of the signal waveform occurs. In order to minimize the problem caused by mismatching of the impedance, the specifications of the lead frame and the bonding wire are determined. Therefore, the circuit design technology of packaging and motherboard is becoming more and more demanding, and even if it meets these specifications, the problem of reducing the power loss due to impedance mismatch between transmission lines and the speed reduction of signal transmission can be avoided. There will be no.
따라서 본 발명의 목적은 전송라인들간의 임피던스를 매칭시켜 고속으로 신호전송이 가능한 반도체 메모리장치의 전송라인접속법을 제공하는 데 있다.Accordingly, an object of the present invention is to provide a transmission line connection method of a semiconductor memory device capable of transmitting signals at high speed by matching impedance between transmission lines.
본 발명의 다른 목적은 전력소비를 줄이는 반도체 메모리장치의 전송라인접속법을 제공하는 데 있다.Another object of the present invention is to provide a transmission line connection method of a semiconductor memory device which reduces power consumption.
상기 본 발명의 목적을 달성하기 위하여 본 발명에 따른 반도체 메모리장치의 전송라인접속법은, 소정의 제1라인과 소정의 제2라인을 동일 평면상에 형성하고 상기 제1라인과 제2라인의 구조를 같게하여 상기 제1라인과 제2라인간의 임피던스를 매칭시킴을 특징으로 한다.In order to achieve the object of the present invention, a transmission line connection method of a semiconductor memory device according to the present invention comprises forming a predetermined first line and a predetermined second line on the same plane, and forming the structure of the first line and the second line. It is characterized by matching the impedance between the first line and the second line by the same.
이하 첨부된 도면을 사용하여 본 발명의 바람직한 실시예를 설명하겠다. 도면들중 동일한 구성 및 동일동작을 하는 소자들 및 회로들에 대해서는 가능한한 어느 곳에서든지 동일한 참조번호 및 동일참조부호를 사용하겠다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. The same reference numerals and the same reference numerals will be used wherever possible for elements and circuits having the same configuration and the same operation in the drawings.
제2도는 본 발명의 일실시예에 따른 전송라인접속법을 보여주는 도면이고, 제3도는 본 발명의 다른 실시예에 따른 전송라인접속법을 보여주는 도면이다. 또, 제4도는 본 발명의 실시예에 따른 실버에폭시공정을 보여주는 도면이고, 제5도는 본 발명의 또 다른 실시예에 따른 전송라인접속법을 보여주는 도면이다.2 is a view showing a transmission line connection method according to an embodiment of the present invention, Figure 3 is a view showing a transmission line connection method according to another embodiment of the present invention. 4 is a view showing a silver epoxy process according to an embodiment of the present invention, Figure 5 is a view showing a transmission line connection method according to another embodiment of the present invention.
제2도에서 극명하게 드러나듯이 전송라인들 예컨대 전송라인(12)과 리드프레임(14)과 본딩패드(18)는 모두 동일 평면상에 배치되고 동일한 구조로 설계된다. 상기 전송라인들간의 접속은 실버에폭시(silver epoxy)공정으로 이루어진다. 상기와 같이 전송라인들을 동일한 평면상에 배치하기 위하여 베리드칩기술(Buried-Chip Technology)이 사용된다. 즉, 칩캐리어(22)의 소정영역을 파서 그 속에 칩(20)을 묻어버리는 형식이다. 칩캐리어(22)는 상기 칩(20)과 마찬가지로 마더보더(26)의 소정영역에 묻히는 베리드칩(buried chip)기술이 사용된다. 또, 상기 제2도와 같은 전송라인은 마이크로스트립(microstrip)방법이나 코플래너 웨이브가이드(coplanar waveguide)방법으로 형성된 것이다. 제3도에서 전송라인들은 코플래너 웨이브가이드(coplanar waveguide) 구조로 형성된 전송라인들을 보여주고 있다. 나머지 구조는 상기 제2도와 동일하다. 상기와 같은 마이크로스트립방법 및 코플래너 웨이브가이드구조에 대한 사항은 미합중국 특허 제5262739호, 제목 WAVEGUIDE ADAPTORS에 상세히 개시되어 있다.As clearly shown in FIG. 2, the transmission lines, for example, the transmission line 12, the lead frame 14, and the bonding pads 18 are all arranged on the same plane and are designed in the same structure. The connection between the transmission lines is made by a silver epoxy process. Burried-Chip Technology is used to arrange the transmission lines on the same plane as above. In other words, a predetermined area of the chip carrier 22 is dug and the chip 20 is buried therein. Similar to the chip 20, the chip carrier 22 uses a buried chip technology that is buried in a predetermined area of the mother board 26. In addition, the transmission line as shown in FIG. 2 is formed by a microstrip method or a coplanar waveguide method. In FIG. 3, the transmission lines show transmission lines formed of a coplanar waveguide structure. The rest of the structure is the same as in FIG. Details of such microstrip methods and coplanar waveguide structures are disclosed in detail in US Pat. No. 5,526,39, entitled WAVEGUIDE ADAPTORS.
제4도는 전술한 바와 같이 제2도 및 제3도에 나타난 전송라인들간의 접속을 위한 실버에폭시공정을 보여주는 도면이다.4 illustrates a silver epoxy process for connection between transmission lines shown in FIGS. 2 and 3 as described above.
상기 제4도에 따른 실버에폭시공정에 따라 제1전송라인과 제2전송라인이 접속됨에 따라 와이어가 필요없는 와이어레스(wireless)본딩이 구현된다. 본딩핀(30)의 끝부분의 크기는 수㎛정도의 크기로 팁(tip)의 끝에는 점성을 가지고 있는 도전성액체(conducting liquid)의 한 종류인 실버에폭시가 묻어 있다. 그 팁이 제1전송라인(34)와 제2전송라인(36)연결된 접속될 부분에 형성되고 상기 실버에폭시의 점성과 가열전까지의 시간에 의해 상기 실버에폭시의 양이 결정된다. 상기 실버에폭시가 표면위에 놓여진 후 약 30분정도 300℃온도의 오븐(oven)에서 가열하면 실버에폭시도 경화되고 전도도도 상승하여 임피던스의 매칭이 유지된 전기적 연결이 가능해 지는 것이다.According to the silver epoxy process according to FIG. 4, wire bonding without wires is realized as the first transmission line and the second transmission line are connected. The tip of the bonding pin 30 has a size of about several μm, and the tip of the tip is buried in silver epoxy, which is a kind of conductive liquid having a viscosity. The tip is formed in the portion to be connected to which the first transmission line 34 and the second transmission line 36 are connected, and the amount of the silver epoxy is determined by the viscosity of the silver epoxy and the time until heating. After the silver epoxy is placed on the surface and heated in an oven at 300 ° C. for about 30 minutes, the silver epoxy is also cured and the conductivity is increased to enable electrical connection in which impedance matching is maintained.
제5도에서는 상기 제2도 및 제3도의 베리드칩기술이 변형된 베리드플립칩(Beried Flip-Chip)기술을 이용한 전송라인접속법이 나타나 있다.FIG. 5 shows a transmission line connection method using a buried flip-chip technology in which the buried chip technology of FIGS. 2 and 3 is modified.
이 배리드플립칩기술은 기존의 배리드칩기술의 응용으로서 평면적인 전송라인구조의 전기적 연결에 유용하게 사용될 수 있다. 이러한 배리드플필칩기술은 상기 배리드칩기술과 달리 소자를 뒤집어서 솔더범퍼에 의해서 두개의 전송라인이 연결되도록 하는 구조이다. 이 방법에서는 칩캐리어(22)만이 마더보더(26)안에 설치되고 소자들은 칩캐리어(22)위에 형성된다.This buried flip chip technology is an application of the conventional buried chip technology, and can be usefully used for the electrical connection of a planar transmission line structure. Unlike the buried chip technology, the buried flip-chip technology has a structure in which two transmission lines are connected by a solder bumper by inverting an element. In this method, only the chip carrier 22 is installed in the motherboard 26 and the elements are formed on the chip carrier 22.
이상과 같은 본 발명에 따른 전송라인접속법이 제공되므로써 임피던스 매칭을 수월하게 이룩하게 되었고, 이에 따라 고속의 신호전달이 가능해지고 전력손실을 최소화하게 된다. 이상에서 서술한 바와 같은 본 발명의 기술적 사상은 본 발명의 요지를 변경하지 않는 범위내에서 당분야에 통상의 지식을 가진 사람이라면 다양하게 변경가능할 것이다.Since the transmission line connection method according to the present invention is provided as described above, impedance matching can be easily achieved, thereby enabling high-speed signal transmission and minimizing power loss. The technical spirit of the present invention as described above may be variously changed by those skilled in the art without changing the gist of the present invention.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950024729A KR0177745B1 (en) | 1995-08-10 | 1995-08-10 | Transmission line interconnection method of semiconductor memory device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950024729A KR0177745B1 (en) | 1995-08-10 | 1995-08-10 | Transmission line interconnection method of semiconductor memory device |
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| Publication Number | Publication Date |
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| KR970013300A KR970013300A (en) | 1997-03-29 |
| KR0177745B1 true KR0177745B1 (en) | 1999-03-20 |
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| KR1019950024729A Expired - Fee Related KR0177745B1 (en) | 1995-08-10 | 1995-08-10 | Transmission line interconnection method of semiconductor memory device |
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