KR0174992B1 - Manufacturing method of semiconductor reticle and manufacturing method of vernier-key - Google Patents

Abstract

A method for manufacturing a vernier-key having a 0.03 μm pitch pattern and a method for manufacturing a reticle for semiconductors used therein.

According to the present invention, a method of performing a data operation on a specific pattern corresponding to each part constituting a reticle using a computer, forming the data of each specific pattern into a pattern on a tape, A method of manufacturing a reticle for a semiconductor comprising the steps of forming the specific patterns on a reticle by performing an electron beam operation, wherein the specific pattern formed on the vernier-key portion is independent of other components of the reticle during the electron beam operation. To reduce the ratio to form a vernier-key having a desired size, and produce a vernier-key having a 0.03 μm pitch pattern through an electron beam operation that reduces the vernier-key data having a 0.05 μm pitch pattern by 60%.

Therefore, the 0.25 μm spot size can be used, making it easy to manufacture the reticle, thereby reducing the cost.

Description

Manufacturing method of semiconductor reticle and manufacturing method of vernier-key

1 is a process flowchart showing a general reticle manufacturing process.

2 is a diagram showing vernier-key data in a conventional vernier-key data operation.

3 is a diagram illustrating vernier-key data when working with vernier-key data according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: pre-step pattern 12,13: post-step pattern

The present invention relates to a method for manufacturing a reticle for semiconductors and a method for manufacturing a vernier-key, and more particularly, to form a vernier-key having a degree of alignment between a pattern formed in a previous step and a pattern formed in a subsequent step during a semiconductor manufacturing process. It relates to a reticle manufacturing method and its vernier-key manufacturing method.

In the semiconductor manufacturing process, a specific circuit is realized by a multilayer film made of an insulating layer and a conductive layer on a wafer, and the most basic is to form a specific pattern on a wafer. In particular, in a photo process using a light source and a pattern transfer mechanism such as a mask or a reticle, a reliable semiconductor circuit may be realized only when the pattern formed in the previous step and the pattern formed in the subsequent step are correctly aligned.

In general, Vernier Key is used to check the degree of alignment between pre and post step patterns in photo process. The vernier-key is formed around the chip of the semiconductor wafer and in a scribe line that is cut and discarded after the wafer process is completed. Since the semiconductor manufacturing process goes through a multi-step pattern formation process, a reticle with a specific pattern is used in each step. A vernier-key is formed in a reticle used in each step, and a vernier-key formed in a previous step is used. The reference key and the vernier-key formed in the later step become the measurement key, and the degree of overlap between the patterns is determined by examining the relative positional relationship of the vernier-key of the later step with respect to the vernier-key of the previous step.

1 is a process flow diagram showing a general reticle manufacturing process. The reticle for performing the semiconductor photo process is basically a main portion, a scribe line portion, a vernier-key portion, and a tag portion used for testing through the same process as the main portion, which is an element active region of a semiconductor chip. It is composed.

Referring to FIG. 1, a data operation of designing a specific circuit pattern is first performed using a computer. The data operation is performed separately for each of the main portion, the scribe line portion, the vernier-key portion, and the tag portion constituting the reticle, and is generally performed in a size of 1: 1 with the pattern formed on the wafer.

Subsequently, as a P / G (Pattern Gerneration) process, data for each part of the reticle is formed in a tape in an actual pattern. In this case, the size of the data pattern is 1: 1.

Subsequently, an electron beam operation is performed based on the pattern formed on the tape to form each specific pattern on the reticle to complete the reticle fabrication. In this case, the pattern is usually enlarged to about 5: 1.

2 is a diagram showing conventional vernier-key data. As semiconductor integrated circuits become more highly integrated, design rules become more stringent, leading to the use of vernier-key pitch patterns reduced from 0.05 µm to 0.03 µm.

Referring to FIG. 2, the rectangular pattern indicated by the dotted line represents the vernier-key data designed by the computer to perform a specific step of the semiconductor manufacturing process, and the all-step pattern in the sense that it is performed before the next step of the process proceeds. It is named (10). In the previous step pattern 10, a plurality of patterns having the same size as the left and right are formed at the center of the reference point (zero point), and the distance between the centers of the unit patterns is constant, for example, 10 μm.

On the other hand, the small rectangular pattern represented by a solid line represents vernier-key data designed by a computer in order to perform another specific step of the semiconductor manufacturing process, in the sense that it is performed after the process of the previous step pattern 10 step is performed. The post-step pattern 12 is called. Like the previous step pattern 10, a plurality of patterns having the same size as the previous step pattern 10 are formed on the basis of the reference point (zero point), and the distance between the centers of the unit patterns is constant. For example, it is formed in 9.97 micrometers.

Therefore, compared with the previous step pattern 10, the 0.03 micrometer pitch pattern which shows the difference of 0.03 micrometer with the distance between the post-step patterns 12 is formed. In order to form a vernier-key having such a 0.03 μm pitch pattern, an electron beam spot size of 0.15 μm should be used.

However, according to the prior art, since the spot size of the electron beam must be used as small as 0.15 μm when forming the vernier-key, the amount of the electron beam is large and the electron beam scanning time is required to form the same size pattern. There is a problem that it becomes a factor of cost increase.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a reticle for a semiconductor that can be easily operated with cost reduction by increasing the spot size of an electron beam in manufacturing a vernier-key of the same size.

Another object of the present invention is to provide a method for manufacturing a vernier-key which can easily produce a vernier-key having the same size even when the spot size of the electron beam is increased.

In the semiconductor reticle manufacturing method of the present invention for achieving the above object, using a computer to perform a data operation for a specific pattern corresponding to the main portion, scribe line portion, vernier-key portion and the tag portion constituting the reticle A method of manufacturing a reticle for a semiconductor comprising the steps of: forming data of each specific pattern into a pattern on a tape; and performing the electron beam operation according to each data pattern to form each specific pattern on a reticle. In the electron beam operation, the specific pattern formed on the vernier-key portion is reduced to a predetermined ratio independently of other components of the reticle to form a vernier-key having a desired size.

The pitch pattern of the vernier-key during the data operation is 0.05 μm, and is reduced by 60% during the electron beam operation to form the vernier-key having a 0.03 μm pitch pattern on the reticle, and the spot size used during the electron beam operation is 0.25. μm may be used.

Vernier-key fabrication method of the present invention for achieving the above object is a manufacturing method of the vernier-key which can confirm the degree of alignment of the pattern formed on the semiconductor wafer by examining the relative positional relationship with respect to the reference key by all steps Performing a vernier-key data operation with a 0.05 μm pitch pattern using a computer, forming a vernier-key pattern on a tape based on the vernier-key data, the spot size being 0.25 μm, 60% Performing a reduced electron beam operation to form a vernier-key with a 0.03 μm pitch pattern on the reticle and transferring the vernier-key on the reticle onto the wafer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 shows vernier-key data in a vernier-key data operation according to an embodiment of the present invention corresponding to FIG. The vernier-key data operation is performed separately from other parts of the reticle.

Referring to FIG. 3, the rectangular pattern indicated by the dotted line represents the vernier-key data designed by the computer to perform a specific step of the semiconductor manufacturing process as shown in FIG. In the previous step pattern 10, a plurality of patterns having the same size as the left and right are formed at the center with a reference point (0 point) at intervals of 10 μm.

On the other hand, the small rectangular pattern shown by the solid line shows the vernier-key data designed by the computer, and is the post step pattern 13 after the process of the said previous step pattern 10 step progressed. Like the previous step pattern 10, a plurality of patterns having the same size as the left and right steps are formed at the center of the reference point (zero point) while maintaining a 9.95 μm spacing. Therefore, compared to the previous step pattern 10, data for a 0.05 μm pitch pattern having a difference of 0.05 μm between the post step patterns 13 is formed.

Subsequently, a P / G (Pattern Gerneration) process of forming the vernier-key data into a tape in an actual pattern is performed, and is generally formed in a size of 1: 1 with the data pattern.

Subsequently, an electron beam operation is performed on the basis of the 0.05 μm pitch pattern formed on the tape to form each vernier-key pattern on the reticle, where other parts constituting the reticle, for example, a main part and a screed, are formed. The reticle fabrication is completed by forming a specific pattern corresponding to the line portion and the tag portion. In this case, the pattern is usually enlarged to about 5: 1.

Meanwhile, in the process of forming the reticle as described above, the vernier-key pattern is separated from other parts to perform electron beam work, and the ratio is reduced by 60%, so that the data for the 0.05 μm pitch pattern is 0.03. It is formed in a μm pitch pattern.

Meanwhile, in the process of forming the vernier-key on the semiconductor wafer, first, the pattern transfer operation is performed on the wafer using a reticle having the previous step pattern 10 in a specific step of the semiconductor wafer process, and then in the specific step. The pattern transfer operation is performed using the reticle having the post-step pattern 13. Therefore, by checking the relative positional relationship between the two vernier-key, it is possible to confirm the degree of overlap of the pattern between the front and rear steps.

Therefore, according to the present invention, since a conventional electron beam having a 0.25 μm spot size is used, reticle fabrication is easy, and when manufacturing a vernier-key having a pitch pattern of 0.03 μm, instead of using a spot size of 0.15 μm, 0.25μm can be used, which can reduce the cost.

Although the present invention has been described in detail only with respect to the described embodiments, it will be apparent to those skilled in the art that various modifications and changes are possible within the technical scope of the present invention, and such modifications and modifications belong to the appended claims.

Claims (4)

Performing a data operation on a specific pattern corresponding to each of the main part, the scribe line part, the vernier-key part, and the tag part constituting the reticle using a computer, and forming the data of the specific pattern in a pattern on a tape And forming the specific pattern on the reticle by performing electron beam operation according to each data pattern, wherein the reticle during electron beam operation is performed for a specific pattern formed on the vernier-key portion. A method of manufacturing a reticle for semiconductors, characterized in that to form a vernier-key of a desired size by reducing the ratio to a ratio independent of other components of the. The method of claim 1, wherein the pitch pattern of the vernier-key during the data operation is set to 0.05μm, 60% reduction in the electron beam operation to form a vernier-key having a 0.03μm pitch pattern on the reticle Reticle manufacturing method for semiconductors. The method of claim 2, wherein the spot size used in the electron beam operation is 0.25 μm. In the vernier-key manufacturing method which can check the alignment degree of the pattern formed on the semiconductor wafer by inspecting the relative positional relationship with respect to the reference key by all steps, the vernier-key data which has a 0.05 micrometer pitch pattern using a computer. Performing a task; Forming a vernier-key pattern on a tape based on the vernier-key data; Performing an electron beam operation with a spot size of 0.25 μm and 60% shrinking to form a vernier-key having a 0.03 μm pitch pattern on the reticle; Transferring the vernier-key on the reticle onto a wafer; Vernier-key manufacturing method characterized in that it comprises a.