KR0174622B1 - Structure of Bipolar Inverter and Manufacturing Method Thereof - Google Patents

Abstract

In fabricating a bipolar inverter on a semiconductor, by forming two PNP transistors and an NPN transistor as one element, the area occupied by the two transistors is reduced, thereby reducing the length of the wiring. As a result, parasitic capacitance and parasitic resistance are reduced, and one elementized inverter provides improved performance in terms of processing speed as compared to a conventional inverter, and it is easy to form a fine pattern due to the miniaturization of a bipolar inverter when forming a fine pattern. Done.

Description

Structure of Bipolar Inverter and Manufacturing Method Thereof

1 is a circuit diagram constituting a general bipolar inverter.

2 is a cross-sectional view of a bipolar inverter according to an embodiment of the present invention.

3A-3H are process diagrams for manufacturing a bipolar inverter by the method of the present invention.

* Explanation of symbols for main parts of the drawings

21: p-type silicon substrate 22, 25, 29: insulating film

23: N + type buried layer 24: P-type epitaxial layer

26: N-type diffusion layer

26-1: N-type diffusion layer for collector of NPN transistor

26-2: N-type diffusion layer for base of PNP transistor

28: P-type diffusion layer

28-1: P-type diffusion layer for base of NPN transistor

28-2: P-type diffusion layer for emitter of PNP transistor

30: N + type diffusion layer 31: trench

32, 34: insulator 33: first conductive metal

35: second conductive metal 36: insulating oxide film

37: electrode terminal 38: third conductive metal material

A: Signal input terminal B: Ground terminal

C: power terminal D: output terminal

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor, and more particularly, to a structure of a bipolar inverter and a method for manufacturing the same. It relates to a manufacturing method.

Recently, with the introduction of multifunctional electronic products one after another, semiconductors require high integration and processing speed, and in order to achieve high integration and high speed of semiconductors, it is essential to reduce the area of devices on the semiconductors.

1 is a circuit diagram of a general bipolar inverter.

Referring to FIG. 1, an inverter for converting and outputting an input signal in reverse phase is composed of a PNP transistor and an NPN transistor, each transistor having different polarities, and connects the base of the PNP transistor and the base of the NPN transistor to a signal input terminal. (A) The emitter of the PNP transistor is used as the signal output terminal (D) by connecting the power supply terminal (C), the emitter of the NPN transistor to the ground terminal (B), and the collector of the PNP transistor and the NPN transistor.

At this time, the PNP transistor is used as a load element of the signal, and the NPN transistor is used as a driver element of the signal.

However, the conventional inverter as described above uses two metal elements and connects them with metal wiring, so that the area occupied by the inverter is large and the signal processing speed is inevitably slow. In addition, there are disadvantages in that parasitic resistances and parasitic capacitances associated with connecting two transistors are generated. In particular, the signal processing speed of the inverter is an important factor in evaluating the performance of the inverter, and is greatly influenced by the product of the inverter's resistance and capacitance. The slow signal processing speed is a fatal defect of the bipolar inverter.

Therefore, the conventional inverter connected by metal wiring after forming the two elements as described above, the area is increased, there is a problem that the signal processing speed is slow.

Disclosure of Invention The present invention has been made in an effort to provide a bipolar inverter and a method of manufacturing the same, which improve the signal processing speed by reducing the area of the device by forming the NPN transistor and the PNP transistor as one device. There is this.

A feature of the present invention for achieving the above object is an N + -type buried layer in a silicon substrate, a P-type epitaxial layer on the N + -type buried layer, an N-type diffused layer in a P-type epitaxial layer, and an N-type diffused layer. A step of sequentially forming a P-type diffusion layer and an N + type diffusion layer in the P-type diffusion layer; Forming a trench in the substrate, whereby an unetched portion is formed in the region of the NPN transistor and the PNP transistor; Etching the trench formed between the two transistors to have a wider width than a lower portion of the trench; After filling the insulator in the trench, etching the insulator in the trench formed between the two transistors at an angle to connect the bases of the two transistors in the trench; A conductive metal material is applied on the insulated etched film in the trench to connect the bases of the two transistors to each other, and after filling the insulator in the trench, the insulator is etched and removed to form the conductive metal material. Process of doing; Coating an insulating oxide film on the surface of the substrate, and performing a terminal wiring step to sequentially form an input terminal, a power supply terminal, and a ground terminal; After polishing the back surface of a board | substrate to a burying layer, it implements terminal wiring and forms an output terminal.

Another aspect of the invention is a transistor in which a NPN transistor and a PNP transistor are respectively formed in a silicon substrate in a silicon substrate, each side of each of the two transistors having a trench filled with an insulator; The NPN transistor includes an N + type buried layer, an N-type diffusion layer serving as a collector region, a P-type diffusion layer serving as a base region, and an N + diffusion layer serving as an emitter region; The PNP transistor is formed with a P-type epitaxial layer, a collector region, an N-type diffusion layer, a base region, and a P-type diffusion layer, an emitter region; A first conductive metal is formed and electrically connected between the base of the NPN transistor and the PNP transistor in the trench between the two transistors; A second conductive metal material is formed on the first conductive metal material and on the surface of the silicon substrate; And a bipolar inverter structure in which a third conductive metal is formed on the back surface of the silicon substrate.

Hereinafter, described in detail according to an embodiment of the present invention with the accompanying drawings as follows.

2 is a cross-sectional view showing the structure of a bipolar inverter manufactured by the method of the present invention.

Referring to FIG. 2, NPN transistors and PNP transistors are formed in the silicon substrate, respectively, and trenches filled with the insulator 32 are formed on both sides of the two transistors.

The NPN transistor includes an N + type buried layer 23, an N-type diffusion layer 26-1 serving as a collector region, a P-type diffusion layer 28-1 serving as a base region, and an N + type diffusion layer 30 serving as an emitter region. It is formed. In the PNP transistor, a P-type epitaxial layer 24 that is a collector region, an N-type diffusion layer 26-2 that is a base region, and a P-type diffusion layer 28-2 that is an emitter region are sequentially formed. have.

In the trench between the two transistors, a first conductive metal material 33 is formed and electrically connected between the base 28-1 and 26-2 of the NPN transistor and the PNP transistor. The second conductive metal material 35 is formed from the upper portion of the metal material 33 to the surface of the silicon substrate.

A third conductive metal material 38 is formed on the entire surface of the back surface of the silicon substrate, and a patterned insulating oxide film 36 is formed on the front surface of the substrate, and between the contacts of the patterned insulating oxide film 36 and the substrate. A metal terminal (B) (A) (C) is formed on the rear surface of the NPN transistor. The ground terminal (B) is disposed above the emitter region (30) of the NPN transistor, and the input terminal (A) is located above the second conductive metal material (35). ), The power supply terminal C is formed on the emitter region 28-2 of the PNP transistor, and the output terminal D is formed on the third conductive metal material 38, respectively.

3A to 3H are process drawings for manufacturing a bipolar inverter according to the present invention.

Referring to FIG. 3A, an insulating film 22 is formed on the entire surface of the silicon substrate 21 into which the P-type impurity is implanted. Then, after patterning, N + type impurity ions are implanted using the insulating film 22 as a mask. An N + type buried layer 23 having a low resistance is formed.

As shown in FIG. 3B, the P-type epitaxial layer 24 is thickly grown on the silicon plate 21 removed by etching the insulating film. Referring to FIG. 3C, the insulating film is formed on the entire surface of the silicon substrate 21. An N-type diffusion layer 26 is formed by forming and patterning 35 and injecting N-type impurity ions using the patterned insulating film 25 as a mask.

Referring to FIG. 3D, a P-type diffusion layer 28 is formed by injecting P-type impurity ions using the insulating film 25 as a mask, and as shown in FIG. 3E, the insulating film 25 is removed, and then impurities An insulating film 29 for ion implantation is formed and patterned, and after implanting N + type impurity ions using the insulating film 29 as a mask, a diffusion process is performed to form an N + type diffusion layer 30. Here, the N-type diffusion layer 26 becomes the collector of the NPN transistor and the base of the PNP transistor, the P-type diffusion layer 28 becomes the base of the NPN transistor and the emitter of the PNP transistor, and the N + type diffusion layer 30 It becomes the emitter of the NPN transistor.

As shown in FIG. 3F, the N-type impurity material layer 23 is selectively etched and removed through a predetermined etching process to form trenches 31-1, 31-2 and 31-3, which are devices. In order to prevent leakage current between semiconductor devices by forming an isolation region, an unetched impurity region in the substrate 21 is divided into an NPN transistor and a PNP transistor region.

In other words, the portion composed of the N + type buried layer 23, the N-type diffusion layer 26-1, the P-type diffusion layer 28-1, and the N + type diffusion layer 30 becomes an NPN transistor region, and the N + type diffusion layer. Numeral 30 denotes an emitter of the NPN transistor, N-type diffusion layer 26-1 becomes a collector of NPN transistor, and P-type diffusion layer 28-1 becomes a base of NPN transistor. The portion composed of the P-type diffusion layer 28-2, the N-type diffusion layer 26-2, and the P-type epitaxial layer 24 becomes a PNP transistor region, and the P-type diffusion layer 28-2 is provided. The emitter of the PNP transistor, the N-type diffusion layer 26-2 are the base of the PNP transistor, and the P-type epitaxial layer 24 is the collector of the PNP transistor.

Subsequently, referring to FIG. 3G, the NPN transistor and the PNP transistor are electrically isolated by filling the insulator 32 in the trenches 31-1, 31-2, and 31-3 formed as described above.

In addition, the inlet of the trench 31-2 formed between the two transistors is etched to have a width wider than the bottom of the trench 31-2, to widen the width of the base terminal of the transistor.

Subsequently, the insulator 32 in the trench 31-2 between the two transistors is etched in the inclined direction so that the base 28-1 and 26-2 of the NPN transistor and the PNP transistor can be connected.

Etching the insulator 32 in an inclined direction is accomplished by an oblique viewing method commonly used in the art. That is, while only a part of the surface of the insulator 32 is exposed, the sputter etching is inclined with respect to the surface of the substrate 21 to etch a part of the insulator 32, and then the entire upper surface of the insulator 32 is exposed. When sputter etching perpendicular to the surface of the substrate 21 in the state, as shown in FIG. 3g, the surface of the insulator 32 is inclined. At this time, by controlling the etching time of the insulator 32, the base 28-1 and 26-2 of the NPN transistor and the PNP transistor are exposed.

In addition, during the vertical sputter etching, the base terminals of both transistors are widened by etching the openings of the trench 31-2.

As described above, the first conductive metal material 33 is filled on the insulator 32 etched in the inclined direction, the insulating material 34 is filled on the first conductive metal material 33, and then anisotropic etching is selectively performed. As a result, a part of the insulating film 34 is removed up to the first conductive metal material 33, and the second conductive metal material 35 is filled in the removed portion.

Subsequently, an oxide film 36 for insulation is coated on the entire surface of the substrate, and then patterned. Then, a terminal wiring process is performed to form a gate input terminal A, a ground terminal B, and a power supply terminal C in this order. .

Finally, the back surface of the substrate is polished to remove the N + type buried layer 23, and then the third conductive metal material 38 is formed on this surface to form an output terminal D for outputting a signal. This completes one elementized inverter (FIG. 2).

According to the present invention as described above, by forming two transistors as one element, the parasitic resistance and parasitic capacitance between the metal oxide film and the silicon film to connect the two conventional devices is reduced, and the two conventional transistors By reducing the space occupied and thus the wiring length, the processing speed of the inverter can be improved.

Claims (3)

In manufacturing a bipolar inverter composed of an NPN transistor and a PNP transistor, a step of forming an N-type buckled layer 23 on the P-type substrate 21 and growing the P-type epitaxial layer 24 thereon, and N Forming an N-type diffusion layer 26 so as to contact the type buckling layer 23, and forming a P-type diffusion layer 28 inside the N-type diffusion layer 26; Forming a high concentration of the N-type diffusion layer 30 inside the P-type diffusion layer 28 and trenches 31-1, 31-2 and 31-3 in the substrate 21 in which impurities are formed as described above. And the impurity regions that remain unetched by forming the trenches 31-1, 31-2 and 31-3, and are divided into NPN transistors and PNP transistor regions, and trenches 31-1. The process of filling the insulator 32 in (31-2) and (31-3), and the base region 28-1 (26-2) of a PNP transistor and an NPN transistor in the trench 31-2 using a conductive metal. Method of manufacturing a bipolar inverter comprising a step for connecting by. The process of claim 1, wherein the process of connecting the NPN transistors and the base regions 28-1 and 26-2 of the PNP transistor is etched such that the insulator 32 filled in the trench 31-2 is inclined. A gate terminal to be etched until the sidewalls of the base regions 28-1 and 26-2 of the NPN transistor and the PNP transistor are exposed, and inclinedly etched in a direction widening the inlet of the trench 31-2. The process of widening the width of the junction and connecting the base regions 28-1 and 26-2 of the NPN transistor and the PNP transistor formed as described above with the first conductive metal material 33 inside the trench 31-2. Filling the insulator 32 in the trench 31-2 as described above, selectively etching a part of the insulator 32 to the first metal material 33, and The bipolar inverter, characterized in that the step of forming a conductive metal material 35 Article methods. Trenches 31-1, 31-2 and 31-3 formed in the silicon substrate, an N + type buried layer 23 sequentially formed in the substrate between neighboring trenches, and an N-type diffusion layer for collectors of NPN transistors ( 26-1), P-type diffusion layer 28-1 for emitters, N + type diffusion layer 30 for emitters, and P-type epitaxial layer 24 for collectors of PNP transistors sequentially formed in a substrate between neighboring trenches. ), The base N-type diffusion layer 26-2, the emitter P-type diffusion layer 28-2, and the base 28-1 of the NPN transistor and the PNP transistor formed in the trench between the two transistors described above. A first conductive metal material 33 for connecting the 26-2, and a second conductive metal material formed over the first conductive metal material 33 in the trench 31-2 and the surface of the silicon substrate; 35, an insulating film 32 formed in the trench 31-2 except for the first and second conductive metal materials 33 and 35, and a front surface of the silicon substrate. An N + type diffusion layer 30 for emitters of the NPN transistors on the substrate between the formed third conductive metal material 38, the insulating oxide film 36 formed on the front surface of the substrate, and the insulating oxide film 36; A ground terminal B and an input terminal A formed to be electrically connected to the second conductive metal material 35, the P-type diffusion layer 28-2 for the emitter of the PNP transistor, and the third conductive metal material 38, respectively. ), A power supply terminal (C) and an output terminal (D) are formed, respectively.