[go: up one dir, main page]

KR0172547B1 - Method of forming fine contact hole in semiconductor device - Google Patents

Method of forming fine contact hole in semiconductor device Download PDF

Info

Publication number
KR0172547B1
KR0172547B1 KR1019950066046A KR19950066046A KR0172547B1 KR 0172547 B1 KR0172547 B1 KR 0172547B1 KR 1019950066046 A KR1019950066046 A KR 1019950066046A KR 19950066046 A KR19950066046 A KR 19950066046A KR 0172547 B1 KR0172547 B1 KR 0172547B1
Authority
KR
South Korea
Prior art keywords
contact
forming
mask
contact hole
semiconductor device
Prior art date
Application number
KR1019950066046A
Other languages
Korean (ko)
Other versions
KR970052457A (en
Inventor
이병렬
김정
Original Assignee
김주용
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업주식회사 filed Critical 김주용
Priority to KR1019950066046A priority Critical patent/KR0172547B1/en
Publication of KR970052457A publication Critical patent/KR970052457A/en
Application granted granted Critical
Publication of KR0172547B1 publication Critical patent/KR0172547B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 미세 콘택홀 형성방법에 관한 것으로, 콘택 마스크를 종래의 주콘택 마스크 외측둘레로 링형패턴을 첨가시킨 형태로 함으로써 콘택 형성을 위한 하부 감광막 패턴 형성시 빛의 간섭에 의해 그 측벽이 경사지도록 하여 콘택홀 식각시 공정마진을 증가시킴과 아울러, 미세콘택홀 형성을 용이하게 할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fine contact hole in a semiconductor device. The contact mask is formed by adding a ring-shaped pattern around the outer side of a conventional main contact mask. By making the inclination increase, the process margin may be increased during the etching of the contact hole, and the formation of the fine contact hole may be facilitated.

Description

반도체 소자의 미세콘택홀 형성방법Method for forming micro contact hole in semiconductor device

제1a도는 일반적인 콘택 마스크의 레이아웃도.1A is a layout diagram of a general contact mask.

제1b도는 제1a도의 A-A선에 따른 단면도.FIG. 1B is a cross-sectional view taken along the line A-A of FIG. 1A.

제2a도는 본 발명에 따른 콘택 마스크의 레이아웃도.2A is a layout diagram of a contact mask according to the present invention.

제2b도는 제2a도의 B-B선에 따른 단면도.FIG. 2B is a cross sectional view along line B-B in FIG. 2A;

제2c도는 식각에 의해 콘택홀을 형성한 상태의 단면도.2C is a cross-sectional view of a state in which a contact hole is formed by etching.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘 기판 2 : 필드 산화막1: silicon substrate 2: field oxide film

3 : 활성 영역 4 : 층간 절연막3: active region 4: interlayer insulating film

5 : 감광막 11 : 액티브 마스크5: photosensitive film 11: active mask

12, 13 : 콘택 마스크 12a : 주콘택 마스크12, 13: contact mask 12a: main contact mask

12b : 링형패턴12b: ring pattern

본 발명은 반도체 소자의 미세 콘택홀 형성방법에 관한 것으로, 특히 콘택 마스크를 종래의 주콘택 마스크 외측둘레로 링(Ring)형 패턴을 추가시켜 빛의 간섭이 생기도록 함으로써 마스크 작업시 형성되는 감광막 패턴의 측벽이 경사지도록 하여 콘택홀 식각에 따른 공정마진을 증가시키며 미세콘택홀의 형성을 용이하게 하는 반도체 소자의 미세콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fine contact hole in a semiconductor device. In particular, a photoresist pattern formed during a mask operation by adding a ring pattern around the outside of a conventional main contact mask to generate interference of light The present invention relates to a method for forming a micro contact hole in a semiconductor device, which makes the sidewalls of the semiconductor substrate be inclined to increase process margins due to contact hole etching and to facilitate formation of fine contact holes.

반도체 소자의 고집적화에 따라 상하 배선을 연결하는 콘택의 크기가 감소되며, 콘택홀의 지름과 깊이의 비인 에스팩트비(aspect ratio)가 증가하게된다.As the semiconductor device is highly integrated, the size of the contact connecting the upper and lower wirings is reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, is increased.

따라서 다층 도전선을 구비하는 반도체 소자에서 콘택홀을 형성하기 위해서는 제조공정에서의 정확하고 엄격한 정렬이 요구된다. 또한 콘택홀 크기의 감소는 반도체 제조장비의 고정밀성을 요구하게 되며 0.4㎛이하의 미세패턴의 형성은 매우 어렵다. 이를 극복하기 위한 것으로 위상반전마스크(Phase Shift Mask; 이하 PSM 마스크라 칭함.)를 사용하는 것이 채택되고 있으나 상기 PSM마스크는 가격이 매우 고가이므로 제조원가 상승의 요인이 되는 문제점이 있다.Therefore, in order to form contact holes in a semiconductor device having a multi-layer conductive line, accurate and strict alignment in a manufacturing process is required. In addition, the reduction of the contact hole size requires high precision of semiconductor manufacturing equipment, and it is very difficult to form a fine pattern of 0.4 μm or less. In order to overcome this problem, a phase shift mask (hereinafter referred to as a PSM mask) has been adopted. However, since the price of the PSM mask is very high, there is a problem that the manufacturing cost increases.

따라서 본 발명은 상기의 문제점을 해결하기 위한 것으로, 본 발명은 상기 PSM마스크를 사용하지 않고 보통의 콘택 마스크에 링형의 패턴을 첨가시켜 마스크 작업시 빛의 간섭이 생기도록 함으로써 감광막의 패턴이 경사지도록하여 에스팩트비를 감소시켜 식각작업이 용이하도록 하는 반도체 소자의 미세콘택홀 제조방법을 제공함에 그 목적이 있다.Therefore, the present invention is to solve the above problems, the present invention is to add a ring-shaped pattern to the normal contact mask without using the PSM mask so that the interference of light occurs during the mask operation so that the pattern of the photoresist film is inclined The purpose of the present invention is to provide a method for manufacturing a micro contact hole of a semiconductor device to reduce the aspect ratio to facilitate etching.

상기 목적을 달성하기 위한 본 발명은 반도체 기판상의 예정된 위치에 소자 분리를 위한 필드 산화막을 형성하는 단계와, 반도체 기판상에 활성영역을 위한 불순물을 주입하는 단계와, 전체구조 상부에 소정두께의 감광막을 형성하는 단계와, 콘택 마스크를 사용하여 하부의 감광막을 노광 및 현상하여 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 이용하여 하부절연막을 식각하여 콘택홀을 형성하는 단계와, 감광막을 제거하는 단계를 구비하는 콘택홀 형성방법에 있어서, 상기 감광막 패턴 형성을 위한 콘택 마스크로 주콘택 마스크 외측둘레로 링형 패턴을 첨가시킨 형태로 함으로써 마스크 작업시 빛의 간섭이 생겨 감광막 패턴의 측벽면이 일정각도 경사지게 형성되도록 한 것을 특징으로 한다.The present invention for achieving the above object is to form a field oxide film for device isolation at a predetermined position on the semiconductor substrate, injecting impurities for the active region on the semiconductor substrate, a photoresist film of a predetermined thickness on the entire structure Forming a photoresist pattern by exposing and developing a lower photoresist film using a contact mask; forming a contact hole by etching a lower insulating film using the photoresist pattern; and removing the photoresist film. In the contact hole forming method comprising the step of forming a ring-shaped pattern around the outer side of the main contact mask as a contact mask for forming the photoresist pattern, light interference occurs during the mask operation, so that the sidewall surface of the photoresist pattern is at an angle. Characterized in that it is formed to be inclined.

이하 본 발명에 따른 반도체 소자의 미세콘택홀 형성 방법에 관하여 첨부도면을 참조하여 상세히 설명한다.Hereinafter, a method for forming a micro contact hole of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

제1a도와 제1b도는 종래의 사용하고 있는 반도체소자의 콘택 레이아웃도와 마스크 작업시 감광막 패턴 형성후의 감광막의 프로파일을 도시한 도면이다.1A and 1B show a contact layout diagram of a semiconductor device that is conventionally used and a profile of the photoresist film after formation of the photoresist pattern during masking.

상기 제1a도와 제1b도를 참조하면, 반도체 기판(1)상에 소자 분리를 위한 필드 산화막(2)을 형성한 후 활성영역(3)을 위한 불순물을 임플란테이션(implantation)을 통해 주입된다.Referring to FIGS. 1A and 1B, after forming a field oxide film 2 for device isolation on a semiconductor substrate 1, impurities for the active region 3 are implanted through implantation. .

다음, 전체구조 상부에 층간 절연막(4)을 화학기상 증착법으로 증착한후, 활성영역(3)중 원하는 부위에 상하 배선을 형성하기 위한 콘택 마스크(12)를 위치시킨다.Next, after the interlayer insulating film 4 is deposited on the entire structure by chemical vapor deposition, the contact mask 12 for forming the upper and lower wirings is positioned at a desired portion of the active region 3.

이때, 상기 종래의 사용되는 콘택 마스크(12)는 사각형상의 마스크로서, 상기 종래의 마스크(12)를 사용하여 층간절연막(4)을 식각하여 콘택홀을 형성할 경우, 콘택홀의 측벽이 수직인 형상으로 형성되어 크기가 미세한 콘택홀 형성시에는 콘택홀 형성에 따른 한계가 따르게 된다.In this case, the conventionally used contact mask 12 is a rectangular mask, and when the interlayer insulating layer 4 is etched using the conventional mask 12 to form a contact hole, the sidewall of the contact hole is vertical. In the case of forming a contact hole having a small size, the limit of contact hole formation is followed.

제2a도와 제2b도는 본 발명에 따른 반도체 소자의 콘택홀 제조 방법을 도시한 도면으로서, 제2a도는 콘택홀 형성을 위한 레이아웃도이고, 제2b도는 마스크 작업후 감광막 패턴의 단면 프로파일을 도시한 도면이다.2a and 2b illustrate a method for manufacturing a contact hole in a semiconductor device according to the present invention, and FIG. 2a illustrates a layout for forming a contact hole, and FIG. 2b illustrates a cross-sectional profile of a photoresist pattern after masking. to be.

상기 제2a도와 제2b도를 참조하여 본 발명의 방법에 따른 콘택홀 형성공정단계를 살펴보기로 한다.A process for forming a contact hole according to the method of the present invention will be described with reference to FIGS. 2a and 2b.

먼저, 반도체 기판(1)상에 소자 분리를 위한 필드 산화막(2)을 형성한 후 활성영역(3)을 위한 불순물을 임플란테이션 통해 주입한다.First, after forming a field oxide film 2 for device isolation on the semiconductor substrate 1, impurities for the active region 3 are implanted through implantation.

다음 전체구조 상부에 층간 절연막(4)을 화학기상 증착법으로 증착한 다음, 원하는 활성영역(3)상에 상하 배선을 형성하기 위한 콘택 마스크(13)을 사용하여 감광막을 노출시킨다.Next, the interlayer insulating film 4 is deposited on the entire structure by chemical vapor deposition, and then the photoresist film is exposed using the contact mask 13 for forming the upper and lower wirings on the desired active region 3.

이때, 상기 본 발명의 콘택 마스크(13)는 종래의 주콘택 마스크(12a)의 외측둘레로 내부가 비어있는 링형패턴(12b)을 첨가시킨 형태로서, 종래의 주콘택 마스크(12a)와 링형패턴(12b)과의 사이가 일정간격이 이격되어 마스크 작업시 빛의 간섭이 생기도록 한다.In this case, the contact mask 13 of the present invention is a form in which a ring-shaped pattern 12b having an empty inside is added to the outer circumference of the conventional main contact mask 12a, and the conventional main contact mask 12a and the ring-shaped pattern are added. There is a certain interval between (12b) and the interference of light during the mask operation.

이때, 상기 주콘택 마스크(12a)와 링형패턴(12b) 사이의 간격은 적정 거리로 조정가능한 구조로 형성하고, 이와 동시에 주콘택 마스크(12a)의 외측둘레에 구비되는 링형패턴(12b)의 수는 2개~4개 범위에서 적절하게 추가시켜 사용할 수 있게한다.At this time, the interval between the main contact mask 12a and the ring-shaped pattern 12b is formed in a structure that can be adjusted to an appropriate distance, and at the same time the number of the ring-shaped pattern 12b provided on the outer periphery of the main contact mask 12a Can be used in the range of 2 to 4 as appropriate.

따라서 빛의 간섭을 발생시키는 콘택 마스크(13)를 사용함에 의해 절연층(1)상부에 형성된 감광막 패턴(6)은 그 측벽면(7)이 일정각도 경사지게 형성되어 감광막 패턴(6)의 에스펙트비를 감소시키게 된다.Therefore, the photoresist pattern 6 formed on the insulating layer 1 by the use of the contact mask 13 generating the interference of light has its sidewall surface 7 formed to be inclined at an angle, so that the aspect of the photoresist pattern 6 is reduced. Will reduce rain.

상기와 같이 측벽면(7)이 경사진 감광막 패턴(6)을 이용하여 하부 층간 절연막(4)을 식각한 상태를 제2c도에 도시하였다.2C shows a state where the lower interlayer insulating film 4 is etched using the photosensitive film pattern 6 in which the sidewall surface 7 is inclined as described above.

상기 제2c도에 도시한 바와같이, 측벽면(7)이 경사져 있는 감광막 패턴(6)을 이용하여 하부 절연층(4)을 식각할 경우 그 식각을 보다 용이하게 하고 이에 따라 형성되는 콘택홀(8)의 측벽면도 경사지게 되어 에스펙트비가 감소하여 콘택홀 매립이 또한 용이하게 이뤄지게 된다.As illustrated in FIG. 2C, when the lower insulating layer 4 is etched using the photosensitive film pattern 6 having the sidewall surface 7 inclined, the contact hole is formed more easily and thus formed. The side wall surface of 8) is also inclined so that the aspect ratio is reduced so that contact hole filling is also easily achieved.

결국, 상기와 같이 측벽면이 경사진 콘택홀을 형성함으로써 콘택홀 매립공정을 용이하게 하고 공정마진의 증가 및 반도체 소자 제조의 수율 및 신뢰성 향상 및 고집적화에 유리한 이점이 있다.As a result, as described above, by forming a contact hole having an inclined sidewall surface, the contact hole filling process may be facilitated, and process margins may be increased, and yield and reliability of semiconductor device manufacturing may be improved, and high integration may be advantageous.

한편, 상기 본 발명에 따른 콘택 마스크(13)는 반도체 소자의 금속배선을 위한 콘택 형성시 뿐만 아니라, 메모리 셀의 비트라인 콘택 및 스토리지노드 콘택을 각각 형성할 시 적용될 수 있으며, 또한 메모리셀의 비트라인 콘택 및 스토리지노드 콘택을 동시에 형성할 경우에도 적용될 수 있다.Meanwhile, the contact mask 13 according to the present invention may be applied not only when forming a contact for metal wiring of a semiconductor device but also when forming a bit line contact and a storage node contact of a memory cell. The same applies to the case where the line contact and the storage node contact are simultaneously formed.

이상 상술한 바와 같이 본 발명에 따른 반도체 소자의 미세콘택홀 형성방법에 있어서는, 종래의 콘택 마스크의 외측둘레로 링형 패턴을 첨가시킨 콘택 마스크를 사용하여 하부 감광막 패턴 형성시 빛의 간섭으로 인해 감광막 패턴의 측벽이 경사지게 하여 콘택홀 식각을 위한 공정마진을 증가시킬 뿐만 아니라, 상기 감광막 패턴으로 하부 절연층을 식각하여 형성된 콘택홀의 측벽면도 경사지도록 함으로써 콘택홀의 에스팩트비가 감소되도록 하고 층간배선을 위한 도체의 매립이 용이하게 되도록 함으로써 반도체 소자 제조공정수율 및 신뢰성을 향상시킨다.As described above, in the method for forming a micro contact hole of the semiconductor device according to the present invention, the photoresist pattern is formed due to the interference of light when the lower photoresist pattern is formed by using a contact mask in which a ring-shaped pattern is added around the outside of the conventional contact mask. In addition to increasing the process margin for contact hole etching by inclining the side wall of the contact hole, the sidewall surface of the contact hole formed by etching the lower insulating layer with the photosensitive film pattern is also inclined so that the aspect ratio of the contact hole is reduced and the conductor for interlayer wiring is reduced. By making the embedding easy, the semiconductor device manufacturing process yield and reliability are improved.

Claims (6)

반도체 기판상의 예정된 위치에 소자 분리를 위한 필드 산화막을 형성하는 단계와, 반도체 기판상에 활성영역을 위한 불순물을 주입하는 단계와, 전체구조 상부에 층간 절연막을 형성하는 단계와, 전체구조 상부에 소정두께의 감광막을 형성하는 단계와, 콘택 마스크를 사용하여 하부의 감광막을 노광 및 현상하여 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 이용하여 하부절연막을 식각하여 콘택홀을 형성하는 단계와, 감광막을 제거하는 단계를 구비하는 콘택홀 형성방법에 있어서, 상기 감광막 패턴 형성을 위한 콘택 마스크로 콘택 마스크 외측둘레로 링형 패턴을 첨가시킨 형태의 마스크를 사용하여 마스크 작업시 빛의 간섭이 생겨 감광막 패턴의 측벽면이 일정각도 경사지게 형성되도록한 것을 특징으로 하는 반도체 소자의 미세콘택홀 형성방법.Forming a field oxide film for device isolation at a predetermined position on the semiconductor substrate, implanting an impurity for an active region on the semiconductor substrate, forming an interlayer insulating film over the entire structure, and forming a predetermined upper portion over the entire structure Forming a photoresist layer having a thickness, exposing and developing a lower photoresist layer using a contact mask to form a photoresist pattern, and etching a lower insulating layer using the photoresist pattern to form contact holes; In the method for forming a contact hole comprising the step of removing the photoresist pattern, using a mask of the form in which a ring-shaped pattern is added around the outer side of the contact mask as a contact mask for forming the photoresist pattern, the light interference occurs during the mask operation The micro contact hole of the semiconductor device, characterized in that the side wall surface is formed to be inclined at a predetermined angle Formation method. 제1항에 있어서, 상기 콘택 마스크는 메모리 셀의 비트라인 콘택 및 스토리지노드 콘택을 각각 형성할 시 적용되는 것을 특징으로 하는 반도체 소자의 미세콘택홀 형성방법.The method of claim 1, wherein the contact mask is applied to each of forming a bit line contact and a storage node contact of a memory cell. 제1항에 있어서, 상기 콘택 마스크는 메모리셀의 비트라인 콘택 및 스토리지노드 콘택을 동시에 형성할 시 적용되는 것을 특징으로 하는 반도체 소자의 미세 콘택홀 형성방법.The method of claim 1, wherein the contact mask is applied when simultaneously forming a bit line contact and a storage node contact of a memory cell. 제1항에 있어서, 상기 콘택 마스크는 반도체 소자의 금속배선을 위한 콘택홀 형성시 적용되는 것을 특징으로 하는 반도체 소자의 미세콘택홀 형성방법.The method of claim 1, wherein the contact mask is applied when forming a contact hole for metal wiring of the semiconductor device. 제1항에 있어서, 상기 콘택 마스크의 외측둘레에 구비되는 링형 패턴의 수는 2개~4개인 것을 특징으로 하는 반도체 소자의 미세콘택홀 형성방법.The method of claim 1, wherein the number of ring-shaped patterns provided on the outer circumference of the contact mask is two to four. 제1항에 있어서, 상기 주 콘택 마스크와 링형패턴 사이의 간격은 적정간격으로 조절할 수 있도록 구비된 것을 특징으로 하는 반도체 소자의 미세콘택홀 형성방법.The method of claim 1, wherein an interval between the main contact mask and the ring-shaped pattern is adjusted to be appropriately spaced apart.
KR1019950066046A 1995-12-29 1995-12-29 Method of forming fine contact hole in semiconductor device KR0172547B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950066046A KR0172547B1 (en) 1995-12-29 1995-12-29 Method of forming fine contact hole in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950066046A KR0172547B1 (en) 1995-12-29 1995-12-29 Method of forming fine contact hole in semiconductor device

Publications (2)

Publication Number Publication Date
KR970052457A KR970052457A (en) 1997-07-29
KR0172547B1 true KR0172547B1 (en) 1999-03-30

Family

ID=19447218

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950066046A KR0172547B1 (en) 1995-12-29 1995-12-29 Method of forming fine contact hole in semiconductor device

Country Status (1)

Country Link
KR (1) KR0172547B1 (en)

Also Published As

Publication number Publication date
KR970052457A (en) 1997-07-29

Similar Documents

Publication Publication Date Title
US6071799A (en) Method of forming a contact of a semiconductor device
US5879838A (en) Contact mask having guard ring patterns for manufacturing a semiconductor device
KR970013365A (en) Semiconductor device and manufacturing method thereof
KR20100030125A (en) Photo key and fabrication method of semiconductor device using the same
KR100368569B1 (en) Semiconductor device and its manufacturing method
JPH1092935A (en) Contact of semiconductor device and manufacture thereof
KR0172547B1 (en) Method of forming fine contact hole in semiconductor device
KR100256057B1 (en) Manufacturing Method of Semiconductor Device for Bit Line Capping of Ultra Fine Line Width
KR100384876B1 (en) Improved dual damascene process in semiconductor device
KR100228352B1 (en) Process for fabricating semiconductor device
KR100505414B1 (en) method for forming align key
KR0137566B1 (en) Contact hole formation method of semiconductor device
KR100338107B1 (en) Manufacturing method of semiconductor device
KR100340852B1 (en) Method for fabricating multi metal interconnection of semiconductor device
KR970007821B1 (en) Contact manufacturing method of semiconductor device
KR100401535B1 (en) Manufacturing Method of Analog Semiconductor Device
KR0167607B1 (en) Rom gate electrode manufacturing method
US20020177085A1 (en) Self-aligned photolithographic process for forming silicon-on-insulator devices
KR100808557B1 (en) MM capacitor formation method
KR0158903B1 (en) Gate electrode contact of semiconductor device and manufacturing method thereof
KR100244791B1 (en) Method for manufacturing contact hole of semiconductor device
KR0146247B1 (en) Method for manufacturing semiconductor device
KR20000007539A (en) Manufacturing Method of Semiconductor Device
JP2897350B2 (en) Method for manufacturing semiconductor device
KR0166488B1 (en) Microcontact Formation Method of Semiconductor Device

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19951229

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19951229

Comment text: Request for Examination of Application

PG1501 Laying open of application
E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 19980925

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 19981024

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 19981024

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20010918

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20020918

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20030919

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20040920

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 20050922

Start annual number: 8

End annual number: 8

PR1001 Payment of annual fee

Payment date: 20060920

Start annual number: 9

End annual number: 9

PR1001 Payment of annual fee

Payment date: 20070914

Start annual number: 10

End annual number: 10

PR1001 Payment of annual fee

Payment date: 20081006

Start annual number: 11

End annual number: 11

PR1001 Payment of annual fee

Payment date: 20090922

Start annual number: 12

End annual number: 12

FPAY Annual fee payment

Payment date: 20100920

Year of fee payment: 13

PR1001 Payment of annual fee

Payment date: 20100920

Start annual number: 13

End annual number: 13

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

Termination category: Default of registration fee

Termination date: 20120909