KR0169002B1 - Address generation circuit of video signal processing device - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

An address generating circuit of a video signal processing apparatus.

2. The technical problem to be solved by the invention

Allows processing of image data in various forms.

3. Summary of Solution to Invention

The address generation circuit of the image signal processing apparatus includes an index register section for storing respective start addresses in an area of an external memory, an address for storing unrestored image data in the external memory and reading stored image data from the memory. A motion compensation processor for generating an input signal processor, information about a reference address used for motion compensation, and an address for writing motion compensation-completed image data to the external memory, and a screen according to the restored video data. A generation display processing unit, a multiplexer which multiplexes each address generated from the input signal processing unit, the motion compensation processing unit and the display processing unit according to an applied selection signal, and the multiplexing address for reading data to be displayed on the display; Receiving the selected address output from it will be characterized by having a final address and a memory interface for generating memory control signals for read and write the image data to the external memory.

4. Important uses of the invention

Used in the field of image data processing.

Description

Address generation circuit of video signal processing device

1 is a circuit diagram of a conventional video signal difference block.

2 is a block diagram of an address generation circuit according to the present invention.

3 through 11 are views according to one embodiment of FIG.

The present invention relates to an image signal processing apparatus, and more particularly, to a memory address generation circuit for storing and restoring an image signal.

In general, an image signal processing apparatus digitalizes an applied image signal, stores it in a memory, processes the stored data in various forms, and displays the same on a screen.

In the conventional video signal processing apparatus, a block for processing a video signal is configured as shown in FIG. Referring to FIG. 1, a signal processor 2 for processing an applied image signal, a microcontroller 4 connected to the signal processor 2 and controlling overall signal processing, and an external device in response to an address applied from the microcontroller 4 The memory interface 6 for interfacing image data input and output between the memory 20 and the signal processor 2 constitutes the block 10.

The image signal processing block configured as shown in FIG. 1 stores the image data in the external memory 20 through the memory interface 6 and then stores the stored data in the external memory 20 through the memory interface 6 to restore the image signal. Read and process the stored data. The microcontroller 4 receives reference data from the signal processor 2 to generate a control signal and an address. The memory interface 6 provides a final address and various memory control signals to the external memory 20 in response to the address.

However, the conventional circuit described above has to embed a ROM memory in the microcontroller 4 and write a program for signal recovery in the ROM memory. Therefore, since data processing is performed once according to a predetermined program, there is a problem that the ROM memory needs to be replaced when a separate high-speed circuit for controlling the entire system is interlocked.

As such, in the related art, the processing of the image data for restoring the image signal is entirely dependent on the microcontroller. Therefore, the cumbersome problem of necessitating a mall memory and a program process and replacing the ROM memory when the high speed circuit is interlocked, and the operation of the circuit accordingly. There was a limit to scalability.

Accordingly, an object of the present invention is to provide an image signal processing apparatus capable of solving the above-mentioned conventional problems.

Another object of the present invention is to provide an address generating circuit of an image signal processing apparatus which enables processing of image data in various forms.

It is still another object of the present invention to provide a circuit capable of storing and restoring image data without processing the image data depending on the program of the ROM memory.

According to the present invention for achieving the above object, an address generating circuit of an image signal processing apparatus includes an index register section for storing respective start addresses in an area of an external memory, and stores unrestored image data in the external memory. An input signal processor that generates an address for reading stored image data from the memory, and generates information on a reference address used for motion compensation, and generates an address for writing image data of which motion compensation is completed to the external memory. A display processor for generating a motion compensation processor, an address for reading data to be displayed on the screen according to the restored image data, and a respective address generated from the input signal processor, the motion compensation processor, and the display processor. On select signal Receiving La multiplexed with a multiplexer, the selected address is output from the multiplexer which will be characterized by having a final address and a memory interface for generating memory control signals for read and write the image data to the external memory.

Hereinafter, a circuit according to a preferred embodiment of the present invention will be described with the accompanying drawings. Like reference numerals in the accompanying drawings indicate that the same configuration and function as possible. In the following statement, the detailed items of such construction are described in detail to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In addition, well-known features of the basic elements of the image signal processing apparatus and configurations of known circuit blocks are not described in detail in order not to obscure the present invention.

First, FIG. 2 shows an overall block diagram of the circuit according to the invention. The index register 25 composed of a plurality of address sections 19, 21-23 is responsible for storing respective start addresses for the maps of the external memory 20, as shown in FIG. The input signal processor 30 generates an address for storing unrestored image data in the external memory 20 and reading stored image data from the memory 20. The motion compensation processor 40 generates information on a reference address used for motion compensation, and generates an address for writing image data of which motion compensation is completed to the external memory 20. The display processor 50 generates an address for reading data to be displayed on the screen according to the restored image data. The addresses generated from the input signal processor 30, the motion compensation processor 40, and the display processor 50 are applied to the multiplexers 60, 61, and 62, respectively. The multiplexers 60, 61, and 62 provide one of three inputs to the memory interface 70 according to the selection signal applied. The memory interface 70 receives the selected address and generates memory control signals / RAS, / CAS, / WE for reading and writing image data to the final address and the external memory 20.

The image data processed by the input signal processor 30 during the second operation is sequentially stored and read by sequentially increasing addresses. 4 illustrates an address generated by the input signal processor 30 as an example. In order to store the input image data, the current write address becomes the start address, the data ring for writing becomes the last address, and the increment amount is 1. In order to read the image data stored in the memory, the current read address is the start address, the amount of data to be read is the last address, and the increment is 1. In the embodiment of the present invention, the amount of data to be read is 32 and the amount of data to be written is 16, so that the same processing as other conventional circuit blocks can be performed. 5 shows the detailed configuration of the input signal processor 30 as blocks 50-53. At the beginning of the operation, the counters 50 and 51 are initialized to zero values, and when the image data is input, the counters 50 and 51 are stored as 32 data groups, and the write counter value is increased by 1 and the memory address is generated. Therefore, it can be seen that the start address initially becomes 0 and the counter value becomes 1 after writing is completed. This value will later be the start address. On the other hand, the read operation of the stored image data is the same as the above write operation except that only the path of the image data is different.

6 shows a reference address form for motion compensation of the motion compensation processor 40. In MPEG-1 or MPEG-2, the dynamic compensation of input video data is processed in 16x16 units, and the restored video data is also stored in 16x16. When storing image data in 64-bit units, one 16 × 16 block occupies 32 addresses. The amount of external memory for restoring MPEG-2 data of 720x480 or 720x576 requires 16 megabits, and 16 16x16 blocks are stored in one row of the memory. As shown in FIG. 6, in order to read the motion compensation chama data, the memory must perform page mode 2 or 4, and for this purpose, four start addresses, four last addresses, and two incremental addresses are assigned to the memory. Must be provided.

7 shows details of the address selection circuit existing in the motion compensation processor 40. As shown in FIG. The circuit for selecting each address consists of three multiplexers 70-71. The start address and the last address calculated in FIG. 7 are values calculated from the motion compensation vector, and other values are fixed values.

8 shows that the display processor 50 of FIG. 1 generates an address necessary for reading data stored in the memory. In the case of the display, only one data is read, so the start address and the end address are the same and require separate processing. In practice, the operation of generating an address calculates the upper 13 bits and the lower 5 bits separately and finally generates an effective address.

9 shows a circuit responsible for generating a start address, a last address, and an increment generated in the lower 5 bits and generating a page mode completion signal generated therefrom. Reference numerals 90,91,102,103,105-107 denote flip-flop elements, and 93-95,100 denote multiplexers. In FIG. 9, when the page mode start signal is applied, a new start and last address are output, and the next clock generates an next generation address by adding an increment to the currently generated address. The generated address is compared by the comparator 101 with the last address. Thus, the above operation continues until the generated address matches the last address, and upon matching, the page mode completion signal is generated at the AND gate 104.

FIG. 10 shows a circuit for generating memory control signals / RAS (low address strobe signal), / CAS (column address strobe signal) in the memory interface 70 of FIG.

The lower 5-bit address generated in FIG. 9 is added together with the index address and the 16x16 block address to finally generate the memory address, which is shown in FIG. Read and write of image data is performed from the generated address and memory control signals.

According to the present invention as described above, there is an effect that the processing of the image data can be in various forms.

Claims (2)

An address generating circuit of an image signal processing apparatus, comprising: an index register section for storing respective start addresses in an area of an external memory, and for storing unrestored image data in the external memory and reading stored image data from the memory; An input signal processor for generating an address, a motion compensation processor for generating information on a reference address used for motion compensation, and an address for writing motion compensated image data to the external memory, and a restored image data. A display processor for generating an address for reading data to be displayed on the screen, a multiplexer for multiplexing each address generated from the input signal processor, the motion compensation processor, and the display processor according to an applied selection signal; End address by receiving a selected address output from the Multiplexers and the circuit, characterized by having a memory interface for generating memory read and write control signals to the image data to the external memory. 2. The circuit of claim 1 wherein the memory control signals comprise row and column strobe signals.