KR0167682B1 - Data transmission enable signal occurrence circuit of semiconductor memory apparatus - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs:

The present invention relates to a dual port memory of a semiconductor memory device.

2. The technical problem the invention is trying to solve:

The present invention achieves the same operation as one column address strobe transmission cycle when transmitting the same 8 column data to the entire array of samples, thereby reducing the number of cycles required and improving the system performance. To provide.

3. Summary of the Solution of the Invention:

The present invention provides a data transfer enable signal generating circuit of a semiconductor memory device including a DRAM cell array and a sample cell array, wherein the data transfer enable signal is output from the DRAM cell array and includes one or more bits. A counter for inputting an individual address signal for selecting one of the enable signals into the circuit, a combination of the three column address signals output from the counter, and the inverted column address signals, respectively, are inputted as three input signals to each input terminal and inverted. A plurality of NOR gates outputted in OR, a plurality of first inverters connected to output terminals of the respective NOR gates, and outputting an inverted signal, and one input terminal connected to an output terminal of the plurality of first inverters, Generation of total transmission information signal including this one third inverter A plurality of first NAND gates connected to a circuit to output a logically combined signal of an inverse logical product, and a first input terminal is connected to an output terminal of the first NAND gate, and a transmission for controlling the data transmission enable signal is disabled. Inputting the disable control signal to the second input terminal and the transmission cycle enable signal to the third input terminal, resulting in a logical combination of the logical product to output the data transmission enable signals, which are output signals, to the sample cell array simultaneously. A second NAND gate and a second inverter are provided.

4. Important uses of the invention:

It is suitably used for semiconductor memory devices.

Description

Data transfer enable signal generation circuit of semiconductor memory device

1 is a configuration diagram showing a cell array configuration of a serial access memory for one serial port.

2 is an operation timing diagram of FIG.

3 is a detailed circuit diagram of a data transmission enable signal generation circuit according to the prior art.

4 is a data transmission enable signal generation circuit according to the present invention.

5 is a detailed circuit diagram of the entire transmission information signal generation circuit of the data transmission enable signal generation circuit according to the present invention.

6 is an operation timing diagram of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a data transfer enable signal generation circuit for simultaneously transferring a large amount of the same data from a column of a dynamic RAM to a serial port memory during screen cleaning in a dual port memory.

In general, Dual Port Memory, which has a RAM Port (Random Access Memory Port) and a Sam PORT (Serial Acess Memory Port), is primarily a graphics buffer due to the high speed of the Sam Port. Graphic Buffer). That is, the fast data output signal (SAM DOUT or SDOUT) designates the address of the RAMDAC, and the designated color of the RAMDAC corresponds to the pixel of the screen. At this time, the data output through the Sem port comes from having data temporarily transferred from the cell array of the dynamic RAM (or DRAM). In this case, refreshing the screen once requires a large amount of data, and thus a lot of data transfer cycles from the DRAM array to the SAM are required. Moreover, in recent years, as the capacity of dual port memory increases, the chip size increases, and in order to reduce the overall chip size, the sample size is reduced to an effective size, which requires more data transfer cycles. This reduces the performance by degrading the peculiar advantage of the dual port memory that can read and write to the DRAM cell array through the RAM port when only the Sam port is active. have. That is, since the data transfer cycle needs to exchange information with the DRAM cell array, the RAM port cannot be operated at this time. In particular, since screen cleaning requires a large amount of the same data among the various functions of the screen display, first record the data to be used as the DRAM cell, and then transfer the data to the SAM, and then through the serial port from the SAM. The data is output, but the same data is transferred in each cell over several data transfer cycles. 1 is a configuration diagram showing a cell array configuration of a serial access memory for one serial port. Referring to FIG. 1, the data transfer from the DRAM cell array to the cell array is performed by receiving 8 bit column data selected from the DRAM cell array at the input address DATA IN7: 0. Data is stored in inverters 7, 9, in eight cells 50 in the selected fountain array 100 of one hundred. The construction is connected to the output terminal of the DRAM cell array receives the transmit enable signal DTPi and the transmission enable signal DTPi and the inverted signal through the inverter 5 as a switch for transmitting data of the DRAM cell array as a switch gate 8 And a latch circuit composed of inverters 7, 9, one side of which is connected to the transfer gate 8 to latch and temporarily store the data, and one side of which is connected to the latch circuit, and the other side of which is connected to the sam data output plate. A cell 50 of Sam, consisting of an MOS transistor 10 for outputting the data to a serial port activated by a signal SELi, the inverter 5, a transfer gate 8, a latch circuit and an MOS transistor 10, and the eight cells It consists of a sam array 100 of eight rows of 50. In operation, the Sam data output pin DQ, that is, the Sam array corresponding to the serial port is configured as an 8 × 8 structure, so that each Sam array 100, for example, the Sam cell 50 corresponding to the row, has a data transfer path. The enable signal DTPi restores the selected 8-bit column data from the DRAM array as a latch circuit by DPTO to DTP7, respectively. 2 is an operation timing diagram of FIG. Referring to FIG. 2, referring to FIG. 2, eight cycles of each data output pin DQ are enabled by one cycle, and the states of the 3-bit counter output signals CNT0, CNT1, and CNT2. An example of one row controlled by the enabled DTPi of eight row arrays with one of eight data transmission enable signals DTP0 to DTP7 enabled and having the same data path from the DRAM array For example, data is stored in a sam array (8-bit cells). Therefore, eight column address strobe cycles (CAS cycles), for example, a transfer cycle T are required to transfer eight arrays of DRAM array data to eight sample arrays. Eight transmission cycles are required even if the same eight column data is transmitted. 3 is a detailed circuit diagram of a data transmission enable signal generation circuit according to the prior art. Referring to FIG. 3, a noah gate for combining a three-bit counter output signal CNT2, CNT1, CNT0 and the inverted logic sum by using the signals passed through inverters 3, 5, and 7 which inverts the signals are three input signals, respectively. 31,41,51,61,71,81,91,101 and the DTPi disable control signal PIDDTEDB which determines the pulse width of the DTPi by controlling the disable of the data transmission enable signal DTPi and enable during the transmission cycle. NAND gates 35, 45, and 55, which combine the inverted and logical outputs of the signal SDTP and the output signals of the NOA gates 31, 41, 51, 61, 71, 81, 91, and 101, respectively, to enable the DTPi. And 65, 75, 85, 95, 105 and inverters 9, 11, 13, 15, 17, 19, 21, 23 which invert the output signals again. The SDTP is enabled during the transmission cycle, and the PIDDTEDB controls the disable of the data transmission enable signal DTPi to determine a pulse width. Here, the 3-bit counter output signals CNTO, 1, and 2 are incremented by 1 bit when performing the transmission cycle, and decoded to select and enable one of the eight data transmission enable signals DTP7: 0. Therefore, the data of the DRAM array may not be simultaneously transmitted to eight sample arrays, thereby reducing the overall performance when performing a large amount of the same data output operation such as screen cleaning.

Accordingly, an object of the present invention is to enable the data transfer to improve the system performance by reducing the number of cycles required by performing the same operation as one column address strobe transfer cycle when transmitting the same 8 column data to the entire sampling array. It is to provide a signal generating circuit.

According to the technical idea of the present invention for achieving the above object, in the data transfer enable signal generation circuit of a semiconductor memory device consisting of a dual-port memory including a DRAM cell array and a sam cell array, from the DRAM cell array A counter which inputs an individual address signal which is output and is composed of one or more bits and selects one of a plurality of data transmission enable signals into a circuit, a combination of three column address signals output from the counter and an inverted column address signal, respectively A plurality of NOA gates inputted as three input signals to each input terminal and inverted and logic-outputted, a plurality of first inverters connected to an output terminal of each of the NOA gates to output an inverted signal, and a plurality of one input terminals Connected to the output terminals of the first inverter A plurality of first NAND gates connected to all transmission information signal generation circuits including one third inverter to output a logically combined signal of an inverse logic, and a first input terminal to an output terminal of the first NAND gate; And a transmission disable control signal for controlling the data transmission enable signal is disabled to a second input terminal, and a transmission cycle enable signal is input to a third input terminal, resulting in a logical combination of logical products. And a second NAND gate and a second inverter for simultaneously outputting transmission enable signals to the sample cell array.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

It should be noted that like elements and parts in the drawings represent like reference numerals wherever possible.

4 is a data transmission enable signal generation circuit according to the present invention. Referring to FIG. 4, the configuration is Noah gates 31, 41, 51, 61, 71, 81, 91, 101 and NAND gates 35, 45, 55, 65, 75, 85, 95, 105 in the configuration of FIG. Inverters 113, 43, 53, 63, 73, 83, 93, 103 and inverters 113, NAND gates 34, 44, 54, 64 connected to respective output and input terminals in between Control means 500, consisting of 74, 84, 94, 104, are added to the configuration of FIG. In other words, the inverter outputs 8 lines which are decoded and output of the 3-bit counter output signals CNT0, CNT1, and CNT2 through the inverters 33, 43, 53, 63, 73, 83, 93, and 103, respectively. The NAND gates 34, 44, 54, 64, 74, 84, 94, and 104, which use one side input and the other side input as the entire transmission information signal SRTF, are added to the data transmission enable signal generation circuit of FIG. In operation, when the entire transmission information signal SRTF is enabled, the eight data transmission enable signals DTPi, for example, DTP7: 0 are simultaneously enabled by ignoring the decoding paths of the 3-bit counter output signals CNT0, 1 and 2, respectively. Data of the selected eight columns of the DRAM cell array are simultaneously transferred to eight row sampling arrays. As can be seen in FIG. 1, the sampling cells of each sampling array can be used because each column uses a data path corresponding to the columns of each DRAM cell array. At this time, the enable of the entire transmission information signal SRTF is generated by differentiating from the general transmission cycle when the transmission cycle is set up, and at the same time, the mode is set up when transmitting to the entire sampling array. This can be seen in Table 1. Table 1 is a table showing the transmission format according to the combination of column selection addresses in the column address strobe signal transmission cycle. Table 1 is as follows.

In the column address strobe signal cycle, up to eight different transfer cycle modes can be created by a combination of column addresses A0, A1, and A2, depending on the column address at the time of the function definition as the transfer cycle. In this case, since eight columns are simultaneously enabled, the group addresses A0, A1, and A2 are not used to select columns of the DRAM array. 5 is a detailed circuit diagram of the entire transmission information signal generation circuit of the data transmission enable signal generation circuit according to the present invention. The transmission cycle information signal PITRAN and the column address A1, A2 and the column address A0 through the inverter 40 are inputted, and the NAND gate 60 and the inverter 70, which form a combination of logical products, generate the entire transmission information signal SRTF and generate data. Supply to the transmission enable signal generating circuit. 6 is an operation timing diagram of FIG. Referring to FIG. 4, the combination of the remaining addresses A2, A1, and A0 except for an address for selecting a column in the DRAM array among the addresses input during the column address strobe signal transmission cycle is described in Table 1 above. As can be seen, since the address corresponds to the entire transmission mode of 0, 1 and 1, the transmission cycle information and the address combination information are ANDed together to enable the entire transmission information signal SRTF and the signal SDTP enabled with the transmission cycle information SRTF. And enable all of the data transfer enable signals DTP0 to DTP7. Accordingly, the data storage or the transmit enable signal DTPi of the eight sampling arrays of FIG. When the data of the input data signal DATA IN7: 0 are the same, all the sample cells have the same data. Of course, each data output pin DQ has a sam array as shown in FIG. 1, and different data can be transmitted for each DQ. In this case, the data of the serial port is outputted with the same data set for each DQ. Therefore, it is possible to output the data as necessary without a transmission cycle. Of course, each conventional transmission is possible by a combination of addresses. That is, when the addresses A2, A1, and A0 are 0, 0, 0, the signal SRTF is not enabled by setting the transmission mode according to Table 1, respectively. The signal SDTP is enabled by the transmission cycle information. At this time, one DTP selected from the data transmission enable signals DTP0 to DTP7 is enabled by decoding of the 3-bit counter output signal CNT2, 1, 0. In the first transmission cycle, the signal CNT2, 1, 0 is 0, 0, 0, so that the signal DTPO is enabled as in FIG. 4, which is the first array of row samples controlled by the signal DTPO in FIG. The data of the input data signal DATA IN7: 0 is transferred. In the second transmission cycle, the signal DTP1 is enabled by the counter output signals CNT2, 1 and 0 that are automatically generated. The column input data signal DATA IN7: 0 of the DRAM array selected in the second transmission cycle is transmitted to the second low sampling array. As described above, according to the present invention, the same operation as one column address strobe transmission cycle when transferring the same eight column data to the entire sampling array results in improved system performance by reducing the number of cycles required. It works.

Although the present invention described above has been limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.

Claims (4)

A data transfer enable signal generation circuit of a semiconductor memory device having a dual port memory including a DRAM cell array and a sample cell array, the data transmission enable signal generating circuit comprising: one or more bits of a plurality of data transfer enable signals output from the DRAM cell array. A counter for inputting an individual address signal for selecting a circuit into a circuit, three column address signals outputted from the counter, and inverted column address signals, respectively, are input as three input signals to each input terminal, and are then inverted and logically outputted. A plurality of NOA gates, a plurality of first inverters for outputting an inverted signal by connecting an input terminal to an output terminal of each of the NOA gates, one input terminal is connected to an output terminal of the plurality of first inverters, and a type force terminal is one A total transmission information signal generating circuit including a third inverter and Transmission disable control for controlling a plurality of first NAND gates that are connected to output a logical combined signal of an inverse logic and a first input die connected to an output terminal of the first NAND gate, and disabling the data transfer enable signal. A second NAND for simultaneously inputting a signal to a second input terminal and a transmit cycle enable signal to a third input terminal and consequently performing a logical combination of logical products to output data transmission enable signals, which are output signals, to the sample cell array at the same time; A data transfer enable signal generation circuit of a semiconductor memory device, comprising a gate and a second inverter. 2. The data transfer enable signal generation circuit of claim 1, wherein the plurality of NOR gates comprise eight. 2. The data transfer enable signal generation circuit of claim 1, wherein the plurality of first inverters comprises eight. 4. The data transfer enable signal of a semiconductor memory device according to claim 1 or 3, wherein the plurality of second NAND gates and second inverters are configured in the same number as the first NAND gates and the first inverters. Generating circuit.