JPH0696583A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To access at a high speed by forming at least one of a row address input terminal and a column address input terminal of a terminal common with a data input/output terminal. CONSTITUTION:A row address is input to a row address buffer 3 through a data input/output and row address terminal, a column address is input to a column address buffer 6 through a data input/output and column address terminal, and fetched to buffers 3, 7. Then, a row in which a row decoder 2 is designated is selected in response to a signal of the buffer 3, and a column is designated by a column decoder 6 in response to a signal of the buffer 7. Here, data rear by a sense amplifier and an input/output controller 4 are output from data input/output buffer 5 via data input/output and row address and input/ output and column address terminals. Then, since any one of the row address input terminal and the column address input terminal becomes common with a data input/output terminal, accessing can be accelerated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a memory address having a plurality of input / output pins.
It relates to the improvement of data multiplex input.

[0002]

2. Description of the Related Art For example, in a dynamic RAM having dynamic memory cells, an address input terminal and a data input / output terminal are separately provided, and row and column addresses are input by timing division to input the whole address. The number of terminals of the device has been reduced.

FIG. 7 is a block diagram showing the structure of a conventional semiconductor memory device in which the number of terminals is reduced as described above. In the figure, 1 has an address space of 256 rows.times.256 columns, and has an input of 16 bits. 1 Mbit memory array with output, 2 row decoder, 3 row address buffer, 4 1
Sense amplifier and input / output control connected to each column of the M-bit memory array 1, 5 is a data input / output buffer for transmitting amplified data of the sense amplifier 4, 6 is a column decoder, 7 is a column address buffer, and 8 is each circuit Is a timing generation circuit for generating the operation timing of the above, and 100 indicates the entire semiconductor memory device.

Next, the operation will be described. 8 is shown in FIG.
8 is a timing chart illustrating a read operation of the conventional semiconductor memory device shown in FIG.

The / RAS terminal is a row address strobe input, and the row address buffer 3 latches the row address signal input from the address input terminals A _{0 to} A ₇ at the falling timing of this signal. Then, the row address is transmitted to the row decoder 2 in accordance with the latched row address signal. Row decoder 2 activates the row designated by row address buffer 3 and selects one row out of 256 rows of 1 Mbit memory array 1. Then, the sense amplifier 4 reads the data of 256 columns connected to the selected one row.

On the other hand, after the row address signal is latched by the row address buffer 3, address input terminals A _{0 to} A
_A column address signal is input to ₇ . Then, the column address buffer 7 internally transmits the column address in accordance with the input column address signal. The column decoder 6 receiving this column address designates one of the 256 columns, and the data of the designated column is transmitted to the data input / output buffer 5 via the sense amplifier and the input / output control 4. Next, external / CAS (column address strobe input: Column Add
ress Strobe Input) and / OE (output enable input:
The data of the data input / output buffer 5 appears from the data input / output terminal due to the low level active state of (Output Enable Input).

[0007]

As described above, in the conventional memory device, the address input terminal and the data input / output terminal are required independently of each other, and the column address signal and the row address signal have the same time as those of the same terminal. Since it is necessary to divide and input the data, the column address cannot be input internally until the row address signal is latched internally, which causes a problem that the data access time cannot be shortened.

An object of the present invention is to obtain a semiconductor memory device capable of inputting a row address signal and a column address signal from different terminals, respectively, and enabling high speed access.

Still another object of the present invention is to provide a semiconductor memory device capable of performing high-speed access as described above and reducing the number of input signal terminals.

[0010]

A semiconductor memory device according to the present invention is such that one of a row address input terminal and a column address input terminal is commonly used as a data input / output terminal. In the semiconductor memory device according to the present invention, each of the row address input terminal and the column address input terminal is shared with the data input / output terminal.

[0011]

According to the present invention, since the row address signal and the column address signal can be simultaneously transmitted to the inside, the data access time can be shortened. Further, in the present invention, both the row address input terminal and the column address input terminal are shared with the data input / output terminal, so that the number of signal input terminals can be reduced.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a semiconductor memory device according to an embodiment of the present invention. In the figure, 1 to 8 indicate the same or corresponding portions as in FIG. A row address is input to row address buffer 3 through a data input / output / row address terminal, and a column address is input to column address buffer 7 through a data input / output / column address terminal.

FIG. 2 is a timing chart for explaining the operation of the semiconductor memory device of the present invention shown in FIG. A row address and a column address are input from the data input / output / row address and the data input / output / column address terminals at the falling edge of the / ADS (Address Strobe Input) terminal, and the row address buffer 3 and the column address buffer 7 Is taken into.

Then, the row decoder 2 selects a designated row among 256 rows in response to the signal of the row address buffer 3, and at the same time, the column decoder 6 designates a column in accordance with the signal of the column address buffer 7. . The data read by the sense amplifier and the input / output control 4 is output from the data input / output buffer 5 from the data input / output / row address and data input / output / column address terminals.

Although the read cycle has been described above, the write cycle is the same except that the data input / output buffer performs the write operation. In such a semiconductor memory device according to this embodiment, the column address input terminal and the row address input terminal are formed by different terminals, and these column address input terminal and row address input terminal are shared with the data input / output terminal. As a result, the data access time can be shortened and the number of terminals of the entire device can be reduced.

FIG. 3 is a block diagram of a semiconductor memory device according to a second embodiment of the present invention. In this semiconductor memory device, only column addresses are shared with data input / output terminals.
The signal input to the row address buffer is the same as the conventional one, but the signal input to the column address buffer is input from the data input / output terminal.

FIG. 4 is a timing chart for explaining the operation of the semiconductor memory device shown in FIG. As shown in the figure, since the row address and the column address are given at the falling edge of / ADS, the access speed can be increased as compared with the conventional case.

In such a semiconductor memory device according to this embodiment, the row address input terminal and the column address input terminal are formed by different terminals, and the input terminal to the column address buffer is common to the data input / output terminal. Since this is achieved, the speed can be increased as compared with the conventional one.

FIG. 5 shows a semiconductor memory device according to a third embodiment of the present invention. In this semiconductor memory device, a column address is input from a column address input terminal and a row address is shared by data input / output terminals. You are typing.

FIG. 6 is a timing chart for explaining the operation of the semiconductor memory device shown in FIG. At the falling edge of / ADS, the row address buffer 3 and the column address buffer 7 latch the column address and the row address. Then, a row of the 1 Mbit memory array is selected according to each data, the data of the selected row is read by the sense amplifier and the input / output control 4, and the column decoder 6 selects the designated column. Then, the data input / output buffer 5 outputs the selected data.

Next, when the column address changes from the column address 1 to the column address 2, the column address buffer similarly fetches the column address 2 in accordance with the address input, and another column address in the row address designated at the falling edge of / ADS. The column decoder 6 specifies the column address 2, and the data is subsequently output.

In such a semiconductor memory device of this embodiment, the row address input terminal and the column address input terminal are formed by different terminals, and the row address input terminal is shared with the data input / output terminal. Therefore, so-called page access is possible in which different column addresses are continuously read or written with respect to the same row address.

[0023]

As described above, according to the present invention, either one of the row address input terminal and the column address input terminal is shared with the data input / output terminal, so that the access speed can be increased. is there.

Further, according to the present invention, both the row address input terminal and the column address input terminal are shared with the data input / output terminal, so that access can be speeded up and the number of signal input / output terminals can be reduced. Therefore, there is an effect that the device can be downsized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a memory device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the memory device according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a memory device according to another embodiment of the present invention.

FIG. 4 is a timing chart showing an operation of a memory device according to another embodiment of the present invention.

FIG. 5 is a block diagram showing a memory device according to another embodiment of the present invention.

FIG. 6 is a timing chart showing an operation of a memory device according to still another embodiment of the present invention.

FIG. 7 is a block diagram illustrating a conventional memory device.

FIG. 8 is a timing chart showing the operation of the conventional memory device.

[Explanation of symbols]

 1 1M bit memory array 2 row decoder 3 row address buffer 4 sense amplifier and input / output control 5 data input / output buffer 6 column decoder 7 column address buffer 8 timing generation circuit 100 memory device

Claims (2)

[Claims] 1. A memory cell array having an address space in the row and column directions, and a row address buffer to which a plurality of row address signals are input and latched and which supplies a row address to a row decoder described later according to the plurality of row address signals. , A plurality of column address signals are input and latched, and a column address buffer for giving a column address to a column decoder described later according to the plurality of column address signals; and a row of the memory cell array receiving a signal from the row address buffer. It has a row decoder for selection and a column decoder for receiving a signal from the column address buffer and selecting a column of the memory cell array, and writes or reads data at a specific address specified by a plurality of address signals. In the semiconductor memory device, the plurality of row address signals are externally input. The semiconductor memory device characterized by at least one row address input terminal for inputting an address input terminal and the plurality of column address signals, and of a common terminal and the output terminal of the data. 2. The semiconductor memory device according to claim 1, wherein both the row address input terminal and the column address input terminal are shared with the data input / output terminal.