KR0167669B1 - Manufacturing Method of Semiconductor Device - Google Patents
Manufacturing Method of Semiconductor Device Download PDFInfo
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- KR0167669B1 KR0167669B1 KR1019950041736A KR19950041736A KR0167669B1 KR 0167669 B1 KR0167669 B1 KR 0167669B1 KR 1019950041736 A KR1019950041736 A KR 1019950041736A KR 19950041736 A KR19950041736 A KR 19950041736A KR 0167669 B1 KR0167669 B1 KR 0167669B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 125000006850 spacer group Chemical group 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 24
- 229920005591 polysilicon Polymers 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims 1
- 210000002268 wool Anatomy 0.000 claims 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
- H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
- H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 게이트전극이 오버랩된 LDD 구조의 트렌지스터 제조방법에 관한 것으로, 제1도전형 반도체기판상에 게이트절연막을 형성하는 공정과, 상기 게이트절연막위에 제1도전층과 제1절연막을 차례로 형성하는 공정, 상기 제1절연막 및 제1도전층을 소정의 게이트패턴으로 패터닝하여 제1도전층으로 이루어진 게이트전극을 형성하는 공정, 저농도의 제2도전형의 불순물을 이온주입하여 상기 게이트전극 양단의 기판부위에 LDD 접합을 형성하는 공정, 기판 전면에 제2절연막과 제2도전층을 차례로 형성하는 공정, 상기 제2도전층을 이방성식각하여 상기 게이트전극의 측벽에 스페이서를 형성하는 공정, 상기 스페이서를 식각저지층으로 하여 상기 제2절연막을 제거하는 공정, 상기 게이트전극 상부의 제1절연막을 제거하는 공정,기판 전면에 제3도전층을 형성하는 공정, 및 상기 제3도전층을 블랭킷 에치백하여 상기 게이트전극과 스페이서를 접속하는 도전층 스트링거를 형성하는 공정을 구비하여 이루어지 것을 특징으로 반도체장치의 제조방법.The present invention relates to a method of fabricating a transistor having an LDD structure in which a gate electrode is overlapped, and to forming a gate insulating film on a first conductive semiconductor substrate, and sequentially forming a first conductive layer and a first insulating film on the gate insulating film. Forming a gate electrode formed of a first conductive layer by patterning the first insulating layer and the first conductive layer into a predetermined gate pattern; implanting impurities of a low conductivity type second conductive type; Forming an LDD junction at a portion; forming a second insulating layer and a second conductive layer on the entire surface of the substrate; and forming an spacer on a sidewall of the gate electrode by anisotropically etching the second conductive layer. Removing the second insulating layer as an etch stop layer, removing the first insulating layer on the gate electrode, and forming a third conductive layer on the entire substrate And a step of forming a conductive layer stringer connecting the gate electrode and the spacer by blanket-etching the third conductive layer to form a conductive layer stringer.
Description
제1도는 종래의 게이트 오버랩된 트렌지스터의 단면구조를 개략적으로 도시하고 단면도이고,1 is a schematic cross-sectional view and cross-sectional view of a conventional gate overlapped transistor,
제2도는 본 발명의 방법에 따른 일 실시예의 반도체장치 제조방법의 제조공정 순서 단면도이다.2 is a cross sectional view of a manufacturing process of a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2 : 게이트절연막1 substrate 2 gate insulating film
3 : 게이트전극 5 : LDD접합3: gate electrode 5: LDD junction
4 : 산화막 6 : 나이트라이드막4: oxide film 6: nitride film
7 : 폴리실리콘 스페이서 8 : 폴리스트링거7: polysilicon spacer 8: polystringer
본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 게이트전극이 오버랩된 LDD(Lightly Doped Drain) 구조의 트렌지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a transistor having an LDD structure having overlapping gate electrodes.
종래의 LDD 구조를 갖는 반도체장치에서는 LDD 접합 상부에 산화막 또는 절연막이 존재하여 전하가 트랩되는 장소로 기능하게 되어 반도체장치의 전기적인 특성이 열화되는 요인이 되고 있다.In a conventional semiconductor device having an LDD structure, an oxide film or an insulating film is present on the LDD junction, and thus functions as a place where charges are trapped, thereby deteriorating electrical characteristics of the semiconductor device.
게이트가 오버랩된 구조의 LDD 트렌지스터는 저농도의 n형 LDD 접합이 존재함으로 인하여 발생하는 트렌지스터의 특성열화를 개선시키기 위한 구조로서, 게이트 오버랩된 LDD구조의 트랜지스터는 LDD 접합부 상부에 게이트전극이 오버랩되도록 형성하여 종래의 LDD 구조에 따른 트렌지스터가 신뢰성이 저하되는 문제에 대한 대비를 하기 위한 것이다. 그러나 이러한 LDD 구조 위에 게이트전극을 오버랩시키기 위한 반도체장치의 제조방법은 매우 복잡한 제조공정이 요구된다.The LDD transistor with overlapped gate structure is designed to improve the deterioration of transistor characteristics due to the presence of low concentration of n-type LDD junction. The transistor according to the conventional LDD structure is to prepare for the problem that the reliability is lowered. However, the manufacturing method of the semiconductor device for overlapping the gate electrode on the LDD structure requires a very complicated manufacturing process.
종래의 게이트 오버랩된 트렌지스터의 단면구조를 개략적으로 도시하고 있는 제1도를 참조하여 보면, 도면에서 보듯이 폴리실리콘 게이트를 인버스(inverse)-T 형태로 형성시켜야 한다. 즉, 게이트전극 하부의 폭이 넓은 폴리실리콘과 상부의 좁은 폴리실리콘을 각각 분리시켜 형성한후, 양쪽의 폴리실리콘을 연결하는 방법이 흔히 사용되는데, 이러한 형상의 게이트전극을 형성하는 과정은 매우 어렵고 복잡한 제조공정을 요구하게 된다.Referring to FIG. 1 schematically illustrating a cross-sectional structure of a conventional gate overlapped transistor, as shown in the drawing, a polysilicon gate should be formed in an inverse-T shape. That is, a method of connecting the polysilicon of both sides after forming the wide polysilicon under the gate electrode and the narrow polysilicon on the upper side separately, is commonly used. Complex manufacturing processes are required.
본 발명은 게이트전극 하부의 폴리실리콘을 형성하지 않고, 스페이서를 폴리실리콘으로 사용하여 형성한 후, 이 스페이서와 게이트, 폴리실리콘을 연결시킴으로서 종래의 게이트 오버랩된 LDD 구조의 트렌지스터 제조공정보다 제작공정이 간단하고 특성상 문제가 없는 새로운 반도체장치의 제조방법을 제공하는데 그 목적이 있다.The present invention does not form polysilicon under the gate electrode, but forms the spacer using polysilicon, and then connects the spacer, the gate and the polysilicon, so that the manufacturing process of the transistor manufacturing process of the LDD structure overlapping the conventional gate is more complicated. It is an object of the present invention to provide a method for manufacturing a new semiconductor device that is simple and has no problems in nature.
상기한 목적을 달성하기 위한 본 발명의 바람직한 일 실시예의 게이트 오버랩 트렌지스터의 제조하는 방법은 제1도전형 반도체기판상에 게이트절연막을 형성하는 공정과, 상기 게이트절연막위에 제1도전층과 제1절연막을 차례로 형성하는 공정, 상기 제1절연막 및 제1도전층을 소정의 게이트패턴으로 패터닝하여 제1도전층으로 이루어진 게이트전극을 형성하는 공정, 저농도의 제2도전형의 불순물을 이온주입하여 상기 게이트전극 양단의 기판부위에 LDD 접합을 형성하는 공정, 기판 전면에 제2절연막과 제2도전층을 차례로 형성하는 공정, 상기 제2도전층을 이방성식각하여 상기 게이트전극의 측벽에 스페이서를 형성하는 공정, 상기 스페이서를 식각저지층으로 하여 상기 제2절연막을 제거하는 공정, 상기 게이트전극 상부의 제1절연막을 제거하는 공정, 기판 전면에 제3도전층을 형성하는 공정, 및 상기 제3도전층을 블랭킷 에치백하여 상기 게이트전극과 스페이서를 접속하는 도전층 스트링거를 형성하는 공정을 구비하여 이루어진다.A method of manufacturing a gate overlap transistor according to a preferred embodiment of the present invention for achieving the above object is a step of forming a gate insulating film on a first conductive semiconductor substrate, a first conductive layer and a first insulating film on the gate insulating film Forming a gate electrode formed of a first conductive layer by patterning the first insulating layer and the first conductive layer into a predetermined gate pattern, and ion implanting impurities of a second conductivity type with low concentration. Forming LDD junctions on the substrates at both ends of the electrodes, sequentially forming a second insulating layer and a second conductive layer on the entire surface of the substrate, and anisotropically etching the second conductive layer to form spacers on sidewalls of the gate electrode. Removing the second insulating layer by using the spacer as an etch stop layer, and removing the first insulating layer on the gate electrode. , It is achieved by etching back the first step, and the third conductive layer to form a third conductive layer over the entire surface of the substrate to the blanket by a step of forming a conductive layer stringers for connecting the gate electrode and spacers.
이하, 첨부도면을 참조하여 본 발명의 바람직한 실시예들을 보다 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2도(a)는 본 발명의 방법에 따른 일 실시예의 반도체장치 제조방법의 제조공정 순서 단면도로서, 이 도면을 참조하여 일 실시예의 반도체장치 제조방법을 살펴보면, 먼저, 제2도 (A)에 도시된 바와 같이 반도체기판(1) 상에 게이트절연막(2)을 형성한다. 이어서, 상기 게이트절연막(2) 위에 폴리실리콘(3) 또는 폴리사이드(polycide)를 침적하고, 산화막(4)을 적층형성한 후, 포토리소그래피 기술을 통해 상기 산화막과 폴리실리콘(또는 폴리사이드)을 소정의 게이트패턴으로 패터닝하여 게이트전극(3)을 형성한다.FIG. 2A is a cross sectional view illustrating a manufacturing process of a semiconductor device manufacturing method in accordance with an embodiment of the present invention. Referring to this drawing, a semiconductor device manufacturing method in accordance with an embodiment will now be described. A gate insulating film 2 is formed on the semiconductor substrate 1 as shown in FIG. Subsequently, polysilicon 3 or polycide is deposited on the gate insulating film 2, and an oxide film 4 is laminated. Then, the oxide film and the polysilicon (or polyside) are formed through photolithography. The gate electrode 3 is formed by patterning a predetermined gate pattern.
다음에 제2(b)도에 도시된 바와 같이 저농도의 n형 불순물을 액티브 영역에 이온주입하고 어닐링하여 n- LDD 접합(5)을 형성한다.Next, as shown in FIG. 2 (b), a low concentration of n-type impurities is ion implanted into the active region and annealed to form an n-LDD junction 5.
계속해서, 제2(c)도에 도시된 바와 같이 기판 전면에 절연막으로서,예컨데 나이트라이드막(6)을 형성한다.Subsequently, as shown in FIG. 2C, the nitride film 6 is formed as an insulating film over the entire surface of the substrate.
이어서 제2(d)도에 도시된 바와 같이 상기 나이트라이드막(6)상에 폴리실리콘층 형성한 다음, 이방성식각으로 상기 폴리실리콘층을 식각하여 게이트전극의 측벽에 폴리실리콘 스페이서(7)를 형성한다.Subsequently, as shown in FIG. 2 (d), a polysilicon layer is formed on the nitride layer 6, and then the polysilicon layer is etched by anisotropic etching to form a polysilicon spacer 7 on the sidewall of the gate electrode. Form.
이어서, 제2(e)도에 도시된 바와 같이 폴리실리콘 스페이서(7)를 식각저지층으로 이용하여 상기 나이트라이드막(6)을 습식식각방식으로 제거하고, 계속해서 게이트전극 상부의 산화막을 습식식각하여 제거한다.Subsequently, as shown in FIG. 2E, the nitride layer 6 is removed by wet etching using the polysilicon spacer 7 as an etch stop layer, and the oxide layer on the gate electrode is wetted. Etch and remove
그 다음, 제2(f)도에 도시된 바와 같이 폴리실리콘 스페이서(7)와 게이트전극(3)의 폴리실리콘을 접속하기 위해 또 다른 폴리실리콘층을 기판 전면에 형성하고, 이를 블랭킷 에치백(blanket etchback)하여 제2(g)도에 도시된 바와 같이 게이트전극(3)과 스페이서의 폴리실리콘(7)을 접속시키는 폴리스트링거(poly-stringer)(8)를 게이트전극 측벽에 형성함으로써 게이트전극(3)과 폴리실리콘 스페이서(7) 및 이들을 연결하는 폴리스트링거(8)로 이루어지는 오버랩 구조의 게이트전극을 형성한다. 이후, 고농도의 n형 불순물을 기판에 이온주입하여 고농도 소오스 및 드레인을 형성함으로써 본 발명의 일실시예에 의한 게이트 오버랩구조의 트렌지스터를 완성하게 된다.Then, as shown in FIG. 2 (f), another polysilicon layer is formed on the entire surface of the substrate to connect the polysilicon spacer 7 and the polysilicon of the gate electrode 3, and the blanket etchback ( The gate electrode is formed by forming a poly-stringer 8 on the sidewall of the gate electrode which blanket-etches back and connects the gate electrode 3 and the polysilicon 7 of the spacer as shown in FIG. 2 (g). An overlapping gate electrode composed of (3) and a polysilicon spacer 7 and a polystringer 8 connecting them is formed. Thereafter, a high concentration of source and drain are formed by ion implanting a high concentration of n-type impurities into a substrate, thereby completing a transistor of a gate overlap structure according to an embodiment of the present invention.
이상 상술한 바와 같이 본 발명에 의하면, 폴리실리콘을 오버랩된 게이트극의 측벽스페이서 재료로 활용하고, 이 폴리실리콘 스페이서와 게일, 전국의 폴리실리콘을 단순한 공정에 의해 연결함으로써 게이트 오버랩된 LDD 구조이 트렌지스터를 용이하게 제조할 수가 있다.As described above, according to the present invention, the gate overlapped LDD structure is formed by using polysilicon as the sidewall spacer material of the overlapped gate electrode and connecting the polysilicon spacer, the galle and the polysilicon of the whole country by a simple process. It can be manufactured easily.
또한, 차세대 극미세구조의 트렌지스터 제조공정에 있어서 전극이 오버랩된 LDD 트렌지스터를 효과적으로 형성하여 집적소자의 개발을 용이하게 할 수 있으며, 고집적반도체 소자의 제작으로 수익성 증대효과를 얻을 수 있다.In addition, in the next-generation ultra-fine transistor manufacturing process, LDD transistors with overlapping electrodes may be effectively formed to facilitate the development of integrated devices, and profitability may be increased by manufacturing highly integrated semiconductor devices.
또한, 고집적 반도체장치의 기초소자인 트렌지스터를 신뢰성과 동작 특성이 우수하게 제작함으로서 모든 반도체장치의 활용이 가능하고 차세대 반도체장치의 개발에 유용하게 된다.In addition, since the transistor, which is a basic element of the highly integrated semiconductor device, is manufactured with excellent reliability and operation characteristics, all semiconductor devices can be utilized and are useful for the development of next-generation semiconductor devices.
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