KR0165889B1 - Current difference circuit - Google Patents

Abstract

None.

Description

Circuit for forming current difference

1, 3 and 4 are circuit diagrams illustrating different embodiments for forming a current difference.

2A-2F show time curves for two currents at current inputs E ₁ and E ₂ and time curves for current difference at current outputs A;

* Explanation of symbols for main parts of the drawings

1, 2 current path i ₁ , i ₂ : input current

T ₁ , T ₄ : input transistors T ₃ , T ₆ : output transistors

T ₂ , T ₅ : Balance transistor K ₁ , K ₂ : Node

The present invention relates to a circuit for forming a current difference, in which two input currents are supplied to different current input portions.

Using a difference circuit, a difference of two current input amounts is formed and transmitted to the output of the circuit. With the help of the rectifier circuit, the input amount with alternating current (A.C.) is rectified. That is, signals having the same polarity are received at the output of the circuit. For example, an amplitude modulated HF signal in a radio must be rectified, i.e. demodulated, so that the low frequency portion of the previously modulated carrier signal can be output through the amplifier to the speaker.

It is an object of the present invention to provide a simple circuit which utilizes a difference in the amount of two input currents of the same polarity. If either input current is alternating current, the difference in input current must be rectified.

This purpose is that both input currents flow through the individual current paths of the circuit to both sides of the current balance, and in the event of a difference in the input currents, the current required to achieve the equilibrium state of the current balance is the current output of the circuit. Is achieved by using a circuit for forming a current difference of a current having the same polarity according to the invention, which is supplied from a current supply line from or removed from the current balancer to a current output section through a current discharge line.

Here, the current balance transistor is preferably designed as a current inverter and consists of two transistors having the same emitter surface, having the same base / emitter voltage due to the circuit arrangement, and having an emitter connected to ground potential. This allows the same collector current or emitter current to flow through both balanced transistors and allows simple current comparison. If both input currents flowing from both sides of the current balance transistor into the individual current paths of the circuit arrangement are equal in magnitude, the current balance transistor is in equilibrium. Therefore, the requirements for the equilibrium of transistor currents are met.

If a difference occurs in the two input currents, the current balance transistor is not in an equilibrium state. Therefore, the difference current required to bring the current balance transistor into equilibrium flows from one current output portion of the circuit to the current balance transistor having a low input current or from the side having a large input current to the current output portion, so that the current balance transistor is balanced. Is converted to a state.

For the purpose of supplying or removing the difference current, the output transistor connected to the current output of the circuit is triggered by the collector / emitter voltage of the balance transistor, depending on the setting of the current balance transistor.

The output current at the current output is simply the magnitude of the difference of the two input currents of the same extreme.

The input current at the current input of the circuit is first made a potential offset by the base / emitter voltage of these transistors by passing through the input transistors which are preferably connected as diodes. The effect of this is that the collector / emitter voltage of the balance transistor is always in the optimum operating range, thereby achieving a larger modulation range for the balance transistor.

If at least one of the two input currents of the same polarity is alternating current, a difference in two input currents is formed for both half-waves of the alternating current and transferred to the current output in a positive value, i.e., rectified, so that full-wave rectification is obtained. In addition, the difference value of the input current, that is, the difference of the output current, can be smoothed by integrating with a capacitor, for example, using known connecting means, and then further processed.

The circuit arrangement is preferably designed symmetrically such that the difference rectification has high accuracy by symmetrical rectification of both half waves. The fact that both half-waves can be rectified results in a higher output signal, which is advantageous for further processing of this output signal, for example to reduce ripple. For example, the distortion rate, which represents an error dimension for the linearity of the rectification, and which substantially depends on the symmetry of the components, in particular the balance transistor, can be reduced in nature.

If the design of the circuit permits, the balance transistor is provided with an emitter resistor; The resulting reduction in the effect of the elements on commutation further increases commutation accuracy. With the circuit arrangement according to the invention, a difference between an alternating current having a frequency between OHz (direct current) and the upper limit frequency can be formed / rectified. This threshold frequency is caused by parasitic capacitance occurring in circuits that do not achieve charge reversal at high frequencies in time, resulting in defective difference formation or rectification.

The operation mode of the circuit according to the present invention will be described in more detail with reference to FIGS. 1 to 4.

In the circuit arrangement according to FIG. 1, the input current i ₁ in the current path 1 is from the current input E ₁ to the resistor R ₃ , the input transistor T ₁ , the node K ₁ and the balance. Flows through transistor T ₂ to a reference potential, preferably a ground potential; Input current i ₂ in current path 2 is grounded from current input E ₂ through resistor R ₄ , input transistor T ₄ , node K ₂ and balance transistor T ₅ . Flow to potential

또는

의 전류가 전류 출력부(A)로 흐른다. 동일한 전위차가 노드(K₁및 K₂)에 공급된다; 그러므로, 2 밸런스 트랜지스터(T₂및 T₅)는 동일한 콜렉터/에미터 전압을 갖는다. 그러므로, 동일한 콜렉터 전류/에미터 전류가 양 밸런스 트랜지스터에 흘러 전류 밸런스 트랜지스터는 평형 상태에 있게 된다 만일 2 입력 전류(i₁및 i₂)가 다르다면, 예컨대 i₁i₂이라면, 낮은 전압이 노드(K₁)보다는 노드(K₂)에 존재한다; 따라서, 밸런스 트랜지스터(T₂)에서의 콜렉터/에미터 전압이 밸런스 트랜지스터(T₅)에서의 콜렉터/에미터 전압보다 더 커지게 되어 밸런스 트랜지스터는 평형 상태를 상실하게 된다. 그러나, 본 발명에 따른 회로 디자인에서는 양 밸런스 트랜지스터에 동일한 전류가 흘러야 된다. 이러한 이유로해서, 기존의 전류차(i₁-i₂)가 밸런스를 상실하여 전류 밸런스가 평형 상태로 복귀될 때까지 전류(i_A)가 전류 출력부(A)로부터 출력 트랜지스터(T₃)를 통해 노드(K₂)로 흘러야 한다. 만일 입력 전류(i₁)가 입력 전류(i₂)보다 작다면, 즉 i₁i₂이라면 반대의 결과가 발생한다; 밸런스 트랜지스터(T₂)에서의 콜렉터/에미터 전압이 밸런스 트랜지스터(T₅)에서의 콜렉터/에미터 전압보다 작아지게 된다. 전류 밸런스부의 평형 상태를 이루기 위해, 밸런스 트랜지스터들의 2 콜렉터 전류가 동일해질 때까지 출력 전류(i_A)가 출력 트랜지스터(T₆)를 통해 노드(K₁)로 흐른다.If the two input currents i ₁ and i ₂ are the same, a low zero input current is passed through the base of the output transistor T ₃ or T ₆ to the current output A or the node K ₁ or K _2, respectively. Flow. This zero input current depends on the size of the resistors R ₃ / R ₄ and the relationship between the emitter surfaces of the transistors T ₁ and T ₃ / T ₄ and T _6, respectively. If, for example, the relationship of emitter surfaces is chosen to be 10: 1 and the resistors (R ₃ / R ₄ ) are chosen to be 2µs, a voltage drop of about 60µs may occur.

or

Current flows to the current output unit (A). The same potential difference is supplied to nodes K ₁ and K ₂ ; Therefore, the two balance transistors T ₂ and T ₅ have the same collector / emitter voltage. Therefore, the same collector current / emitter current flows in both balance transistors, resulting in a balanced current balance transistor. If the two input currents i ₁ and i ₂ are different, e.g. i ₁ i ₂ , the low voltage is a node. Are present at node K ₂ rather than (K ₁ ); Thus, the balance transistor (T ₂₎ is the collector / emitter voltage of the balanced transistor (T ₅₎ is made higher than the collector / emitter voltage of the transistor in the balance it loses the equilibrium. However, in the circuit design according to the invention, the same current must flow through both balanced transistors. For this reason, the current i _A causes the output transistor T ₃ to flow out of the current output unit _A until the existing current difference i ₁ -i ₂ loses its balance and the current balance returns to the equilibrium state. Must flow through node (K ₂ ). If the input current i ₁ is less than the input current i ₂ , i.e. i ₁ i _{2, the} opposite result occurs; The collector / emitter voltage of the balanced transistor (T ₂₎ balance transistor (T ₅₎ becomes smaller than the collector / emitter voltage in the. To achieve the equilibrium state of the current balance portion, the output current i _A flows through the output transistor T ₆ to the node K ₁ until the two collector currents of the balance transistors are equal.

Thus, output transistors T ₃ and T ₆ are triggered depending on the difference in collector / emitter low voltage of the balance transistor; That is, blocked or conducted. In the current output unit A, the difference (i ₁ -i ₂ ) of the amount of two currents is obtained for i ₁ i ₂ and i ₁ i ₂ in both cases to form a difference and full-wave rectification for both half-waves. A capacitor (not shown) may be connected to the current output unit A to smooth the rectified output signal. Transistors T ₇ and T ₈ provide the base current required for the current balance transistor. If the supply voltage or output voltage is high enough, the balance transistors T ₂ and T ₅ may be provided with emitter resistors; This makes it possible to compensate for the surface or parameter difference of the balance transistor by the negative feedback effect, so that the current inverter, and therefore the current balance part, operates more accurately.

2a-2f show the time curves of the input current i ₁ or i ₂ and the output current i _A as an example.

2a, 2c and 2e, the input current i ₁ has an alternating current at the input portion E ₁ and the input current i ₂ has a direct current; Positive input current has positive polarity. 2b, 2d and 2f show the time curves of the (rectified) difference of the two input currents; A positive value for the output current (i _A) is solved for the time, and i ₁ i ₂ i ₁ i ₂ in time. Figures 2c-f show the operating mode of the 180 ° phase shift switch. Depending on the amplitude ratio of the signal current i ₁ to the switching direct current i ₂ , a signal current smaller than the switching current is delivered to the output in its original phase or 180 ° out of phase. The turning 2d represents a phase signal (i ₁ i _2), the 2f gives the output signal (i ₁ i ₂₎ 180 ° phase shift.

0.65V 관계 때문에, 출력 트랜지스터(T₃및 T₆)는 U_BET6=U6되지 않는다. 따라서 제1도에 따른 회로와 달리 전류 밸런스부가 평형 상태에 있을 때 어떠한 영 입력 전류도 전류 출력부(A)로 흐르지 않는다. 만일 입력 전류(i₁및 i₂)의 크기가 서로 다르다면, 예컨대 i₁i₂이라면, 전류 밸런스부의 평형 상태를 달성하기 위하여 차 전류(i₁-i₂)가 전류 출력부(A)로부터 출력 트랜지스터(T₃)를 통해 밸런스 트랜지스터(T₅)로 흐르도록 트랜지스터(T₃)의 베이스/에미터 전압이 충분히 클 때까지 전류 입력부(E₂)에서의 전압이 강하한다. 제3도의 회로는 단지 몇가지 부품으로 구성되며, 작은 공간을 요하고, 그러므로 제조 가격이 싸진다. 하나의 결점은 완전히 대칭으로 구성되지 않으므로 제1도에 도시된 회로만큼 정확하게 동작하지 않는다는 것이다.3 is a simpler variant of the above mentioned circuit according to FIG. When the input currents i ₁ and i ₂ are the same, approximately the same current flows to the balance transistors T ₂ (diode) and T ₅ so that the current balance portion is in an equilibrium state. U _BET1 = U _BET6 + U _BET3

Because of the 0.65V relationship, the output transistors T ₃ and T ₆ are not U _BET6 = U6. Thus, unlike the circuit according to FIG. 1, no zero input current flows to the current output portion A when the current balance portion is in equilibrium. If the magnitudes of the input currents i ₁ and i ₂ are different, for example i ₁ i ₂ , the differential currents i _1- i ₂ are drawn from the current output part A to achieve an equilibrium state of the current balance part. The voltage at the current input portion E ₂ drops until the base / emitter voltage of the transistor T ₃ is large enough to flow through the output transistor T ₃ to the balance transistor T ₅ . The circuit of FIG. 3 consists of just a few components, requires little space, and therefore is cheap to manufacture. One drawback is that they do not operate as accurately as the circuit shown in FIG.

4 shows another embodiment of a circuit according to the invention. A current balance transistor consisting of balance transistors T ₂ and T ₅ , through which input currents i ₁ and i ₂ flow less than the output current, is provided through resistors R ₅ and R ₆ between the collector and the base.

In addition, the inputs E ₁ and E ₂ are connected to the respective differential voltage inputs K ₃ and K ₄ of the operational amplifier and to the collectors of the transistors T ₉ and T ₁₀ . The difference between the input currents i ₁ and i _{2 results} in a difference in the collector / emitter voltage of the balance transistors T ₂ and T ₅ , resulting in a lack of equilibrium in the balance transistor. In order to make the same current flow again through the balance transistor, the output transistors T ₃ , T ₉ or T ₁₀ , T ₆ are controlled by the operational amplifier 3 due to the difference in the collector / emitter voltage of the balance transistor. In this case, the amount of the difference current i _1- i ₂ is discharged from the side of the balance transistor having a higher current through the transistor T ₉ or T ₁₀ to ground and at the same time the output transistor T ₃ or T ₆ . Passed in the inverted form to the current output unit (A) through. Therefore, the output current i _A again corresponds exactly to the amount of difference current i ₁ -i ₂ of the two current input unit.

The circuit according to the invention can be used wherever a difference of two input currents of the same polarity must be formed. This circuit can preferably be used, for example, in a rectifier, a demodulator, preferably an amplitude modulated demodulator, or a differential rectifier circuit of a measuring device in which the rms value is expressed as an analog quantity. In the demodulator, the zero input current of the circuit is optimized according to the maximum frequency required for the demodulator with minimal distortion. In the individual circuit arrangement according to FIG. 1, a demodulator of an AM signal having 100 Hz may be achieved; The distortion rate may then be reduced to 0.1% for 80% modulation rate. Integrated technology is also used for applications at 455 GHz. As shown in Figs. 2C to 2F, it is possible for the 180 ° phase shifter to change the phase from 0 ° to 180 ° without changing the amplitude by the switch and the DC control.

Claims (18)

In a circuit for forming a current difference of a current having the same polarity, wherein two input currents i ₁ and i ₂ are configured to be applied to different current inputs, the two input currents i ₁ and i ₂ When the current flows from the separated current paths 1 and 2 to one side of the current balance part consisting of two balance transistors T ₂ and T ₅ , and a difference occurs in the input currents i ₁ and i ₂ , the balance state of the current balance part The current i _A necessary for holding is a relatively small input current i ₁ , i ₂ of the balance transistors T ₂ , T ₅ from the current output A through the output transistors T ₃ , T ₆ . Is supplied to a balance transistor (T ₂ , T ₅ ) flowing through the circuit. 2. The balanced transistors T ₂ and T ₅ have the same base-emitter voltage and the same emitter surface, and the input currents i ₁ and i ₂ are balanced transistors T ₂ and T _5. And the bases of the balance transistors (T ₂ , T ₅ ) are connected to each other and the emitters of the balance transistors (T ₂ , T ₅ ) are connected to ground potential. The supply of output current i _A to the balance transistors T ₂ , T _{5 is} via two output transistors T ₃ , T ₆ , and the collectors connected to each other are And a current output section (A). 4. The circuit of claim 3, wherein the circuit is configured symmetrically. The input transistors T ₁ , T of claim 2, wherein the input currents i ₁ , i ₂ at the current inputs E ₁ , E ₂ are connected as diodes in one current path 1, 2, respectively. ₄ ) flows to the node points K ₁ , K ₂ and from the node points through the balance transistors T ₂ , T ₅ to the ground potential, and the bases connected to each other of the balance transistors T ₂ , T ₅ . Is supplied current through the emitters of two auxiliary transistors (T ₇ , T ₈ ) with collectors connected to auxiliary voltage (V ₁ ), and the bases of the auxiliary transistors (T ₇ , T ₈ ) are each It is connected to the current inputs E ₁ , E ₂ , and the current supply has two output transistors T ₃ , T ₆ , and the collector of the output transistors T ₃ , T _{6 is} connected to the current output A. form and its base is of the current input (E _1, E ₂₎ is connected to its emitter, respectively other current path (2, 1) for Note that the circuit node is placed, characterized in that connected to the (K _1, K _2). 6. The circuit according to claim 5, wherein the emitter surface of the input transistors (T ₁ , T ₄ ) connected as diodes is four times the emitter surface of the output transistors (T ₃ , T ₆ ). The input transistor (E ₁ , E ₂ ) of claim 6, wherein the current inputs (E ₁ , E ₂ ) are connected to the base of the input transistors (T ₁ , T ₄ ) having resistors (R ₃ , R ₄ ) between the collector and the base. And the collector of (T ₁ , T ₄ ) is connected to the base of the output transistors (T ₃ , T ₆ ). 8. The circuit of claim 7, wherein the balance transistor (T ₂ , T ₅ ) has an emitter resistance. In the input unit (E ₁₎ a first input current (i ₁₎ of the first current path (1) the input transistor input transistor (T ₁₎ through (T ₁₎ connected as a diode in the claim 2, wherein Flows to the node point K ₁ connected to the emitter and from the node point to the balance transistor T ₂ connected as a diode and then to the ground potential, the second input current i ₂ at the input E ₂ . ) Flows in the second current path 2 to the second balance transistor T ₅ , the current inlet has two output transistors T ₃ , T ₆ , and the current output A of the circuit is an output transistor ( T _3, T ₆₎ of being formed of a collector connected to each other emitters second input of the first output transistor (T ₃₎ of the base is connected to the first input (E ₁₎ the first output transistor (T ₃₎ ( E is connected to _2), the second base of the output transistor (T ₆₎ is connected to the second input (E ₂₎ the second output Transistor circuit, characterized in that connected to the emitter node point (K) of the (T _6). In a circuit for forming a current difference of a current having the same polarity, wherein two input currents i ₁ and i ₂ are configured to be applied to different current inputs, the two input currents i ₁ and i ₂ When the current flows from the separated current paths 1 and 2 to one side of the current balance part consisting of two balance transistors T ₂ and T ₅ , and a difference occurs in the input currents i ₁ and i ₂ , the balance state of the current balance part The current i _A necessary for holding is output transistor T ₉ from the balance transistors T ₂ and T ₅ through which relatively large input currents i ₁ and i ₂ flow among the balance transistors T ₂ and T ₅ . , T ₁₀ ) a circuit which is drawn out to the current output unit (A). The balance transistors (T ₂ , T ₅ ) of claim 10, wherein the balance transistors (T ₂ , T ₅ ) have the same base-emitter voltage and the same emitter surface, and the input currents (i ₁ , i ₂ ) are balanced transistors (T ₂ , T _5). And the bases of the balance transistors (T ₂ , T ₅ ) are connected to each other and to the emitter ground potential of the balance transistors (T ₂ , T ₅ ). 11. The method of claim 10, wherein the withdrawal of the output current i _A from the current balance part is made through two output transistors T ₃ , T ₆ , and the collectors connected to each other of the transistors are connected to the current output part A. Forming a circuit. The input current i ₁ , i _{2 of} the current input part E ₁ , E ₂ flows to the ground potential through the collectors of the balance transistors T ₂ , T ₅ , and the current balance part is balanced. Transistors T ₂ and T ₅ are supplied with current through resistors R ₅ and R ₆ connected between the collector and the base, and the operational amplifier 3 has two differential voltage inputs K ₃ and K ₄ and It has two differential outputs K ₅ , K ₆ , and two output stages each have two output transistors T ₃ , T ₉ or T ₆ , T ₁₀ , and the output transistors T ₃ , T ₉ or T The emitters of ₆ , T ₁₀ are connected to the ground potential, and the collectors of the two output transistors T ₉ , T ₁₀ are the current inputs E ₁ , E ₂ and the derivative input K ₃ of the operational amplifier _3. , is connected to K _4), the two output transistors (T _9, T base and the other of the two output transistors ₁₀₎ (T _3, T ₆₎ are each base operational amplifier (3) Differential output is connected to the (K _5, K _6), a collector connected to each other in the two different output transistors (T _3, T ₆₎ of the circuit, characterized in that to form a current output section (A). 15. The circuit of claim 13 wherein the balance transistor (T ₂ , T ₅ ) comprises an emitter resistor. 10. The circuit according to any one of claims 1 to 9, wherein when the input currents have the same polarity, a current having a time dependent amplitude is supplied to at least one input and a rectified difference between the two input currents is obtained. A circuit characterized by being used as a rectifier circuit to be obtained at an output. A method using the circuit according to claim 15 as a demodulator for demodulation of an amplitude modulated signal. Method using the circuit according to any one of claims 1 to 9 as a 180 ° phase shifter switch. 10. Use of a circuit according to any one of claims 1 to 9 as a frequency doubler circuit.

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