JPS61131606A - differential amplifier circuit - Google Patents

Abstract

PURPOSE:To simplify and miniaturize the titled circuit by constituting a cascode amplifier stage of an FET amplifier circuit having a cascode amplifier stage with a self-bias circuit. CONSTITUTION:The self-bias circuit constitution is adopted by connecting gates and drains of FETs 5, 7 of the cascode amplifier stage in a direct coupling FET amplifier circuit consisting of a differential amplifier stage comprising FETs 1-4, the cascode amplifier stage comprising FETs 5-8 and a push-pull amplifier stage comprising FETs 9, 10. Thus, any complicated bias circuit is not required and the entire circuit is simplified and miniaturized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a differential amplifier circuit, and more particularly, to a differential amplifier circuit suitable for an integrated circuit button configured with an lrF insulated gate field effect transistor.

[Background of the invention]

An example of a conventional differential amplifier circuit using insulated gate field effect transistors is shown in FIG. In the figure, differential input transistors 1 and 2 are connected to load transistors 3 and 4. Transistor 5.6 is connected in cascode with transistors 1 and 2.

Operates as a gate-grounded amplifier circuit. The cascode stage output terminal 23 is connected to a buffer stage consisting of transistors 9.10. In conventional circuits like this.

In order to operate the cascode stage transistors 5 and 6 stably, the gate bias was determined as follows. i.e. transistors 11.12 biased to have high resistance.
is connected to the cascode stage output terminal 22°25, the in-phase signal component obtained is detected by the transistor 13, and the reference voltage 1
Compare with 8. If the common mode signal voltage of the cascode stage output voltage is high.

The current flowing through transistor 15 decreases, transistor 1
As the output voltage of the current mirror circuit 4.15 increases, the output voltage of the cascode stage biased with this voltage decreases. In this way, a bias circuit using negative feedback is provided so that the common mode signal voltage of the cascode stage becomes a desired voltage, and a stable point determined by the circuit itself is created.

However, there are cases in which poles and zeros occur in the frequency band used in the bias circuit, and in this case, the frequency characteristics and response waveform of the differential amplifier circuit deteriorate. In addition, the number of elements in the bias circuit in this example is 6 transistors 11 to 16, and two types of bias voltage 17°18 are required, and in addition to the above, a lot of effort is required to design it so that zero points do not occur. It is.

[Object of the Invention J] An object of the present invention is to be able to generate a bias voltage for a cascode stage transistor with a very simple circuit configuration. The goal is to provide a differential amplifier circuit with good characteristics.

[Summary of the invention]

The present invention is characterized in that it adopts a method of applying a self-bias by connecting one of the cascode stage outputs to the gate electrode of the cascode transistor.

[Embodiment of the Invention j Hereinafter, nine embodiments of the present invention will be described with reference to FIG. Differential input transistor 1.2 is connected to load transistors 3, 4. Transistor 5.6 is transistor 1.
2 is connected in cascode.

Operates as a gate-grounded amplifier circuit. The cascode stage output terminal 25 is connected to a buffer stage consisting of transistors 9,10. The present invention provides cascode stage output terminals 24 and 25.
Among them, the terminal 24 is used as a gate bias of the transistor 5.6 VcID.

Transistor 5 becomes a self-bias circuit with its drain and gate connected. Therefore, when the current flowing between the drain and the source is determined, the voltage between the gate and the source of the transistor 5 is determined. Therefore, when the differential signal voltage of the cascode stage input signal is sufficiently small, the source potentials of transistors 5 and 6 are approximately equal to t't.

The same bias conditions are obtained. However, since the voltage amplification factor of the cascode stage output stage is about 40 dB in total,
When changing the output voltage by several volts, transistor 5.
The bias voltage between the gate and source of transistor 6' is sufficiently small, with a difference of only several tens of millivolts, so the above condition is satisfied and the bias voltages of transistors 5 and 6 are equal.

When the common-mode component voltage of the cascode stage output voltage rises, the gate bias voltage of transistors 5 and 6 rises, and the dK negative 4R that lowers the cascode stage output voltage becomes noisy, so that the circuit is functionally the same as the conventional example. There is a point of stability that is determined by itself. Moreover, this negative path is transistor 5
Because it operates at the speed of a self-biasing circuit, it is extremely fast and does not suffer from the problems of unnecessary poles and zeros seen in conventional examples. Also, the bias points are transistors 5, 6, 7. The running speed can be set by the size of B and the current value of @12.13,
The design is extremely easy compared to the conventional example.

[Effects of the Invention] According to the present invention, a complicated negative feedback bias circuit for stably operating the cascode stage is not required, the circuit configuration is simplified, and the problem of unnecessary poles and zeros is solved. This has the effect of making it easier to design a differential amplifier circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional differential amplifier circuit, and FIG. 2 is a circuit diagram showing an embodiment of the differential amplifier circuit according to the present invention. 1 to 10...Insulated gate field effect transistor. 11-13...Bias current source, 24.25...Cascode stage output.

Claims (1)

[Claims] 1. A differential input stage consisting of a pair of input differential transistors each having a load connected to its drain, and a differential output of the differential input stage as its source input signal and its output. a cascode stage consisting of a pair of transistors, one of which is given as a gate bias voltage. 2. The differential amplifier circuit according to claim 1, wherein the load is constituted by an active load transistor forming a current mirror. 3. Claim 2, characterized in that each of the transistors is constituted by an insulated gate field effect transistor.
Differential amplifier circuit described in section.