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KR0159016B1 - 반도체소자의 금속배선간 절연막의 제조방법 - Google Patents

반도체소자의 금속배선간 절연막의 제조방법 Download PDF

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KR0159016B1
KR0159016B1 KR1019950017677A KR19950017677A KR0159016B1 KR 0159016 B1 KR0159016 B1 KR 0159016B1 KR 1019950017677 A KR1019950017677 A KR 1019950017677A KR 19950017677 A KR19950017677 A KR 19950017677A KR 0159016 B1 KR0159016 B1 KR 0159016B1
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film
insulating film
semiconductor device
layer
oxide film
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KR1019950017677A
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KR970003630A (ko
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이승무
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김주용
현대전자산업주식회사
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Priority to KR1019950017677A priority Critical patent/KR0159016B1/ko
Priority to TW085106271A priority patent/TW297924B/zh
Priority to US08/660,151 priority patent/US6060382A/en
Priority to JP8152660A priority patent/JP2857369B2/ja
Priority to CN96108235A priority patent/CN1056468C/zh
Publication of KR970003630A publication Critical patent/KR970003630A/ko
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Publication of KR0159016B1 publication Critical patent/KR0159016B1/ko

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Abstract

본 발명은 반도체소자의 금속배선간 절연막의 제조방법에 관한 것으로서, 금속배선이 되는 도전패턴을 절연막상에 형성한 후에 상기 구조의 표면을 플라즈마로 처리한 후, SiH4-N2O 혼합 가스를 사용한 굴절율 1.47 이상의 Si 과함유 산화막을 상기 구조의 전표면에 형성하며, 상기 산화막상에 O3-TEOS막을 형성하여 금속배선간 절연막을 완성하였으므로, O3-TEOS막의 성장 속도가 향상되며, 내부에 보이드등의 생성이 방지되는 등 막질이 향상되어, 절연막의 재현성이 향상되어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있다.

Description

반도체소자의 금속배선간 절연막의 제조방법
제1a도 내지 제1c도는 종래의 기술에 따른 반도체소자의 금속배선간 절연막의 제조 공정도.
제2a도 내지 제2d도는 본발명에 따른 반도체소자의 금속배선간 절연막의 제조 공정도.
* 도면의 주요부분에 대한 부호의 설명
1 : 절연막 2 : Ti층
3 : TiN층 4 : W층
5 : 반사방지막 6 : 산화막
7 : O3-TEOS막 8 : 과실리콘 산화막
본 발명은 반도체소자의 금속배선간 절연막의 제조방법에 관한 것으로서, 특히 W 배선을 패턴닝하고 패턴닝한 표면을 플라즈마 처리를 실시하고, 상기 구조의 전표면에 플라즈마 유도(plasma enhanced) 화학기상증착(chemical vapor deposition; 이하 PE CVD라 칭함) 방법으로 형성된 제1금속간 절연막을 형성하고, 그 상부에 평탄화막으로 형성되는 O3-TEOS막을 형성하여 O3-TEOS막의 막질을 향상시키고, 재현성이 향상되어 공정수율 및 소자 동작의 신회성을 향상시킬 수 있는 반도체소자의 금속배선간 절연막의 제조방법에 관한 것이다.
반도체소자의 고집적화에 따라 게이트 전극이나 비트라인등의 도전배선의 폭이 줄어들고 있으나, 도전배선의 폭이 N배 줄어들면 전기 저항이 N배 증가되어 반도체소자의 동작속도를 떨어뜨리는 문제점이 있다.
일반적으로 반도체 소자의 게이트나 비트라인등에 사용되는 도전배선으로는 주로 도핑된 다결정실리콘층을 사용하며, 이는 면저항이 약 30~70Ω/□ 정도이며, 콘택 저항이 하나의 콘택당 약 30~70Ω/□ 정도이다.
이와 같이 높은 면저항 및 콘택저항을 감소시키기 위하여 다결정실리콘층상에 금속-실리사이드막이 적층되어있는 살리사이드(salicide; self-aligned silicide) 구조나 선택적 금속막 증착 방법으로 도전배선의 상부에만 금속 실리사이드막이나 선택적 금속막을 형성하여 면저항 및 콘택 저항을 감소시켰다.
예를들어 다결정실리콘층 패턴의 상측에 Ti 실리사이드나 선택적 W을 형성하면, 면저항은 약 5Ω/□, 콘택저항은 콘택택당 약 3Ω/□ 이하로 현저하게 감소되어 소자의 동작 시간 지연을 방지하고, 고집적화가 가능하다.
또한 금속배선으로서도 종래에는 Al이나 그 합금을 주로 사용하였으나, Al 보다 고온에서의 안전성이 우수하고, 금속배선 두께를 얇게 형성하여 평탄화가 용이한 W이 사용되기도 한다.
제1a도 내지 제1c도는 종래의 기술에 따른 반도체소자의 금속배선간 절연막의 제조 공정도로서, W 배선의 예이다.
먼저, 도시되어 있지는 않으나, 실리콘 웨이퍼로된 반도체기판상에 소자분리 산화막과 MOS 트랜지스터와 캐패시터 및 비트라인을 형성하고, 상기 구조의 전표면에 절연막(1)을 형성한다.
그다음 상기 절연막(1)상에 장벽금속층인 Ti층(2)과 TiN(3)을 형성하고, 상기 TiN층(3) 상에 CVD 방법으로 W층(4)을 형성한 후, 상기 W층(4)상에 W층(4)의 패턴닝을 위한 노광 공정시의 난반사를 방지하기 위한 TiN으로된 반사방지막(5)을 형성한다.
그후, 통상의 사진식각방법으로 상기 반사방지막(5)에서 Ti층(2)까지 순차적으로 습식 또는 건식식각하여 반사방지막(5) 패턴에서 Ti층(2) 패턴까지의 도전패턴으로 구성되는 금속배선을 형성한다. (제1a도 참조).
그다음 상기 구조의 전표면에 통상의 CVD 방법으로 산화막(6)을 1000Å 정도의 두께로 형성하고, 상기 산화막(6)의 표면을 Ar 이나 N2가스 플라즈마에 노출시켜 표면을 손상시키고, 전하를 발생 시킨다. 이공정은 후에 형성되는 평탄화층과의 계면 특성을 향상을 위한 공정이다. (제1b도 참조).
그후, 상기 표면이 손상된 산화막(6)상에 O3-TEOS막(7)을 형성하고, 이를 유동시켜 반도체소자의 금속배선간의 제조 공정을 완료한다. (제1c도 참조).
상기와 같은 종래 기술에 따른 반도체소자의 금속배선간 절연막의 제조방법은 금속배선의 표면에 산화막을 형성하고, 상기 산화막의 표면을 플라즈마 처리하여 손상시킨 후, 평탄화막인 O3-TEOS막을 형성하는데, 상기 O3-TEOS막이 하부층에 대한 의존성이 높아 하부층의 종류나 상태에 따라 성장 속도가 다르고, 막질내에 다량의 보이드가 형성되거나, 유동성이 약화되고, 소자의 재현성이 떨어져 공정수율 및 소자 동작인 신뢰성이 떨어지는 문제점이 있다.
더우기 상기 금속배선이 Al이 아닌 W 배선인 경우에는 상기 O3-TEOS막의 성장 속도가 더욱 떨어지고, 막질이 악화되는 문제점이 있다.
본발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본발명의 목적은 금속배선을 패턴닝한 후, 전표면을 플라즈마 처리하여 손상시키고, CVD 산화막과 O3-TEOS막을 전표면에 형성하여 절연층의 내부에 보이드가 형성되거나 막질이 악화되는 것을 방지하고, 재현성이 우수하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 금속배선간 절연막의 제조방법을 제공함에 있다.
상기와 같은 목적을 달성하기 위한 본발명에 따른 반도체소자의 금속배선간 절연막 제조방법의 특징은, 반도체기판상에 절연막을 형성하는 공정과, 상기 절연막상에 금속배선을 형성하는 공정과, 상기 구조의 금속배선을 플라즈마 처리하는 공정과, 상기 구조의 전표면에 과 실리콘 산화막을 형성하는 공정과, 상기 산화막 상에 O3-TEOS막을 형성하는 공정을 구비함에 있다.
이하, 본발명에 따른 반도체소자의 금속배선간 절연막의 제조방법에 관하여 첨부도면을 참조하여 상세히 설명한다.
제2a도 내지 제2d도는 본 발명에 따른 반도체소자의 금속배선간 절연막의 제조 공정도로서, W 배선의 예이다.
먼저, 도시되어 있지는 않으나, 실리콘 웨이퍼로된 반도체기판상에 소자분리를 위한 소자분리 산화막을 형성하여 활성영역을 정의하고, 게이트전극과 소오스/드레인전극등으로 구성되는 MOS 트랜지스터와 캐패시터 및 비트라인등을 형성하여 소자 구조를 완성하고, 상기 구조의 전표면에 산화막이나 비.피.에스.지(Boro Phospho Silicate Glass; 이하 BPSG라 칭함)등의 재질로된 절연막(1)을 형성한다.
그다음 상기 절연막(1)상에 금속배선의 스파이크나 불순물 확산을 방지하기 위한 장벽금속층인 Ti층(2)과 TiN층(3)을 스퍼터링등의 방법으로 형성하고, 상기 TiN층(3) 상에 CVD 방법으로 W층(4)을 형성한다.
그후, 상기 W층(4)의 패턴닝을 위한 노광 공정시의 광의 난반사를 방지하기 위한 TiN으로된 반사방지막(5)을 스퍼터링 방법으로 W층(4)상에 형성한 후, 통상의 사진식각방법으로 상기 반사방지막(5)에서 Ti층(2)까지 순차적으로 습식 또는 건식식각하여 반사방지막(5) 패턴과, W층(4) 패턴, TiN층(3) 패턴 및 Ti층(2) 패턴으로 구성되는 금속배선을 형성한다. (제2a도 참조).
그다음 상기 반사방지막(5) 패턴과, W층(4) 패턴, TiN층(3) 패턴 및 Ti층(2) 패턴과 절연막(1)의 노출되어있는 표면을 Ar 플라즈마로 처리한다. 본발명자의 실험 결과에 따르면 상기 플라즈마 처리의 조건은 상하 두 종류의 주파수를 인가하는 양 주파수(dual frequency) 방식으로서, 고주파수는 200~400W, 저주파수는 50W 이상의 파워로하여, 25℃ 이상의 온도에서, 10초 이상 실시하면, 후속 적층되는 O3-TEOS 절연막의 막질이 우수해진다. 또한 Ar이 아닌 N2가스 플라즈마로 처리하여도 동일한 효과를 얻을 수 있다. (제2b도 참조).
그후, 상기 구조의 전표면에 플라즈마 유도(plasma enhanced) CVD(이하 PECVD라 칭함) 방법으로 SiH4-N2O 혼합 가스를 사용하여 굴절율이 1.47 이상의 Si 원자를 과함유하는 산화막(8)을 1000Å 이상의 두께로 형성한다. 여기서 상기 산화막의 굴절율은 통산의 CVD 산화막의 굴절율이 1.45 정도인 것을 고려하면, 굴절율이 높을수록 후속 적층막의 막질이 향상되는 것을 실험 결과로 알수 있었다. (제2c도 참조).
그다음 상기 산화막(8)상에 O3-TEOS막(7)을 5000Å 이상의 두께로 형성하고, 평탄화시켜 금속배선간 절연막 형성 공정을 완료한다. (제2d도 참조).
상기에는 W배선을 예로 들었으나, O3-TEOS막의 막질이 보다 우수한 경우인 Al배선에서도 본발명의 사상을 적용할 수 있음은 물론이다.
이상에서 설명한 바와 같이, 본발명에 따른 반도체소자의 금속배선간 절연막의 제조방법은 금속배선이 되는 도전패턴을 절연막상에 형성한 후에 상기 구조의 표면을 플라즈마로 처리한 후, SiH4-N2O 혼합 가스를 사용한 굴절율 1.47 이상이 Si 과함유 산화막을 상기 구조의 전표면에 형성하며, 상기 산화막상에 O3-TEOS막을 형성하여 금속배선간 절연막을 완성하였으므로, O3-TEOS막의 성장 속도가 향상되며, 내부에 보이드등의 생성이 방지되는 등 막질이 향상되어, 절연막의 재현성이 향상되어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 이점이 있다.

Claims (9)

  1. 반도체기판상에 절연막을 형성하는 공정과, 상기 절연막상에 금속배선을 형성하는 공정과, 상기 구조의 금속배선을 플라즈마 처리하는 공정과, 상기 구조의 전표면에 과실리콘 산화막을 형성하는 공정과, 상기 산화막 상에 O3-TEOS막을 형성하는 공정을 구비하는 반도체소자의 금속배선간 절연막의 제조방법.
  2. 제1항에 있어서, 상기 절연막이 산화막 또는 BPSG 계열 막인 것을 특징으로하는 반도체소자의 금속배선간 절연막의 제조방법.
  3. 제1항에 있어서, 상기 금속배선이 장벽금속층과 W층 및 반사방지막의 적층 구조로 형성되는 것을 특징으로하는 반도체소자의 금속배선간 절연막의 제조방법.
  4. 제1항에 있어서, 상기 금속배선이 장벽금속층과 Al층으로 형성되는 것을 특징으로하는 반도체소자의 금속배선간 절연막의 제조방법.
  5. 제1항에 있어서, 상기 플라즈마 처리 공정이 Ar 플라즈마로서, 양 주파수(dual frequency) 방식으로, 고주파수는 200~400W, 저주파수는 50W 이상의 파워로하여, 25℃ 이상의 온도에서, 10초 이상 실시하는 것을 특징으로하는 반도체소자의 금속배선간 절연막의 제조방법.
  6. 제1항에 있어서, 상기 플라즈마를 N2가스 플라즈마로 처리하는 것을 특징으로하는 반도체소자의 금속배선간 절연막의 제조방법.
  7. 제1항에 있어서, 상기 과실리콘 산화막을 PECVD 방법으로 SiH4-N2O 혼합 가스를 사용하여 굴절율이 1.47 이상인 산화막으로 형성하는 것을 특징으로하는 반도체소자의 금속배선간 절연막의 제조방법.
  8. 제1항에 있어서, 상기 과실리콘 산화막을 1000Å 이상의 두께로 형성하는 것을 특징으로하는 반도체소자의 금속배선간 절연막의 제조방법.
  9. 제1항에 있어서, 상기 O3-TEOS막을 5000Å 이상의 두께로 형성하는 것을 특징으로 하는 반도체소자의 금속배선간 절연막의 제조방법.
KR1019950017677A 1995-06-28 1995-06-28 반도체소자의 금속배선간 절연막의 제조방법 KR0159016B1 (ko)

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US08/660,151 US6060382A (en) 1995-06-28 1996-06-04 Method for forming insulating film between metal wirings of semiconductor device
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JPH0766287A (ja) * 1993-08-23 1995-03-10 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JPH07115135A (ja) * 1993-10-18 1995-05-02 Toshiba Corp 半導体装置の製造方法
JPH07142471A (ja) * 1993-11-15 1995-06-02 Sony Corp 酸化膜の成膜方法及び酸化膜成膜装置

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CN1143261A (zh) 1997-02-19
KR970003630A (ko) 1997-01-28
TW297924B (ko) 1997-02-11
JPH0917869A (ja) 1997-01-17
CN1056468C (zh) 2000-09-13
US6060382A (en) 2000-05-09
JP2857369B2 (ja) 1999-02-17

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