KR0158641B1 - Matrix display with repairable repair structure in units of pixels - Google Patents

Abstract

The present invention relates to a matrix display device having a mathematical structure of the present invention, and more particularly, to a matrix display device that can be repaired in units of pixels. In the present invention, two or more signal lines such as scan signal lines, display signal lines, and auxiliary signal lines and pixel electrodes are formed by overlapping an insulating layer, thereby disconnecting display signal lines and scan signal lines, short circuiting of pixel electrodes and signal lines, and electrodes of switching elements. If a defect is caused by the loss of the circuit, the overlapped part may be shorted, or the electrodes of the transistor may be shorted and necessary parts may be repaired. At this time, the structures of the auxiliary gate line and the double gate line may be modified together.

Description

Matrix display with repairable repair structure in units of pixels

FIG. 1 is a plan view showing a conventional matrix display device centered on a wiring line,

2 is an equivalent circuit diagram showing a pixel portion of a conventional liquid crystal display device,

3 is a layout view of a thin film transistor substrate for a conventional liquid crystal display device,

4 is a cross-sectional view taken along the line A-A of FIG.

5 is a plan view showing a conventional matrix display device with a repair line formed in a closed curve around a screen, mainly with a wiring,

6a to c are schematic diagrams showing the means for the first repair according to the basic concept of the present invention,

FIG. 7 is a schematic diagram showing a method of repairing a disconnected data line in the structure of FIG.

8 is a schematic diagram showing a second repair means according to the basic concept of the present invention,

9 a and b are schematic diagrams showing a method of repairing a disconnected data line in the structure of FIG. 8;

10 a to c are schematic views showing a third repair means according to the basic concept of the present invention,

11 is a schematic diagram showing a method of repairing a disconnected data line in the structure of FIG.

12 a and b are schematic views showing a fourth repair means according to the basic concept of the present invention,

FIG. 13 is a schematic diagram showing a method of repairing a disconnected data line in the structure of FIG.

14 a to d are schematic views showing a fifth repair means according to the basic concept of the present invention,

FIG. 15 is a schematic diagram showing a method of repairing a disconnected data line in the structure of FIG.

FIG. 16 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention.

17 is a view showing a method for repairing a defect in the first embodiment of the present invention,

18 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

19 a to c are views showing a method for repairing a defect in a second embodiment of the present invention,

20 is a layout view of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention.

21 a and b are views showing a method for repairing a defect in a third embodiment of the present invention,

FIG. 22 is a layout view of a thin film transistor substrate for a liquid crystal display according to a fourth embodiment of the present invention.

23 a and b are views showing a method for repairing a defect in a fourth embodiment of the present invention,

24 is a layout view of a thin film transistor substrate for a liquid crystal display according to a fifth exemplary embodiment of the present invention.

25 a to c are views showing a method for repairing a defect in a fifth embodiment of the present invention,

FIG. 26 is a layout view of a thin film transistor substrate for a liquid crystal display according to a sixth embodiment of the present invention.

27A to 27D illustrate a method for repairing a defect in a sixth embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1, 1a, 1b: auxiliary gate line 2: gate electrode

3: gate oxide film 4: gate insulating layer

5 semiconductor layer 6 contact layer

7 source electrode 8 drain electrode

9: protective film 10: pixel electrode

11, 12, 21, 31, 41, 43, 51, 52, 61, 62: connection

The present invention relates to a matrix type display device having a mathematical structure of the present invention, and more particularly, to a matrix type display device that can be repaired in units of pixels.

As a display device for human and computer media, a liquid crystal display (LCD), a plasma display panel (PDP), which replaces a conventional cathode ray tube (CRT), There are various flat panel displays (FPD) such as EL (electroluminescenec) and FED (field emission display). Such flat panel displays employ a matrix wiring structure that is formed to be orthogonal to each other horizontally and vertically. This will be described in detail with reference to the drawings.

1 is a plan view showing the structure of a matrix display device.

As shown in FIG. 1, in a general matrix display device, a plurality of scan signal lines G ₁ , G ₂ ,..., G _m are formed in parallel to each other, and a plurality of lines intersecting with each other via an insulating layer. The display signal lines D ₁ , D ₂ , D ₃ , D ₄ ,..., D _2n-1 and D _2n are formed vertically.

At one end of each of the display signal lines D ₁ , D ₂ , D ₃ , D ₄ ,..., D _2n-1 , D _2n and the scan signal lines G ₁ , G ₂ , ……, G _m , a signal is inputted. Input pads DP ₁ , DP ₂ , DP ₃ , DP ₄ ,..., DP _2n-1 , DP _2n ; GP ₁ , GP ₂ ,..., GP _m are formed and display signal lines ( D ₁ , D ₂ , D ₃ , D ₄ ,..., D _2n-1 , D _2n ), the input pad is formed on the upper side (D ₁ , D ₃ , ……, D _2n-1 ) and the bottom There are (D ₂ , D ₄ ,..., D _2n ) formed in the.

On the other hand, in the space where the scan signal lines G ₁ , G ₂ ,..., G _m and the display signal lines D ₁ , D ₂ , D ₃ , D ₄ ,..., D _2n-1 , D _2n meet each other, a pixel is formed. (PX) is formed and arranged in the form of a matrix, the structure of this pixel may vary depending on the type of display device.

The liquid crystal display is one of the most popular flat panel display devices in recent years, and is a display device using an electro-optical effect of a liquid crystal material, and its driving method is largely a simple matrix type and an active matrix. It is divided into active matrix types.

In an active matrix liquid crystal display, an operation of each pixel is controlled by adding a switching element having a nonlinear characteristic to each pixel arranged in a matrix form. That is, a three-terminal thin film transistor (TFT) is generally used as the switching element, and a thin film diode (TFD) such as a two-terminal metal insulator metal (MIM) is also used.

In particular, a liquid crystal display using a thin film transistor as a switching element includes a thin film transistor and a pixel electrode, a scan signal line or a gate line supplying a scan signal or a gate signal to pixels, and a display signal or an image signal. A thin film transistor substrate on which display signal lines or data lines to be supplied are formed, an opposing substrate on which a common electrode is formed, and a liquid crystal material enclosed therebetween.

Next, the structure of the pixel of the thin film transistor liquid crystal display will be described with reference to FIG. 2.

2 is a diagram illustrating a structure and an equivalent circuit of a pixel of a liquid crystal display, wherein each pixel PX includes a thin film transistor TFT formed on a lower substrate (a thin film transistor substrate) and a pixel electrode of a lower substrate. And a liquid crystal capacitor C _lc composed of a common electrode CE of the upper substrate, which is the opposite substrate, and a liquid crystal material therebetween, and a storage capacitor C _st formed on the lower substrate. Doing. Here, the storage capacitor C _st serves to hold the signal applied to the pixel PX for a predetermined time. The pixel PX is connected to the data line and the gate line through the thin film transistor TFT.

For example, one terminal of the thin film transistor TFT is connected to the data line, the other terminal is connected to the gate line, and the last terminal is connected to the pixel electrode 10.

However, in FIG. 2, the thin film transistor that opens and closes the corresponding pixel PX has a structure existing outside the pixel. That is, one terminal of the thin film transistor TFT shown in FIG. 2 is a neighboring pixel. It is connected to the pixel electrode of the driving the adjacent pixels. However, there are many cases where a thin film transistor for driving a pixel is formed in the pixel.

In the liquid crystal display, when a pixel is driven and a display operation is performed, a predetermined voltage or a periodic voltage is applied to the common electrode CE, and a voltage is applied to the pixel electrode 10 through the thin film transistor TFT. The display operation is performed by the electro-optic effect of the liquid crystal material of the capacitor C _lc .

Next, in the liquid crystal display having the structures illustrated in FIGS. 1 and 2, the planar layout and the vertical structure of the thin film transistor substrate corresponding to the lower substrate will be described with reference to FIGS. 3 and 4.

FIG. 3 is a plan view illustrating a layout of the thin film transistor substrate corresponding to the lower substrate in FIG. 2, and the gate line structure is a closed curve surrounding the pixel electrode. FIG. 4 is along the AA line of FIG. 3. It is a cut section. Here, PXi (i = 1, 2, 3, 4), which represents a rectangular region, is a region corresponding to the lower part of one pixel, but for convenience, it may include pixels including gate lines and data lines for convenience. The pixel area is referred to as a pixel region, and a set of pixels formed on a horizontal line is referred to as a pixel row.

As shown in FIGS. 3 and 4, upper and lower gate lines G _up and G _down are formed on both sides of the pixel row on the transparent insulating substrate 100. The lower gate line (G _down) may beoteo soon properly horizontally, directed down from the upper gate line (G _up) has a first horizontal portion (G _h1), the first lateral portion (G _h1), which account for most of the length The second vertical portion G _v1 rising upward from the first vertical portion G _v1 , the second horizontal portion G _h1 , and the second horizontal portion G _h2 , which progress horizontally again from the first vertical portion G _v1 . ) Is formed as one repeating unit. The double gate line structure is generally referred to as a double gate line structure.

A second vertical portion of the upper gate line a first horizontal portion (G _h1) and the lower gate line (G _down) is connected to the left auxiliary gate line (1a), an upper gate line (G _up) of (G _up) ( G _v2 ) extends downward to form a right auxiliary gate line 1b that meets the lower gate line G _down .

The data line D is vertically formed between the pixel columns, and the first horizontal portion G _h1 and the lower gate line of the upper gate line G _up are formed through the gate insulating layer (4 in FIG. 4). Intersect with (G _down ).

The upper and lower gate lines G _up and G _down and the pair of auxiliary gate lines 1a and 1b formed to the left and the right form a closed curve, which serves as a black matrix, and is closed by the closed curve. The region includes gate lines G _up and G _down and auxiliary gate lines 1a and 1b with a gate insulating layer (described in FIG. 4) and a protective film (symbol 9 in FIG. 4) described later. The pixel electrodes 10 are formed so as to overlap each other, and the overlapped portions serve as sustain capacitors (C _st in FIG. 2). This holding capacitor is also called a ring capacitor because it consists of a closed curve, and only the upper and lower gate lines G _up and G _down and the pair of auxiliary gate lines 1a and 1b constituting the ring capacitor are used. It is weak and is also called a ring capacitor. Here, the ring capacitor is used in the latter sense.

As described above, when the gate lines G _up and G _down and the auxiliary gate lines 1a and 1b have the structure surrounding the pixel electrode 10 in the form of a closed curve, the gate lines G _up and G _down and the auxiliary gate lines are taken. It is advantageous to adopt such a structure because no signal is cut off if any part of (1a, 1b) is disconnected.

Meanwhile, a thin film transistor is formed in the second vertical portion G _v2 of the upper gate line G _up , which will be described in more detail with reference to FIGS. 3 and 4.

First, part of the second vertical portion G _v2 becomes a gate electrode 2 of the thin film transistor. If the material forming the gate lines G _up and G _down is an anodizable material such as aluminum, except for a gate pad (not shown) that electrically connects the gate lines G _up and G _down to the outside. The remainder is usually anodized. Therefore, the anodized gate oxide film 3 also exists on the gate electrode 2.

On the gate oxide film 3, a gate insulating layer 4 is formed over the gate pad.

The semiconductor layer 5 is formed to cover the gate electrode 2 with the gate insulating layer 4 interposed therebetween. A semiconductor layer 5, in addition to covering the gate electrodes 2 are formed also on the gate lines (G _up, G _down) and serves to prevent short-circuiting of the gate line (G _up, G _down) and the data line (D). The material constituting the semiconductor layer 5 is generally amorphous silicon or polyhard silicon.

A contact layer 6 is formed on the semiconductor layer 5 for good ohmic contact between the semiconductor and the metal, which is mainly composed of n ⁺ amorphous silicon, which is heavily doped. consist of. In FIG. 3, the pattern of the contact layer 6 becomes a portion where the semiconductor layer 5 and the source electrode 7 and the drain electrode 8 overlap each other.

On the contact layer 6, the source electrode 7 which is the branch of the data line D, and the drain electrode 8 separated from this are formed. Since the source electrode 7 is positioned near the intersection of the upper gate line G _up and the data line D, the source electrode 7 may overlap the first horizontal portion G _v2 of the upper gate line G _up as shown in FIG. 3. It may be. One end of the drain electrode 8 faces the source electrode 7 with the gate electrode 2 interposed therebetween, and the other end is connected to the pixel electrode 10 of the upper pixel of the same pixel column and has a lower gate line. Overlaid with (G _down ). For example, in FIG. 3, the drain electrode 8 of the pixel PX2 is connected to the pixel electrode 10 of the pixel PX1, which is the upper pixel of the same pixel column, and the pixel electrode 10 of the pixel PX1. It overlaps with the lower gate line G _down positioned below.

A protective film 9 is entirely covered on the drain electrode 8 and the pixel electrode 10 except for contact portions and pads (not shown), and the pixel electrode 10 made of a transparent conductive material is disposed on the protective film 9. Formed.

In the pixel structure as shown in FIG. 3, a thin film transistor (including a gate electrode, a source electrode, and a drain electrode) formed in a certain pixel region does not drive the pixel, but for convenience of explanation throughout the present specification, This is called a thin film transistor (gate electrode, source electrode, drain electrode) of the pixel.

As described above, a thin film transistor substrate for a flat panel display device, particularly a liquid crystal display device, has wirings such as gate lines and data lines for supplying signals to the pixels. However, it is easy to break or short-circuit in the manufacturing process such as the subsequent heat treatment process and etching process. If the wiring is broken, a signal necessary for the pixel cannot be applied properly, and thus, the display device cannot function properly.

On the other hand, the third help of disconnection of the gate line _{(G up, G down, 1a} , 1b) for the liquid crystal display device having a structure, a gate line _{(G up, G down, 1a} , 1b) is, but can be easily cured, When the data line D is disconnected, an image signal cannot be transmitted to the pixels below the disconnected point, and the pixel electrode 10 and the gate lines G _up , G _down , 1a and 1b are short-circuited and the gate electrode If (2) is lost or damaged, there is a problem that repair is impossible.

Various attempts have been made to solve this problem. Among them, a repair line is formed around the screen where pixels are formed in the form of a closed curve so as to cross the gate line and the data line with the gate insulating layer interposed therebetween. Then, if disconnection occurs in a specific wiring, a method may be adopted in which the wiring disconnected by the repair wire is replaced.

Next, referring to FIG. 5, a conventional matrix display device in which a repair line is formed around a screen in the form of a closed curve will be described in detail.

First as shown in Figure 5, such a matrix type display device, a plurality of linear scanning signal lines that are parallel to each other forming a horizontal _{(G 1, G 2, ......} , G m) and, parallel to this perpendicular crossing Conductive material in the form of a closed curve around an area where pixels PX formed by a plurality of linear display signal lines D ₁ , D ₂ , D ₃ , D ₄ ,..., D _2n-1 , D _2n meet The repair line RL is formed, and the repair line RL intersects each scan signal line G ₁ , G ₂ ,..., G _m once, and each display signal line D ₁ , D _2. , D ₃ , D ₄ , ……, D _2n-1 , D _2n ) intersect with each other twice from the top and bottom, the repair line (RL) and the scan signal lines (G ₁ , G ₂ , ……, G _m ) and The display signal lines D ₁ , D ₂ , D ₃ , D ₄ ,..., D _2n-1 , D _2n are formed through an insulating layer, and the intersection portion serves as a capacitor.

Next, the operation of the matrix display device will be described in detail.

Opening and closing signals are sequentially applied to the pixel 10 through a plurality of horizontally formed scan signal lines G ₁ , G ₂ ,..., G _m , and accordingly, display signal lines D ₁ , D ₂ , D ₃ , The image signals of the corresponding pixels 10 are applied through D ₄ ,..., D _2n-1 , D _2n to display.

By the way, as shown in FIG. 5, it is assumed that the display signal line D ₃ is disconnected. The disconnected point is The point marked with. In this case, since the image signal applied through the display signal line D ₃ reaches only the disconnected point and does not reach the subsequent point, the disconnection point ( ) The image signal is not applied to the pixel connected to the display signal line D ₃ or below.

Now repair it using repair line (RL) Let the signal reach the display signal line D ₃ below. To do this, the upper and lower intersections of the display signal line D ₃ and the repair line RL, denoted by Δ, are short-circuited using a laser. Open point ( When the pixel connected to the display signal line D ₃ or below is open, the signal from the input pad DP ₃ passes through the shorted upper intersection portion, and is connected to the display signal line D ₃ at the intersection portion. It moves along the repair line RL along the left path of the display signal line D ₃ , that is, the path P ₁ , or on the right path, that is, the path P ₂ . However, the path P ₂ is less efficient than passing the signal through the paths P ₁ because they intersect the long, the number of display signal lines than the number of paths P _1. Therefore, it is necessary to allow the signal to flow through only the path P ₁ and to block the signal flowing along the path P ₂ . For this purpose, the point from the short circuit point (DELTA) to the path P ₂ , that is, the portion indicated by x is cut.

In this case, the disconnection point (through the path path P ₁ of the repair line RL) A signal can be applied to the display signal line D ₃ afterward.

On the other hand, the signal applied through the path P ₁ must pass through the intersections a and a 'of the display signal lines D ₁ and D ₂ and the repair line RL. By the way, as mentioned above, the intersections a and a 'serve as capacitors, which distort the image signal traveling through the repair line RL. In particular, as the size of the screen increases and thus the number of display signal lines and scanning signal lines increases, the number of intersections on the path along which the signal travels increases, so that the number of capacitors increases and the overall capacitance also increases. As the length of the repair line RL increases, the resistance also increases. For this reason, there is a problem in that a signal moving through the repair line RL is more likely to be distorted due to an RC time delay.

In addition, the number of display signal lines D ₁ , D ₂ , D ₃ , D ₄ ,..., D _2n-1 , D _2n that can be repaired by the repair line RL is limited due to space limitation. have.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and it is possible to efficiently repair almost all signal lines and prevent short circuits and switching elements of pixel electrodes and signal lines while preventing RC time delays without increasing the number of processes or reducing the aperture ratio. The purpose is to repair defects due to the loss of the electrode.

The basic concept of the present invention for achieving the above object is based on the prior art of FIG. 3 is a double scan signal line, auxiliary to the defects caused by disconnection of the display signal line and scan signal line, short circuit of the pixel electrode and signal line, loss of the electrode of the switching element Repairing is performed using one or more of the signal line, the pixel electrode, and the switching element.

In this case, a method of modifying the structures of the auxiliary gate line and the double gate line may also be considered.

The display device according to the present invention is a matrix type display device in which a plurality of pixel areas are formed in a matrix form, and includes upper and lower first signal lines formed horizontally while forming upper and lower boundaries of each pixel area, A second signal line formed vertically between the pixel areas and insulated from and intersecting the upper and lower first signal lines, a pixel electrode formed in the pixel area and made of a transparent conductive material, and connected to the upper first signal line An opening and closing element having a first terminal connected to the second signal line, a second terminal connected to the second signal line, and a third terminal connected to the pixel electrode, and one of the upper and lower first signal lines via a first insulator; And first connection means for connecting the second signal line.

In this case, an auxiliary signal line forming a boundary of each pixel area may be further included, and the auxiliary signal line may connect the upper and lower first signal lines to each other.

The apparatus may further include second connection means for connecting the first signal line and the pixel electrode, the auxiliary signal line and the pixel electrode, or the second signal line and the pixel electrode through an insulator.

Another display device according to the present invention is a matrix type display device in which a plurality of pixel areas are formed in a matrix form, the upper left of each of the upper first pixel areas forming a boundary of the pixel areas. A left and right auxiliary signal line each having a right boundary and connected to the upper first signal line, a second signal line formed vertically between the pixel areas, and insulated from and intersecting the upper first signal line, the second signal line; A lower first signal line connecting the auxiliary signal lines on both sides of the signal line to each other, a pixel electrode formed in the pixel area and made of a transparent conductive material, and a first terminal connected to the upper first signal line and the second signal line An opening and closing element having a second terminal connected thereto and a third terminal connected to the pixel electrode, and a first insulator A first connection means for connecting the upper and lower group One of the first signal line and the second signal line. Matrix display.

Here, the display device may further include second connection means for connecting the auxiliary signal line and the pixel electrode, or the first signal line and the pixel electrode, and the second signal line and the pixel electrode through an insulator.

Another display device according to the present invention is a matrix type display device in which a plurality of pixel areas are formed in a matrix form, the lower first signal line forming a horizontal upper and lower boundary of each pixel area, Left and right auxiliary signal lines that form the left and right boundaries of the pixel areas, respectively, and connect the upper and lower first signal lines to each other, and are vertically formed between the pixel areas, and are insulated from the upper and lower first signal lines. A second signal line intersecting the second signal line, a pixel electrode formed in the pixel area and made of a transparent conductive material, a first terminal connected to the upper first signal line, a second terminal connected to the second signal line, and the pixel electrode And a switching element having a third terminal connected to and connected to one of the left and right auxiliary signal lines via a first insulator. And first connecting means for connecting the second signal line.

Here, the display device may further include second connection means for connecting the auxiliary signal line and the pixel electrode, or the first signal line and the pixel electrode, and the second signal line and the pixel electrode through an insulator.

Another display device according to the present invention is a matrix type display device in which a plurality of pixel areas are formed in a matrix form, and upper and lower first signal lines formed horizontally while forming upper and lower boundaries of each pixel area, respectively. A second signal line formed vertically between the pixel areas and insulated from and intersecting the upper and lower first signal lines, a pixel electrode formed in the pixel area and made of a transparent conductive material, and the upper first signal line An opening and closing element having a first terminal connected to the second signal line and a second terminal connected to the second signal line, and a third terminal connected to the pixel electrode, and connecting the pixel electrode and the second signal line through an insulator. Connection means.

The auxiliary signal line may further include an auxiliary signal line forming a boundary of each pixel area, and the auxiliary signal line may connect the upper and lower first signal lines to each other.

Another display device according to the present invention is a matrix type display device in which a plurality of pixel regions are formed in a matrix form, wherein the upper first signal line formed horizontally and forming a boundary of each pixel region, Left and right auxiliary signal lines respectively forming a left and right boundary and connected to the upper first signal line, vertically formed between each pixel area, and insulated from and intersecting the first signal line, both of the second signal line A lower first signal line connecting the auxiliary signal lines of the second signal line, a pixel electrode formed in the pixel region, and a first electrode connected to the upper first signal line and a first terminal connected to the upper first signal line; An opening and closing element having a second terminal and a third terminal connected to the pixel electrode, and the pixel via an insulator It includes a pole and connecting means for connecting the second signal line.

Another display device according to the present invention is a matrix type display device in which a plurality of pixel areas are formed in a matrix form, and upper and lower first signal lines formed horizontally while forming upper and lower boundaries of each pixel area, respectively. A first auxiliary signal line which forms one of the left and right boundaries of each pixel area and is separated from one of the upper and lower first signal lines and connected to the other, and is vertically formed between the pixel areas A second signal line which is insulated from and intersects the upper and lower first signal lines, a pixel electrode formed in the pixel area and made of a transparent conductive material, a first terminal connected to the upper first signal line, and the second signal line; An opening and closing element having a second terminal connected to the third electrode and a third terminal connected to the pixel electrode, and the first auxiliary device via an insulator It comprises a line connection means for connecting the second signal line.

In addition to the first auxiliary signal line, the second auxiliary signal line may further include a left and right boundary of each pixel area, and the second auxiliary signal line may connect the upper and lower first signal lines to each other.

Another display device according to the present invention is a matrix type display device in which a plurality of pixel regions are formed in a matrix form, wherein the upper first signal line formed horizontally and forming a boundary of each pixel region, A first auxiliary signal line which forms one of a left and right boundaries and is separated from the upper first signal line, and a first auxiliary signal line which is connected to the upper first signal line and forms a left and right boundary of each pixel area together with the first auxiliary signal line A second auxiliary signal line, a second signal line formed vertically between the pixel areas, insulated from and intersecting the upper first signal line, and a lower first signal line connecting the auxiliary signal lines on both sides of the second signal line; A pixel electrode formed in the pixel region and made of a transparent conductive material, a first terminal connected to the upper first signal line, and the second signal And an opening and closing element having a second terminal connected to a line and a third terminal connected to the pixel electrode, and connecting means for connecting the second auxiliary signal line and the second signal line through an insulator.

Another display device according to the present invention is a matrix type display device in which a plurality of pixel areas are formed in a matrix form, and upper and lower first signal lines formed horizontally while forming upper and lower boundaries of each pixel area, respectively. A first auxiliary signal line which forms one of the left and right boundaries of each pixel area and is separated from one of the upper and lower first signal lines and connected to the other, and is vertically formed between the pixel areas A second signal line which is insulated from and intersects the upper and lower first signal lines, a pixel electrode formed in the pixel area and made of a transparent conductive material, a first terminal connected to the upper first signal line, and the second signal line; An opening / closing element having a second terminal connected to the third electrode and a third terminal connected to the pixel electrode, and the first auxiliary signal line of the first auxiliary signal line First connecting means for connecting one end to the second signal line, and second connecting means for connecting the other end of the first auxiliary signal line and the second signal line through an insulator.

The display device may further include a second auxiliary signal line which forms another one of the left and right boundaries of each pixel area, and the second auxiliary signal line is connected to the upper first signal line.

The display apparatus may further include a lower first signal line that forms a lower boundary of each pixel area and is formed horizontally, wherein the second auxiliary signal line is connected to the lower first signal line.

At this time, it may further include a third connection means for connecting the upper and lower second auxiliary signal line via an insulator.

The substrate for a matrix type liquid crystal display according to the present invention according to the present invention is a substrate for a matrix type liquid crystal display in which a plurality of pixel regions are formed in a matrix form, the upper gate line being formed along a horizontal line, and the upper portion A lower gate line which is formed along a horizontal line at a distance from the gate line, an auxiliary gate line which connects the upper gate line and the lower gate line to form a pair, a gate electrode which is a part or a branch of the upper gate line, the upper and lower gate lines and the An auxiliary gate line, a first insulating layer formed on the entire surface to cover the gate electrode, a semiconductor layer formed on the first insulating layer to cover the gate electrode, and the neighboring auxiliary gate line on the first insulating layer A data line formed longitudinally between pairs, said half as part or branch of said data line A source electrode connected to the body layer, a data electrode connected to the semiconductor layer and separated from the source electrode, a second electrode formed on the front surface of the substrate to cover the data line, the source electrode and the drain electrode, and the first connection part; An insulating layer, and a transparent pixel electrode formed in a closed region of the upper and lower gate lines and the auxiliary gate line on the second insulating layer, wherein the drain electrode is connected to the pixel electrode above the gate electrode and is upper The gate line and the data line partially overlap each other.

In this case, the upper gate line and the data line may overlap each other by a first connection part which is a branch of the data line. At this time, the point where the upper gate line and the data line overlap is located in the upper gate line which does not form a closed area, and the point in which the first connection part is branched is located in the data line between the intersection point of the upper gate line and the lower gate line. desirable.

In addition, the gate electrode may be positioned between the intersection of the upper gate line and the data line from the intersection of the first connection portion and the upper gate line, wherein the upper gate line has a parallel portion parallel to the data line, and one of the auxiliary gate lines is connected to the lower portion of the parallel portion. Connected and the gate electrode may be located in parallel.

On the other hand, as a branch of the pixel electrode may further include a protrusion protruding out of the region formed by the upper and lower gate lines and the auxiliary gate line, and a second connection portion which is a branch of the upper gate line and overlaps with the protrusion of the pixel electrode. The point at which is branched from the upper gate line is preferably between the gate electrode from the connection point of the upper gate line and the auxiliary gate line.

Alternatively, a second connection portion protruding out of the region formed by the upper and lower gate lines and the auxiliary gate line as a branch of the pixel electrode may be overlapped with the upper gate line which does not form a closed region.

The pixel electrode preferably overlaps the upper and lower gate lines and the auxiliary gate line.

Alternatively, the overlapping of the upper gate line and the data line may be made by a third connection part which is a branch of the upper gate line.

Another matrix for a liquid crystal display device according to the present invention is a substrate for a matrix liquid crystal display device in which a plurality of pixel regions are formed in the form of a matrix, and has a gap between an upper gate line and an upper gate line formed along a horizontal line. A lower gate line formed along a horizontal line, the auxiliary gate line connecting the upper gate line and the lower gate line to form a pair, a gate electrode which is a part or branch of the upper gate line, the upper and lower gate lines and the auxiliary gate line, A first insulating layer formed on an entire surface of the first insulating layer to cover the gate electrode, a semiconductor layer formed on the first insulating layer to cover the gate electrode, and a length between the pair of adjacent auxiliary gate lines on the first insulating layer A data line formed along a portion of the data line and connected to the semiconductor layer as a part or a branch of the data line A second insulating layer formed on the front surface of the source electrode, the data electrode connected to the semiconductor layer and separated from the source electrode, and covering the data line, the source electrode, and the drain electrode. And a transparent pixel electrode formed in a closed area formed of the upper and lower gate lines and the auxiliary gate line, wherein the drain electrode is connected to the pixel electrode above the gate electrode and is one of the auxiliary gate lines. And the data line partially overlap.

In this case, the auxiliary gate line and the data line may overlap each other by a first connection part which is a branch of the data line, and the first connection part may also overlap the pixel electrode.

Preferably, the pixel electrode overlaps the upper and lower gate lines and the auxiliary gate line, and the gate electrode is positioned on the upper gate line which does not form a closed region, and in particular, a connection point of the auxiliary gate line and the upper gate line that overlaps the first connection part. Is preferably located at the upper gate line between the intersection of the upper gate line and the data line.

On the other hand, the gate line may have a parallel portion parallel to the data line and the auxiliary gate line overlapping the first connection portion may be connected to the lower portion of the parallel portion, and the gate electrode may be positioned at the parallel portion.

The drain electrode overlaps the lower gate line positioned directly under the pixel electrode connected to the drain electrode.

Alternatively, the overlapping of the auxiliary gate line and the data line may be made by a first connection part which is a branch of the auxiliary gate line.

Another substrate for a matrix type liquid crystal display device according to the present invention is a substrate for a matrix type liquid crystal display device in which a plurality of pixel regions are formed in a matrix form.

An upper gate line formed along the horizontal line,

A lower gate line which is formed along a horizontal line with an interval with the upper gate line,

A first auxiliary gate line connecting the upper gate line and the lower gate line;

One end is connected to one of the upper and lower gate lines, and the other end is open, and is paired with the first auxiliary gate line to form a part of an open area defined by the upper gate line and the lower gate line. 2 auxiliary gate lines,

A gate electrode which is part or branch of the upper gate line,

A first insulating layer formed on a front surface of the upper and lower gate lines, the auxiliary gate line, and the gate electrode;

A semiconductor layer formed on the first insulating layer to cover the gate electrode;

A data line formed vertically between the pair of neighboring auxiliary gate lines on the first insulating layer;

A source electrode connected to the semiconductor layer as part or branch of the data line,

A data electrode connected to the semiconductor layer and separated from the source electrode,

A second insulating layer formed on a front surface of the data line, the source electrode, and the drain electrode to cover the data line;

A transparent pixel electrode on the second insulating layer, the transparent pixel electrode being formed in the open area;

In this case, the drain electrode is connected to the pixel electrode above the gate electrode, and a part of the first auxiliary gate line and the data line overlap each other.

The overlap of the first auxiliary gate line and the data line may be made by a first connection part which is a branch of the first auxiliary gate line, and the gate electrode is disposed across the first auxiliary gate line with respect to the data line and on the upper gate line not forming a closed region. Located.

The overlapping point of the first connection portion and the data line may be positioned at the data line between the branch point of the source electrode at the intersection point of the upper gate line.

The pixel electrode may overlap the upper and lower gate lines and the auxiliary gate line, and the pixel electrode may not overlap the auxiliary gate line between the intersection point with the upper gate line at the branch point of the first connector.

The drain electrode overlaps the lower gate line positioned directly below the pixel electrode connected to the drain electrode, and one open end of the second auxiliary gate line is positioned at a connection point between the pixel electrode and the drain electrode.

Another matrix for a liquid crystal display device according to the present invention is a substrate for a matrix liquid crystal display device in which a plurality of pixel regions are formed in the form of a matrix, and has a gap between an upper gate line and an upper gate line formed along a horizontal line. A lower gate line formed along a horizontal line, a first auxiliary gate line connecting the upper gate line and the lower gate line, one end of which is connected to one of the upper and lower gate lines, and the other end of which is open A second auxiliary gate line paired with the first auxiliary gate line to form a part of an open area defined by the upper gate line and the lower gate line, a gate electrode which is a part or a branch of the auxiliary gate line, and the upper and lower gate lines A first insulating layer formed on a front surface of the auxiliary gate line to cover the gate electrode; A semiconductor layer formed on the first insulating layer so as to cover the pole; a data line formed vertically between the pair of adjacent auxiliary gate lines on the first insulating layer; and the semiconductor layer as a part or branch of the data line. A second insulating layer formed on a front surface of the source electrode connected to the source electrode, the data electrode connected to the semiconductor layer and separated from the source electrode, the data line, the source electrode, and the drain electrode; A transparent pixel electrode is formed on the insulating layer in the open area. The drain electrode is connected to the pixel electrode above the gate electrode, and the open end of the second auxiliary gate line overlaps the data line.

Here, the overlapping of the second auxiliary gate line and the data line may be made by a first connection part which is a branch of an open end of the second auxiliary gate line.

In this case, the pixel electrode overlaps the second auxiliary gate line and the data line, but preferably does not overlap both ends of the second auxiliary gate line. In addition, the pixel electrode may overlap the upper and lower gate lines and the first auxiliary gate line.

The display device may further include a second connection part formed on the insulating layer and formed to cover the data line between the overlapping point with the first connection part at an intersection point of the second auxiliary gate line and the gate line connected to the second auxiliary gate line.

In this case, it is preferable that the connection point between the second auxiliary gate line and the gate line is the same position as the intersection of the gate line and the data line connected with the second auxiliary gate line.

Another matrix for a liquid crystal display device according to the present invention is a substrate for a matrix liquid crystal display device in which a plurality of pixel regions are formed in the form of a matrix, and has a gap between an upper gate line and an upper gate line formed along a horizontal line. And a lower gate line formed along a horizontal line, a first auxiliary gate line connecting the upper gate line and the lower gate line, and both ends of the lower gate line are open, and are paired with the first auxiliary gate line to form the upper gate line and the lower gate. A second auxiliary gate line forming a part of an open area defined by a line, a gate electrode which is a part or a branch of the upper gate line, and a first first surface formed to cover the upper and lower gate lines and the auxiliary gate line, and the gate electrode An insulating layer, a semiconductor layer formed on the first insulating layer to cover the gate electrode, the first A data line formed vertically between the pair of neighboring auxiliary gate lines on a soft layer, a source electrode connected to the semiconductor layer as a part or branch of the data line, and connected to the semiconductor layer and separated from the source electrode Wherein a second insulating layer is formed on the front surface to cover the data electrode, the data line, the source electrode, and the drain electrode, and a transparent pixel electrode formed in the open area on the second insulating layer. The drain electrode is connected to the pixel electrode above the gate electrode, and both open ends of the second auxiliary gate line overlap each other with the data line.

Here, the overlapping of the second auxiliary gate line and the data line may be made by the first connection part and the second connection part which are branches of both open ends of the second auxiliary gate line.

In this case, the second auxiliary gate line adjacent to each other preferably further includes a third connecting portion overlapping both ends, and the third connecting portion is formed on the first insulating layer, and may be formed of a double layer of a metal layer and an ITO layer. It may be formed on the second insulating layer.

The pixel electrode preferably overlaps the second auxiliary gate line at portions except both ends of the second auxiliary gate line, and may also overlap the upper and lower gate lines and the first auxiliary gate line.

On the other hand, the overlap between the open ends of the second auxiliary gate line and the data line is formed by the first connection part and the second connection part which are two branches of the data line, or as long as the first connection part which is one branch of the data line is open of the second auxiliary gate line. A second connection part which overlaps an end and is a branch of another open end of the second auxiliary gate line may be overlapped with the data line.

Another substrate for a matrix type liquid crystal display device according to the present invention is a substrate for a matrix type liquid crystal display device formed in the form of a plurality of pixel matrices, and is horizontally spaced apart from an upper gate line and an upper gate line formed along a horizontal line. A lower gate line formed along the lower gate line; an auxiliary gate line connected to the lower gate line at two places and forming a closed region together with the lower gate line; a bridge connecting the upper gate line and the upper gate line; a part of the upper gate line Or a branched gate electrode, a first insulating layer formed on the front surface to cover the upper and lower gate lines, the auxiliary gate line, the legs, and the gate electrode, and formed on the first insulating layer to cover the gate electrode. A semiconductor layer, between the pair of neighboring auxiliary gate lines over the first insulating layer A data line formed along a furnace, a source electrode connected to the semiconductor layer as part or branch of the data line, a data electrode connected to the semiconductor layer and separated from the source electrode, the data line, and the source electrode And a transparent pixel electrode formed in a closed region formed on the entire surface of the second insulating layer so as to cover the drain electrode, the lower gate line and the auxiliary gate line formed on the second insulating layer, wherein the drain electrode is a gate electrode. The auxiliary gate line and the data line are partially overlapped with each other.

Here, the overlapping of the auxiliary gate line and the data line may be made by a first connection part which is a branch of the auxiliary gate line.

In this case, the display device may further include a second connection part formed on the first insulating layer or the second insulating layer and overlapping the bridge or auxiliary gate line disposed under the lower gate line and the lower gate line.

In this case, the pixel electrode may be formed to overlap the auxiliary gate line and the lower gate line.

Alternatively, the overlapping of the auxiliary gate line and the data line may be made by the first connection part which is a branch of the data line.

Next, the basic concept and operation of the present invention will be described with reference to the accompanying drawings with reference to FIGS. 6 to 15. However, since the present invention mainly repairs the second signal line or the data line, both the double gate line (or first signal line) structure and the ring capacitor structure presented in the prior art may be employed as they are. It should be noted that only one structure may be adopted, or it may be modified. Here are some examples.

The first type is the case where both the double gate line structure and the ring capacitor structure are adopted.

The second type is a case where only the double gate line structure is adopted, and the auxiliary gate lines 1a and 1b are omitted in FIG.

The third type is a case in which only the ring capacitor structure is adopted, and the lower gate line G _down which does not form the ring capacitor is omitted in the structure of FIG. At this time, there is no practical advantage to prepare the auxiliary gate lines 1a and 1b and the remaining lower gate line G _down .

The fourth type is a structure in which only the lower gate line G _down constituting the annular capacitor is omitted in the structure of FIG. Here, of course, there is little profit to distinguish the auxiliary gate lines 1a and 1b from the remaining lower gate line G _down , but the remaining lower gate line G _down serves as an electrode and a light shielding layer of the storage capacitor. In that it does not.

In the fifth type, the lower gate line G _down may be omitted in the structure of FIG. 3. In this case, it is impossible to cure the disconnection of the gate lines G _up and G _down by themselves, and the auxiliary gate line may be regarded as a capacitor or a light shielding layer.

The sixth type omits one of the auxiliary gate lines 1a and 1b in the structure of FIG. 3, or one or both of the auxiliary gate lines 1a and 1b are connected to the upper gate line G _up and the lower gate line G _down . It may be isolated from either or both. Auxiliary gate line (1a, 1b) a top or bottom gate lines (G _up, G _down) if it is in connection with any one has an electrode serving as the addition to the role of the light-shielding layer capacitors, however, the two gate lines (G _up, G _down ) serves as a light shielding layer when separated from both. This type can coexist with the previous five types.

First, a case in which the second signal line D and the upper first signal line G _up are connected to each other by a capacitor C _R as shown in FIGS. FIG. 6 is a first type employing both a double gate line structure and a ring-shaped tuxedo structure, and FIG. 6 is a second type omitting the auxiliary signal lines 1a and 1b (here, only one of the auxiliary signal lines is shown. 6 may be omitted. In this case, FIG. 6C is a fourth type in which only the lower first signal line G _down constituting the annular capacitor is omitted, and two auxiliary signal lines 1a are used for signal transmission of the first signal line. , 1b) are all required.

Then consider the repair method in the case of FIG.

As shown in FIG. 7, the second signal line between the intersection point b of the upper first signal line G _up and the second signal line D and the connection point e of the capacitor C _R and the second signal line D When D) is disconnected (a), the second signal line D and the upper first signal line G _up are shorted (b), and both terminals of the capacitor C _R are shorted (d), and then the upper first When the upper first signal line G _{up at} both the connection point c and the short circuit point b of the signal line G _up and the capacitor C _R is disconnected (f, g), it flows along the second signal line D. The signal bypasses the disconnection point a and proceeds to the second signal line D again through the upper first signal line G _up and the shorted capacitor C _R.

In this case, however, the second signal line D between the intersection point b of the upper first signal line G _up and the second signal line D and the connection point e of the capacitor C _R and the second signal line D. Repair is possible only if) is disconnected (a).

6 a and c can be repaired in the same manner, but in FIG. 6 c, both auxiliary signal lines 1a and 1b are required for signal transmission of the first signal lines G _up and G _down .

The second signal line D and the lower first signal line G _down may be similarly connected to each other by a capacitor.

Next, consider the case where the second signal line D and the auxiliary signal line 1 b are connected by the capacitor C _{R as} shown in FIG. Here, the auxiliary signal line 1a that is not connected to the second signal line D and the capacitor C _R may be omitted.

Then consider how to repair it.

9, the second signal line between the connection point f of the capacitor C _R and the second signal line D at the intersection point b of the upper first signal line G _up and the second signal line D as shown in FIG. When (D) is disconnected (a), the second signal line (D) and the upper first signal line (G _up ) are shorted (b), and both terminals of the capacitor (C _R ) are shorted (e), and then the upper a first signal line (g _up) and a connection point (c) and short-circuit point (b) an upper first signal line (g _up) of both ends of the auxiliary signal line (1b) disconnection (g, h) and the auxiliary signal line (1b) and a capacitor (c _When the auxiliary signal line 1b below the connection point d of _R ) is cut out, the signal flowing along the second signal line D is avoided from the disconnection point a and thus the upper first signal line G _up and the auxiliary signal line 1b. The capacitor C _R is shorted to proceed to the second signal line D again.

Next, as shown in FIG. 9B, the second point between the intersection of the lower first signal line G _down and the second signal line D at the connection point b of the capacitor C _R and the second signal line D is shown in FIG. 2 If the signal line (D) is disconnected (a), short-circuit (c) both terminals of the capacitor (C _R ), short-circuit (f) the second signal line (D) and the lower first signal line (G _down ), and The auxiliary signal line 1b on the connection point d of the auxiliary signal line 1b and the capacitor C _R is cut out, and the connection point e and the short point f of the lower first signal line G _down and the auxiliary signal line 1b are cut out. When both lower first signal lines G _down are disconnected (h, i), signals flowing along the second signal line D are short-circuited to avoid the disconnection point a and the capacitor _CR and the auxiliary signal lines 1b. ) And the upper first signal line G _up to the second signal line D again.

In this case, all disconnections of the second signal line between the intersection with the upper first signal line and the intersection with the lower first signal line can be repaired.

On the other hand, even if there is no auxiliary signal line (1a) that is not connected to the second signal line (D) and the capacitor (C _R ), the signal of the first signal line (G _up , G _down ) can be transmitted and can be omitted.

Next, consider the case where the second signal line D and the pixel electrode 10 are connected by a capacitor C _R as shown in FIGS. As described above, the pixel electrode 10 is connected to one terminal of the switching element S, and the other two terminals of the switching element S are connected to the upper first signal line G _up and the second signal line D, respectively. It is connected. Here, FIG. 10A, the first type employing both the double gate line structure and the annular capacitor structure, and FIG. 10B, in which only the second type double gate line structure is adopted, wherein only one of the auxiliary signal lines 1a and 1b is used. May be omitted, which is the sixth type], and there may be three cases of FIG. 10C in which the lower first signal line constituting the annular capacitor is omitted.

Then, look at the repair method in the case of FIG.

As shown in FIG. 11, the second signal line between the second signal line D and the connection point h of one terminal of the switching element S at the connection point b of the second signal line D and the capacitor C _R ( When D) is disconnected (a), short-circuits (c) both terminals of the capacitor (C _R ), short-circuits (f) the three terminals of the switching element (S), and then the switching element (S) and the upper first signal line. (g _up) and a connection point (g) an upper first signal line of each side (g _up) disconnection (i, j) when the second signal line (D) flowing signals, avoiding short-circuit the capacitor only parked (a) along the The signal flows back to the second signal line D through the C _R , the pixel electrode 10, and the short-circuit opening / closing element S.

In this case, however, the second signal line D between the second signal line D and the connection point h of one terminal of the switching element S at the connection point b of the second signal line D and the capacitor C _R. Repair is only possible if) is disconnected (a).

In the case of FIG. 10, b and c can be repaired in the same manner.

The following examples show the sixth type of modification of the structure of the auxiliary signal line.

First, as shown in FIGS. 12A and 12B, one end of the auxiliary signal line 1a is separated from the upper first signal line G _{up and} connected to the second signal line D and the capacitor C _R. Here, FIG. 12A is combined with the first type, FIG. 12B is the fourth type, and the remaining auxiliary signal lines 1b not separated from FIGS. 12A and 12 may be omitted.

Then, consider the repair method in the case of FIG.

As shown in FIG. 13, the second signal line D between the second signal line D, the lower first signal line G _down , and the intersection point e at the connection point b with the second signal line D and the capacitor C _R. When D) is disconnected (a), the both terminals of the capacitor C _R are shorted (c), the second signal line D and the lower first signal line G _down are shorted (e), and then the lower signal line ( When the lower first signal line G _{down at} both the connection point d and the short point e of the G _down ) and the capacitor C _R is disconnected (f, g), the signal flowing along the second signal line D is In order to avoid the disconnection point (a), the circuit proceeds to the second signal line D again through the shorted capacitor C _R and the lower first signal line G _down .

In this case, however, the second signal line between the second signal line D and the intersection point e between the second signal line D and the lower first signal line G _down at the connection point b of the second signal line D and the capacitor C _R ( Repairs can only be made if D) is broken (a).

The repair method is the same also in the case of FIG.

Similarly, when one end of the auxiliary signal line 1a is separated from the lower first signal line G _{down and} connected to the second signal line D by a capacitor.

Next, as shown in Figs. 14A to D, consider the case where both ends of the auxiliary signal line 1a are connected to the second signal line D and the capacitors C _R1 and C _R2 , respectively. In this case, since only one auxiliary signal line 1a can be repaired, various changes are possible. For example, in the basic modification of FIGS. 14A to 14D, the auxiliary signal line 1a is the upper and lower first signal lines G _up. , G _down ), combined with the first, third, fourth, and fifth types.

In addition, the structure in which the last auxiliary signal line 1b is omitted or one of the upper or lower first signal lines G _up and G _down is omitted, and in FIG. 14, the auxiliary signal line 1a is replaced by the upper first signal line G _up. , G _down ) and / or a myriad of variations, such as structures connected to the lower signal line G _down .

In the case of such a modification, repair may be possible by other methods, but the repair method will be described only in the case of the typical example of FIG.

A second signal line (D) between the connection point (e) a second signal line, as in the 15 degree (D) and the capacitor (C _R1) in the connection point (b) second signal line (D) and the capacitor (C _R) in the In the case of disconnection (a), if both terminals C _R1 and C _R2 are shorted (c, d), the signal flowing along the second signal line (D) is shorted to avoid the disconnection point (a). The process proceeds to the second signal line D again through C _R1 and C _R2 .

In this case, however, a second signal line (D) and the capacitor a second signal line (D) is broken between the (C _R1) in the connection point (b) in the second signal line (D) and a connection point (e) of the capacitor (C _R2) Repairs may only be made in (a).

The same applies to FIG. 14 in the case of b to d.

Various repair structures can be made by combining the basic structures as described above, and the following embodiments are structures that can be repaired to remove all disconnections of the second signal lines by combining, modifying, or adding other structures. Here, as a structure to be added, a structure in which two points of the second signal line, or two points to be connected are connected by a capacitor may be considered.

Next, embodiments of the matrix display device according to the present invention will be described in detail below with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

First, the first embodiment of the present invention is based on the basic structures shown in FIGS. 6 and 10, and includes a means for connecting a data line and an upper gate line and a means for connecting a gate line and a pixel electrode. It is to heal the defect of goodness. In order to connect the data line and the upper gate line through the insulator, it is possible to have the branch of the data line extend toward the upper gate line or the branch of the upper gate line extend toward the data line, but when the branch of the upper gate line extends toward the data line, It is preferable to branch the data line because it may be shorted to other gate lines in the circuit. In addition, in order to connect the gate line and the pixel electrode through an insulator, the pixel electrode is formed to overlap the gate line, or in addition or alternatively, the pixel electrode is formed to protrude out of the closed area formed of the gate line, and then the protruding portion is closed. It may be overlapped with the upper gate line which does not form an area, or the branch of the upper gate line may be overlapped with the protruding portion. In the latter case, it is necessary to leave enough space for the protrusions to form.

This will be described in detail with reference to FIGS. 16 and 17 a to 17 b.

FIG. 16 is a plan view illustrating a pixel structure of a matrix liquid crystal display substrate according to a first embodiment of the present invention, and FIGS. 17A and 17B illustrate data lines of a substrate for a liquid crystal display device according to a first embodiment. This is a diagram showing a repair method when disconnected.

As shown in FIG. 16, in the matrix liquid crystal display substrate according to the first embodiment of the present invention, the first connection portion 11, which is a branch of the data line D, is formed of the upper gate line G _up . a second vertical portion (G _v2) towards the extended second longitudinal section (G _v2) and superimposed, and some of the upper and lower gate lines of the pixel electrode _{(10) (G up, G} down) on the left and the right auxiliary gate Out of the closed area consisting of the lines 1a and 1b, it protrudes into a recess formed by the first vertical portion G _v1 , the second vertical portion G _v2 and the second vertical portion G _{v2 of the} upper gate line. The second connection part 12, which is a branch from the second vertical part G _v2 , extends toward the protrusion of the pixel electrode 10 and overlaps the pixel electrode 10. Here, the overlapping point of the first connecting portion 11 and the second vertical portion G _v2 is located under the gate electrode 2, and the first connecting portion 11 and the second vertical portion G _{v2 are each} disposed in the fourth portion. The gate oxide film 3 and the gate insulating layer 4 shown in the figure are sandwiched between the second connection portion 12 and the pixel electrode 10. The gate oxide film 3 and the gate insulating layer shown in FIG. (4) and the protective film 9 are interposed. In addition, the source electrode 7 and the gate electrode 2, the gate electrode 2 and the drain electrode 8 are also formed to overlap each other. The other part is similar to the structure of FIG. 3 and FIG.

In the case where the data line becomes defective in the liquid crystal display device according to the present exemplary embodiment, the repair method will be divided according to the disconnected position.

First, as shown in FIG. 17A, when the middle portion of the data line D is disconnected, that is, from below the branch point of the first connection part 11 of a certain pixel PX1, the pixel PX2 below it. Consider a case in which the data line 6 between the branch points of the source electrode 7 is broken (a) so that the data signal cannot be transmitted to the lower portion thereof. Arrows in the figure indicate the flow of signals.

In this case, the pixel electrode 10 of the disconnected pixel PX1 is used as a substitute for the disconnected data line.

Once the intersection point b between the first connection portion 11 and the second vertical portion G _v2 , which is located above the disconnection point a of the data line D, is short-circuited using a laser, the data line ( The data signal flowing along D) flows to the second vertical portion G _v2 through the first connecting portion 11 without facing the disconnection point a.

Subsequently, the intersection c of the second connection part 12 and the pixel electrode 10 is short-circuited with a laser, and the second vertical part G _{v2 below} the second connection part 12 is disconnected (f, g). Then, the data signal flowing into the second vertical portion G _v2 flows to the pixel electrode 10 through the second connection portion 12 and again drains the lower pixel PX2 connected to the pixel electrode 10. To the electrode 8.

Next, the drain electrode 8 and the gate electrode 2, the gate electrode 2 and the source electrode 7 of the lower pixel PX2 are short-circuited d and e, respectively, and the gate electrode of the lower pixel PX2 ( 2) Kneel down the upper gate line (G _up ) (h, i). The data signal then moves to the data line D through the drain electrode 8, the gate electrode 2, and the source electrode 7 of the lower pixel PX2.

As a result, the data signal flows through the first connection part 11, the second vertical part G _v2 , the second connection part 12, and the pixel electrode 10 of the disconnected pixel PX1, and drains the lower pixel PX2. It returns to the data line D via the electrode 8, the gate electrode 2, and the source electrode 7.

In this case, the gate signals applied to the right-side pixels PX3 and PX4 of the disconnected pixel PX1 and the lower pixel PX2 are transmitted to the right pixel only through the lower gate line G _down , and the disconnected pixel PX1. The gate electrode 2 is applied with the gate signal from the upper gate line G _up of the right pixel PX3, and the gate signal is not applied to the gate electrode 2 of the lower pixel PX2.

Here, the disconnected pixel PX1 becomes a defect, but is hardly noticeable since the data signal is continuously applied.

Next, as shown in FIG. 17B, the data line D between the branch point of the source electrode 7 of the certain pixel PX2 and the branch point of the first connection portion 11 is disconnected (a) so that a signal is placed thereunder. Consider the case of not passing. This arrow in the figure shows the flow of the signal.

In this case, unlike the foregoing, only the thin film transistor, the second vertical portion G _v2 , and the first connection portion 11 are used to repair the defect.

The source electrode 7 and the gate electrode 2, which are located above the disconnection point a of the data line D, are short-circuited b by using a laser. The data signal flowing along the data line 6 then flows through the source electrode 7 to the gate electrode 2 without going to the disconnection point a. The upper gate line G _up on the gate electrode 2 is cut (e) so that this data signal does not flow to the gate line of the right pixel PX4.

Subsequently, when the second vertical portion G _v2 and the first connection portion 11 are shorted (c) and the second vertical portion G _v2 of the upper gate line G _up below the shorted point c is cut off. , The data signal flows to the data line D through the second vertical portion G _v2 .

As a result, the data signal is again transmitted from the data line D via the source electrode 7, the gate electrode 2, the second vertical portion G _v2 , and the first connection portion 11 of the disconnected pixel PX2. Can flow to line (D).

The upper pixel PX1 of the disconnected pixel PX2 becomes a defect because no signal is applied thereto. However, when the gate electrode 2 and the drain electrode 8 of the disconnected pixel PX2 are shorted, the upper pixel PX1 is shorted. The data signal is always applied to the pixel electrode 10 of the pixel electrode 10, so that the pixel electrode 10 is not easily seen.

The second embodiment of the present invention is based on the basic structures shown in FIGS. 8 and 10, and is provided with a fixing means for connecting the data line and the auxiliary gate line, and the data line and the pixel electrode to repair the defect of the data line. . In this case, in order to connect the data line and the auxiliary gate line through the insulating layer, the branch of the data line may extend toward the auxiliary gate line or the branch of the auxiliary gate line may extend toward the data line. In this embodiment, the former case is selected. . In addition, in order to connect the data line and the pixel electrode through an insulator, a branch of the pixel electrode may be extended out of the closed region formed of the gate line to overlap the data line, or the branch of the data line may be overlapped with the pixel electrode. However, since the pixel electrode has a higher resistance than the data line, it is preferable to branch the data line. In this case, in order for the branching of the data line to overlap the pixel electrode, the branching line of the data line must overlap with the gate line defining the pixel electrode. Therefore, it is preferable to overlap the auxiliary gate line and the pixel electrode by using one data line branching.

This will be described in detail with reference to FIGS. 18 and 19 a to 19 c.

18 is a plan view illustrating a pixel structure of a matrix liquid crystal display substrate according to a second embodiment of the present invention, and FIGS. 19A to 19C are substrates for a liquid crystal display device according to the second embodiment. Is a diagram illustrating a repair method when the data line is disconnected.

As shown in FIG. 18, in the matrix liquid crystal display substrate according to the second embodiment of the present invention, the connecting portion 21, which is a branch of the data line D, extends toward the pixel electrode 10, and thus the right auxiliary gate. It overlaps with the line 1b and the pixel electrode 10. In this case, the connecting portion 21 must extend sufficiently toward the pixel electrode 10 so that only the connecting portion 21 and the pixel electrode 10 overlap each other, and the pixel electrode 10 is connected to the right auxiliary gate line 1b. Since they overlap, the intersection of the connecting portion 21 and the right auxiliary gate line 1b overlaps the pixel electrode 10. Here, the connecting portion 21 and the right auxiliary gate line 1b are interposed between the gate oxide film 3 and the gate insulating layer 4 of FIG. 4, and the connecting portion 21 and the pixel electrode 10 of FIG. The protective film 9 is interposed. The other part is similar to the structure of FIG. 3 and FIG.

Then, when the data line is defective in the matrix type liquid crystal display substrate as in the present embodiment, the repair method will be divided according to the disconnected position.

First, as shown in Figs. 19A and B, the portion between the point where the connection portion 21 of the upper pixel PX1 splits in the data line D and the point where the source electrode 7 of the lower pixel PX2 splits. Consider the case where this disconnection (a) prevents data signals from being transmitted below it. Arrows in the figure indicate the flow of signals.

In this case, it may be repaired using the right auxiliary gate line 1b of the above pixel PX1 or may be repaired using the pixel electrode 10.

First, a repairing method using the right auxiliary gate line 1b of the pixel PX1 will be described with reference to FIG. 19A.

An intersection point (b) between the connection portion 21, which is located above the disconnection point a of the data line D, the right auxiliary gate line 1b, and the pixel electrode 10 is short-circuited using a laser and a short circuit point (b) The upper right auxiliary gate line 1b is cut out (f). At this time, the pixel electrode 10, the right auxiliary gate line 1b, and the connecting portion 21 are simultaneously shorted at the short point b, so that there is a possibility that gate line and data line defects may occur, but in fact, the right auxiliary gate Due to the battery effect between the line 1b and the pixel electrode 10, the right auxiliary gate line 1b of the shorting point b is oxidized, so that the right auxiliary gate line 1b and the pixel electrode 10 are oxidized. In addition to being insulated by itself, since the contact resistance of ITO, which is a material forming the pixel electrode 10, is greater than that of the right auxiliary gate line 1b and the data line D, the data signal is not transmitted to the pixel electrode 10. Since the pixel PX becomes a defect anyway, even if the data signal is continuously applied, the pixel PX is not easily seen.

Therefore, the data signal flowing along the data line D is directed to the right auxiliary gate line 1b of the pixel PX1 above through the connecting portion 21 and not to the disconnection point a, and to the right auxiliary gate line 1b. It flows along the lower gate line (G _down ) connected to.

Subsequently, an intersection c of the lower gate line G _down of the upper pixel PX1 and the pixel electrode 10 and the drain electrode 8 of the lower pixel PX2 is shorted to a gamer and left to the left of the intersection c. The lower gate line G _down and the lower gate line G _{down on the} right of the point where the lower gate line G _down and the right auxiliary gate line 1b meet are disconnected (g, h). In this case, however, a similar problem may occur as in the short-circuit point b, but there is no big problem for the reason as described above. As a result, the signal flowing to the lower gate line G _down of the upper pixel PX1 flows along the drain electrode 8 of the lower pixel PX2.

Again, the drain electrode 8 and the gate electrode 2, the gate electrode 2 and the source electrode 7 of the lower pixel PX2 are short-circuited d and e, and the upper gate line above and below the gate electrode 2 is formed. When (G _up ) is disconnected (i, j), the data signal returns to the data line D again.

As a result, the data signal passes through the connection portion 21 of the upper pixel PX1, the right auxiliary gate line 1b, and the lower gate line G _down , and the drain electrode 8 and the gate electrode 2 of the lower pixel PX2. ) And flows back to the data line D via the source electrode 7.

In this case, the gate signal applied to the right pixel PX3 of the disconnected pixel PX1 is transmitted to the right pixel PX3 only through the upper gate line G _up , and the pixel PX2 below the disconnected pixel PX1. The gate signal applied to the right pixel PX4 of is transferred to the right pixel only through the lower gate line G _down , and no gate signal is applied to the gate electrode 2 of the lower pixel PX2.

Next, as shown in FIG. 19B, as in the case of FIG. 19A, the source electrode of the lower pixel PX2 at the point where the connection part 21 of the upper pixel PX1 splits in the data line D is formed. Consider a method of repairing a defect using the pixel electrode 10 when the part between the points where 7) splits is disconnected (a) so that the data signal cannot be transmitted to the part below it. Arrows in the figure indicate the flow of signals.

When the intersection point b between the connecting portion 21 and the pixel electrode 10 positioned above the disconnection point a of the data line D is shorted by using a laser, data flowing along the data line D is generated. The signal flows to the pixel electrode 10 of the pixel PX1 through the connecting portion 21 without going to the disconnection point a, and flows to the drain electrode 8 of the lower pixel PX2 connected to the pixel electrode 10.

The drain electrode 8, the gate electrode 2, the gate electrode 2, and the source electrode 7 of the lower pixel PX2 are shorted (c, d), and the upper gate line G above and below the gate electrode 2 is applied. _{When up} ) is disconnected (e, f), the data signal returns to the data line D again.

As a result, the data signal passes through the connection part 21 and the pixel electrode 10 of the upper pixel PX1 and passes through the drain electrode 8, the gate electrode 2, and the source electrode 7 of the lower pixel PX2. Flow back to line (D).

In this case, the gate signal applied to the right pixel PX4 of the lower pixel PX2 is transmitted to the right pixel only through the lower gate line G _down , and the gate signal is provided to the gate electrode 2 of the lower pixel PX2. Not authorized

Here, the pixel PX1 becomes a defect, but the data signal is always applied to the pixel electrode 10 so that the pixel PX1 is not easily seen.

Finally, as shown in FIG. 19C, the portion between the point where the connection portion 21 splits at the point where the source electrode 7 of the pixel PX2 splits in the data line D is disconnected a so that the portion below it is separated. Consider the case where a data signal is not transmitted to the receiver. Arrows in the figure indicate the flow of signals.

The intersection point (b) of the data line (D) and the upper gate line (G _up ), which is located above the disconnection point (a) of the data line (D), is shorted or the source electrode (7) and the gate electrode (2) are shorted. (B '), and cuts the upper gate line G _up and the second horizontal portion G _h1 to the right of the intersection point b (d, e). Then, the data signal is directed toward the auxiliary gate line 1b coming from under the second vertical portion G _v2 .

Next, the intersection c between the connecting portion 21 and the pixel electrode 10 is short-circuited using a laser, and the right auxiliary gate line 1b under the cutout is cut off, and flows along the right auxiliary gate line 1b. The data signal enters the data line D again. In this case, however, similarly to the above, the pixel electrode 10, the lower gate line G _down , and the drain electrode 8 are simultaneously short-circuited at the short-circuit point c, so that gate line and data line defects may occur. This is not a big problem for the same reasons as before.

As a result, the data signal flows back through the connection portion 21 to the data line D via the gate electrode 2, the second vertical portion G _v2 , and the right auxiliary gate line 1b.

In this case, the gate signal applied to the right pixel PX4 of the disconnected pixel PX2 is transmitted to the right pixel PX4 only through the lower gate line G _down , and the gate electrode 2 of the disconnected pixel PX2 is provided. ), No gate signal is applied.

The upper pixel PX1 of the disconnected pixel PX2 becomes a defect because no signal is applied thereto. However, when the gate electrode 2 and the drain electrode 8 of the disconnected pixel PX2 are shorted, the upper pixel PX1 is shorted. The data signal is always applied to the pixel electrode 10 of the pixel electrode 10, so that the pixel electrode 10 is not easily seen.

The third embodiment of the present invention is based on the structure of FIG. 8, and has a connecting means for connecting the auxiliary gate line and the data line and a means for connecting the drain electrode and the lower gate line to repair the defect of the data line. In this case, in order to connect the data line and the auxiliary gate line through the insulating layer, it is possible to cause the branch of the data line to extend toward the auxiliary gate line or the branch of the auxiliary gate line to extend toward the data line. In addition, since the drain electrode overlaps the lower gate line, it is not necessary to create another structure.

This will be described in detail with reference to FIGS. 20 and 21 a and b.

FIG. 20 is a plan view illustrating a pixel structure of a matrix liquid crystal display substrate according to a third exemplary embodiment of the present invention, and FIGS. 21A and 21B show data lines of the liquid crystal display substrate according to the third exemplary embodiment. In the case of disconnection, it is a view showing a repair method.

As shown in FIG. 20, in the matrix liquid crystal display substrate according to the third embodiment of the present invention, the connecting portion 31, which is a branch of the left auxiliary gate line 1a, is directed toward the left data line D. As shown in FIG. It extends and overlaps with the branch point of the source electrode 7. At this time, an important point is that in order to repair all the disconnection of the data line D, the connection part 31 must overlap especially at the branching point of the source electrode 7 or above. The pixel electrode 10 overlaps the left auxiliary gate line 1a, but overlaps the left auxiliary gate line 1a from the connection point with the upper gate line G _{up to} the branch point of the connection part 31. This is to prevent the pixel electrode 10 from being damaged when the part is disconnected. On the other hand, the data line D and the connection part 31 sandwich the gate oxide film 3 and the gate insulating layer 4 of FIG. In addition, the right auxiliary gate line 1b is not connected to the lower gate line G _down , but is bent and overlapped to the point where the drain electrode 8 and the pixel electrode 10 are connected. The other parts are similar to the structures of FIGS. 3 and 4.

Then, when the data line is defective in the liquid crystal display substrate as in the present embodiment, the repair method will be divided according to the disconnected position.

First, as shown in FIG. 21A, the data line D between an overlapping point b with the connecting portion 31 or a branching point b of the source electrode 7 and an intersection point c with the lower gate line G _down . Consider a case where) is disconnected (a) so that a data signal cannot be transmitted below. Arrows in the figure indicate the flow of signals.

When the intersection point b of the data line D and the connecting portion 21, which is located above the disconnection point a of the data line D, is shorted by using a laser, the left auxiliary gate line of the right pixel PX3 ( The data signal enters 1a). Again, when the portion above the point where the connection portion 31 splits from the left auxiliary gate line 1a is cut off (d), the data signal flows along the left auxiliary gate line 1a to the lower gate line G _down .

Subsequently, the intersection c of the lower gate line G _down and the data line D of the disconnected pixel PX1 is short-circuited with a laser, and the lower gate line G _{down to the} left of the short circuit point c and the right side The lower gate line G _{down on the} right side of the connection point with the left auxiliary gate line 1b of the pixel PX3 is disconnected (e, f). Then, the data signal enters the data line D again through the short point c.

As a result, the data signal flows back to the data line D via the connection part 31 of the right pixel PX3, the left auxiliary gate line 1a, and the lower gate line G _down .

Next, as shown in FIG. 21B, when the portion between the branch points of the source electrode 7 below it at the intersection of the lower gate line G _down is disconnected a and a data signal cannot be transmitted to the portion below it. Let's consider how to repair the defect. Arrows in the figure indicate the flow of signals.

An intersection (b) of the data line (D) and the lower gate line (G _down ), which is located above the disconnection point (a) of the data line (D), is short-circuited using a laser, and the right side of the short-circuit point (b) When the lower gate line G _down is cut out (f), the data signal flowing along the data line D does not go to the disconnection point a but is left along the lower gate line G _down through the short point b. Flows into.

Subsequently, an intersection c between the drain electrode 8 of the lower pixel PX2 and the lower gate line G _down connected to the pixel electrode 10 of the upper pixel PX1 is shorted, and the lower gate line (left) When G _down ) and the auxiliary gate line 1a are disconnected (g, j), the data signal flows along the drain electrode 8 through the short point c. In this case, however, the pixel electrode 10, the lower gate line G _down , and the drain electrode 8 may be simultaneously shorted at the short point c to cause gate line and data line defects. This is not a problem for the reasons described in.

Next, when the drain electrode 8 and the gate electrode 2, the gate electrode 2 and the source electrode 7 of the lower pixel PX2 are shorted, and the upper gate line G _up of both transistors is cut off, the data The signal flows from the drain electrode 8 to the data line D via the gate electrode 2 and the source electrode 7.

As a result, the data signal passes through the lower gate line G _down of the upper pixel PX1, the drain electrode 8 of the lower pixel PX2, the gate electrode 2, and the source electrode 7. Flows along.

In this case, the gate signal applied to the right pixel PX4 of the lower pixel PX2 is transmitted to the right pixel only through the lower gate line G _down , and the gate signal is provided to the gate electrode 2 of the lower pixel PX2. Not authorized

A fourth embodiment of the present invention is based on the basic structure of FIG. 14, which comprises means for separating one auxiliary gate line from the upper and lower gate lines, and connecting the upper and lower ends of the separated auxiliary gate lines to the data lines, respectively. And connection means for connecting the left auxiliary gate line of the upper pixel and the left auxiliary gate line of the lower pixel to repair the defect of the data line. As mentioned above, in this case, in order to connect the insulating layers of both ends of the data line and the auxiliary gate line, it is possible to have the branch of the data line extend toward the auxiliary gate line or both ends of the auxiliary gate line toward the data line. Chooses the latter. In addition, in order to connect the auxiliary gate line through the insulating layer, a pattern is formed of the same material as that of the data line or the pixel electrode.

This will be described in detail with reference to FIGS. 22 and 23 a and b.

FIG. 22 is a plan view illustrating a pixel structure of a matrix liquid crystal display substrate according to a fourth exemplary embodiment of the present invention, and FIGS. 23A and 23B illustrate data lines of a liquid crystal display substrate according to the fourth exemplary embodiment. In the case of disconnection, it is a view showing a repair method.

As shown in FIG. 23, in the matrix liquid crystal display substrate according to the fourth embodiment of the present invention, the portion corresponding to the left auxiliary gate line 1a in the conventional structure is the upper and lower gate lines G. As shown in FIG. _The upper and lower first connectors 41 and 42, which are separated from _up and G _down , and each of the upper and lower ends of the left auxiliary gate line 1a are bent to the left, respectively, the data line D of the left pixel. And a second connection portion 42 formed to overlap the second auxiliary portion 42 overlapping the left auxiliary gate line 1a of the upper pixel PX1 or PX3 and the left auxiliary gate line 1a of the lower pixel PX2 or PX4. The lower gate line G _down of the pixel PX1 or PX4 and the upper gate line G _up of the lower pixel PX2 or PX4 are formed to intersect. In addition, at the portion where the second connector 43 and the left auxiliary gate line 1a overlap, the pattern of the pixel electrode 10 enters inward, so that the second connector 43 and the left auxiliary gate line 1a are short-circuited. In this case, the pixel electrodes 10 are not shorted together. Here, the data line D and the first connectors 41 and 42 are interposed between the gate oxide film 3 and the gate insulating layer 4 of FIG. 4, and the second connector 43 is connected to the data line D. Alternatively, since a double layer is formed of the same material as the pixel electrode 10 or the two materials are patterned together, the gate oxide layer (a) may be interposed between the left auxiliary gate line 1a, the upper and lower gate lines G _up and G _down . 3) and the gate insulating layer 4 or the protective film 9 are sandwiched. The other parts are similar to the structures of FIGS. 3 and 4.

Then, when the data line is defective in the liquid crystal display substrate as in the present embodiment, the repair method will be divided according to the disconnected position.

First, as shown in FIG. 23A, the data line D between the intersection point b of the upper first connector 41 and the intersection point c of the lower first connector 42 is disconnected a and is below it. Consider the case where no data signal is delivered to the part. Arrows in the figure indicate the flow of signals.

When the intersection point (b) of the data line (D) located above the disconnection point (a) of the data line (D) and the upper first connection portion 41 is shorted with a laser, the left auxiliary of the right pixel PX3 is The data signal enters the gate 1a and flows downward. If the intersection c of the left auxiliary gate line 1a and the lower first connection portion 42 is shorted again, the data signal enters the data line D again.

As a result, the data signal flows back to the data line D via the upper first connector 41, the left auxiliary gate line 1a, and the lower first connector 42 of the right pixel PX3.

Next, as shown in FIG. 23A, the data line D between the intersection point b with the lower first connector 42 and the intersection point e with the upper first connector 41 below is disconnected (a). Consider the case where the data signal is not transmitted below. Arrows in the figure indicate the flow of signals.

When the intersection point b of the data line D and the lower first connection portion 42, which is located above the disconnection point a of the data line D, is short-circuited by using a laser, it is along the data line D. The flowing data signal flows to the lower first connection part 42 through the short point b without being directed to the disconnection point a.

The left auxiliary auxiliary gate line 1a of the right pixel PX3 and the second connecting unit 43 are short-circuited, and the intersection point between the second connecting unit 43 and the left auxiliary gate line 1a of the lower right pixel PX4 ( After shorting d), the left auxiliary gate line 1a and the upper second connection portion 41 of the pixel pixel PX4 are shorted again. Then, the data signal passes from the shorting point c to the second connection part 43, from the second connecting part 43 to the upper second connection part 41 of the pixel PX4 via the shorting point d, and then to the shorting point e. Return to the data line D after passing through).

As a result, the data signal flows back to the data line D via the lower second connector 43 of the right pixel PX3, the first connector 41, and the upper first connector 42 of the lower right pixel PX4. .

The fifth embodiment of the present invention is based on the basic structure of FIG. 12 or 14, and means for separating the upper portion of one auxiliary gate line from the upper gate line, and connecting the upper portion of the separated auxiliary gate line to the data line. In addition, a connection means for connecting the data line of the upper pixel and the data line of the lower pixel is provided to repair defects such as disconnection of the data line and loss of the gate electrode. As mentioned above, in order to connect both ends of the data line and the auxiliary gate line through the insulating layer, it is possible to have the branch of the data line extend toward the auxiliary gate line or both ends of the auxiliary gate line toward the data line. In the example, we choose the latter. In addition, a pattern is formed of the same material as that of the pixel electrode in order to connect the data line through the insulating layer.

This will be described in detail with reference to FIGS. 24 and 25a to 25c.

24 is a plan view illustrating a pixel structure of a substrate for a matrix type liquid crystal display according to a fifth exemplary embodiment of the present invention, and FIGS. 25A and 25B illustrate data lines of a substrate for a liquid crystal display according to the fifth exemplary embodiment. FIG. 25C shows a repair method in the case of disconnection, and FIG. 25C shows a repair method in the case where the gate electrode is lost.

As shown in FIG. 24, in the matrix liquid crystal display substrate according to the fifth embodiment of the present invention, the left auxiliary gate line 1a is separated from the upper gate line G _up , and the upper end thereof is The first connector 51, which is bent to the left, overlaps the data line D of the left pixel, and the lower end thereof is bent to the left and connected to the lower gate line G _down to overlap the data line D. . Further, at the intersection of the lower gate line G _down , the left auxiliary gate line 1a, and the data line D, the data line D between the data line D of the lower pixel column and the overlapping point of the first connection part 51. ) Is covered by the second connecting portion 52. The pixel electrode 10 overlaps the left auxiliary gate line 1a, but is slightly inward from both ends thereof, and thus does not overlap. Here, the data line D and the first connection part 51 sandwich the gate oxide film 3 and the gate insulating layer 4 of FIG. 4, and the second connection part 52 forms the pixel electrode 10. It is formed of a transparent conductive material and has the protective film 9 of FIG. 4 interposed with the data line D. FIG. The other parts are similar to the structures of FIGS. 3 and 4.

In the case where the data line becomes defective in the liquid crystal display device according to the present exemplary embodiment, the repair method will be divided according to the disconnected position.

First, as shown in FIG. 25A, the intersection point c of the lower gate line G _down and the left auxiliary gate line 1a of the coming pixel PX3 from the intersection point b with the first connector 51 is shown. Consider a case where the data line D between them is disconnected and a data signal cannot be transmitted to the lower portion thereof. Arrows in the figure indicate the flow of signals.

When the intersection point (b) of the data line (D) located above the disconnection point (a) and the first connection part (51) is short-circuited using a laser, the data signal enters the left auxiliary gate line (1a) of the pixel PX3. Flows downward. Again, the intersection point c of the left auxiliary gate line 1a and the connection portion of the lower gate line G _down and the data line D is short-circuited, and the lower gate line G _down to the left and right of the short circuit point c is _shortened . When disconnected, the data signal enters the data line D again.

As a result, the data signal flows back to the data line D via the first connector 51 and the left auxiliary gate line 1a of the right pixel PX3.

In this case, the gate signal applied to the right pixel PX3 is transmitted only through the upper gate line G _up .

Next, as shown in FIG. 25B, the data line between the intersection of the left auxiliary gate line 1a and the lower gate line G _down of the right pixel PX3 from the intersection of the first connection part 51 below it. Consider the case where (D) is disconnected (a) so that a data signal cannot be transmitted below it. Arrows in the figure indicate the flow of signals.

The data line D and the second connection portion 52 between the lower gate line G _down and the left auxiliary gate line 1a of the right pixel PX3 from the disconnection point a are short-circuited using a laser. (b) and the data line D below the disconnection point a and the second connection portion 52 are shorted (c), the data signal flowing along the data line D does not point to the disconnection point a. It flows to the 2nd connection part 52 through the short point b, and enters the data line D again from the short point c.

As a result, the data signal enters the data line D from the data line D via the second connection part 52 again.

As a final repair method of the present embodiment, a repair method in a case in which the gate electrode is lost or damaged and fails to serve as a repair chamber will be described. For example, consider the case where the gate electrode 2 of the lower right pixel PX4 is lost (a) as shown in FIG. 25C.

When the gate electrode 2 is lost, a data signal is not applied to the pixel electrode 10 of the upper pixel PX3 connected to the drain electrode 8, so that the data line is connected to the pixel electrode 10. (D) should be connected so that data signal is always applied. To do this, the intersection of the data line D and the lower gate line G _down and the intersection b of the data line D and the left auxiliary gate line 1a of the right pixel PX3 are short-circuited with a laser. When the lower gate line G _{down at the} short-circuit point b is cut off (d, e), and the left auxiliary gate line 1a and the pixel electrode 10 are short-circuited, the data signal is left-side auxiliary gate line ( It enters the pixel electrode 10 through 1a.

In this case, the gate signal applied to the right pixel PX3 is transmitted only through the upper gate line G _up .

The sixth embodiment of the present invention is based on the basic structure of FIG. 8, and the two auxiliary gate lines are separated from the upper gate line, and the two auxiliary gate lines are connected to form a closed region together with the lower gate line. It has a bridge connecting the auxiliary gate line and the upper gate line which are connected again, and a means for connecting the auxiliary gate line and the data line, and a means for connecting the auxiliary gate line and the upper gate line of the lower pixel and the lower gate line of the upper pixel. The defects such as disconnection of the line, short circuit of the auxiliary gate line or the lower gate line and the pixel electrode, and loss of the gate electrode are repaired. This will be described in detail with reference to FIGS. 26A to 27D.

FIG. 26 is a plan view illustrating a pixel structure of a matrix liquid crystal display substrate according to a sixth embodiment of the present invention, and FIGS. 26A to 26D illustrate defects occurring in the substrate for a liquid crystal display device according to the sixth embodiment. In the case of disconnection, it is a view showing a repair method.

As shown in FIG. 26, in the substrate for a matrix type liquid crystal display device according to the sixth embodiment of the present invention, the upper gate line G _up extends in a straight line along the horizontal direction and has a conventional upper gate line having curvature. It shows a different structure from (G _up ) and the structure of the thin film transistor is also different from the conventional one. In addition, the conventional left auxiliary gate line and the right auxiliary gate line are connected to form one auxiliary gate line 1, and are connected to the upper first gate line G _up by the bridge 63, and the left connection point 64 and The right connection point 65 is connected to the lower gate line G _down to form a closed area together. The first connection portion 61, which is a branch of the auxiliary gate line 1, extends toward the data line D to overlap the data line D, and overlaps the lower gate line G _down and the bridge 63, respectively. (It may overlap with the auxiliary gate line 1 instead of the bridge 63.) The second connection portion 62 is formed while crossing the upper gate line G _up below the lower gate line G _down . Here, the data line D and the first connection portion 61 sandwich the gate oxide film 3 and the gate insulating layer 4 of FIG. 4, and the second connection portion 62 includes the data line D or the pixel. The upper and lower gate lines G _up and G _down and the legs 63 are formed of a material constituting the electrode 10 so that the gate oxide film 3 and the gate insulating layer 4 of FIG. 9) in between. The other parts are similar to the structures of FIGS. 3 and 4.

Then, when the data line is defective in the matrix type liquid crystal display substrate as in the present embodiment, the repair method will be divided according to the disconnected position.

First, as shown in FIG. 27A, the data line D between the intersection point b with the first connection portion 61 and the intersection point c with the lower gate line G _down is disconnected a and is below it. Consider the case where no data signal is delivered to the part. Arrows in the figure indicate the flow of signals.

When the intersection (b) of the data line (D) located at the upper part of the disconnection point (a) and the first connection portion (61) is short-circuited (b) by using a laser, the data signal enters the auxiliary gate line (1). Or flow to the left. Again, the data line (D) the lower gate line (G _down) the paragraph (c) and legs (63), the left connecting portion 64, the lower gate line of the left (G _down) and short-circuit point (c) the lower portion of the right side When the gate line G _down is cut off (d, e, f), the data signal enters the data line D again through the auxiliary gate line 1.

As a result, the data signal flows back to the data line D via the first connector 61, the auxiliary gate line 1, and the lower gate line G _down .

In this case, the gate signal of the upper pixel PX1 is transferred to the right pixel only through the upper gate line G _up .

Next, as shown in FIG. 27B, the data line D between the intersection with the lower gate line G _down and the intersection with the first connection portion 51 below is disconnected a and data is stored thereunder. Consider the case where no signal is delivered. Arrows in the figure indicate the flow of signals.

When the data line D and the lower gate line G _down on the disconnection point a are shorted (b), the signal flowing through the data line D avoids the disconnection point a and the auxiliary gate line 1 is disconnected. Flows along. Short-circuit point (b) disconnects the right lower gate line (G _down ) and the leg (63) (g, h), short-circuit (c) the second connection portion 62 and the lower gate line (G _down ) and the short-circuit point ( c) If the lower gate line G _down on the left is cut (f), the data signal flows to the second connection portion 62. When the second connection part 62 and the leg 63 of the lower pixel PX2 are short-circuited d using a laser, the data signal travels along the auxiliary gate line 1. The lower and lower gate lines G _down of the left and right connectors 65 of the left connector 64 and the auxiliary gate line 1 of the lower pixel PX2 are cut (j, k), and the first connector ( When 61 and the data line D are short-circuited, the data signal returns to the data line D again.

As a result, the data signal flows back to the data line D through the lower gate line G _down of the upper pixel PX1, the second connection part 62, and the auxiliary gate line 1 of the lower pixel PX2.

In this case, the gate signal of the upper pixel PX1 is transmitted to the right pixel only through the upper gate line G _down , and the gate signal of the lower pixel PX2 is also transmitted to the right pixel only through the upper gate line G _down . .

In this embodiment, the pixel electrode 10 and the auxiliary gate line 1 are short-circuited and the gate electrode 2 of the transistor can be repaired or damaged.

As shown in FIG. 27C, when the auxiliary gate line 1 is short-circuited with the pixel electrode 10, a leg connecting the auxiliary gate line 1 and the upper gate line G _up ( 63 and the lower right gate line G _down of the left and right connection points 65 of the left connection point 64, and c and d to cut the auxiliary gate line 1 and the lower gate line G connected thereto. _down ) from the surroundings. In this way, the gate signal moves only through the upper gate line G _up .

Lastly, as shown in FIG. 27D, when the gate electrode 2 is damaged or lost (a), the data line D and the first connection portion 61 are short-circuited using a laser. b), the auxiliary gate line 1 and the pixel electrode 10 are short-circuited (c) so that the data signal flows directly into the pixel electrode 10, and then the lower gate to the left of the bridge 63 and the left connection point 64. The lower gate line G _down to the right of the line G _down and the short point c is cut (d, e, f) so that the data signal does not mix with the data signal.

As described above, in this embodiment, almost all signal lines are disconnected and short-circuits between the pixel electrodes and the signal lines and loss of the electrodes of the switching element are prevented without increasing the number of steps or reducing the aperture ratio. Can be repaired in units of pixels.

Claims (81)

A matrix type display device in which a plurality of pixel regions are formed in a matrix form, wherein the upper and lower first signal lines horizontally forming the upper and lower boundaries of each pixel region, and vertically between the pixel regions. And a second signal line formed to be insulated from and intersecting the upper and lower first signal lines, a pixel electrode formed in the pixel area, and made of a transparent conductive material, and a first terminal connected to the upper first signal line and the first signal line. An opening and closing element having a second terminal connected to a second signal line and a third terminal connected to the pixel electrode, and a second connecting one of the upper and lower first signal lines and the second signal line through a first insulator; 1 Display device comprising a connecting means. The matrix display device of claim 1, further comprising an auxiliary signal line forming a boundary of each pixel area. The matrix display device of claim 2, wherein the auxiliary signal line connects the upper and lower first signal lines to each other. The matrix type display device of claim 3, further comprising second connection means for connecting the auxiliary signal line and the pixel electrode via a second insulator. The matrix display device of claim 1, further comprising second connection means for connecting the first signal line and the pixel electrode connected to the first connection means with a second insulator. The matrix type display device of claim 1, further comprising second connection means for connecting the second signal line and the pixel electrode via a second insulator. A matrix type display device in which a plurality of pixel regions are formed in a matrix form, the upper first signal line forming a boundary of each pixel region and being formed horizontally, and forming a left and right boundary of each pixel region, respectively, and the upper first Left and right auxiliary signal lines connected to the signal lines, a second signal line formed vertically between the pixel areas and insulated from and intersecting the upper first signal line, and connecting the auxiliary signal lines on both sides of the second signal line to each other. A lower first signal line, a pixel electrode formed in the pixel area and made of a transparent conductive material, a first terminal connected to the upper first signal line, a second terminal connected to the second signal line, and connected to the pixel electrode An opening and closing element having a third terminal, and one of the upper and lower first signal lines via a first insulator A matrix type display device comprising a first connecting means for connecting the second signal line. The matrix display device of claim 7, further comprising second connection means for connecting the upper first signal line and the pixel electrode through a second insulator. 8. The matrix display device of claim 7, further comprising second connection means for connecting the second signal line and the pixel electrode via a second insulator. A matrix type display device in which a plurality of pixel regions are formed in a matrix form, wherein upper and lower first signal lines horizontally forming the upper and lower boundaries of each pixel region, and left and right sides of each pixel region. Left and right auxiliary signal lines each forming a boundary and connecting the upper and lower first signal lines to each other, a second signal line formed vertically between the pixel areas and insulated from and intersecting the upper and lower first signal lines; A pixel electrode formed in the pixel region and made of a transparent conductive material, a first terminal connected to the upper first signal line, a second terminal connected to the second signal line, and a third terminal connected to the pixel electrode; An opening and closing element, and a first connecting the one of the left and right auxiliary signal lines to the second signal line via a first insulator A matrix type display device comprising a connection means. The matrix display device of claim 10, further comprising second connection means for connecting the auxiliary signal line and the pixel electrode connected to the first connection means with a second insulator. The matrix display device of claim 10, further comprising second connection means connecting the first signal line and the pixel electrode via a second insulator. The matrix display device of claim 10, further comprising second connection means for connecting the second signal line and the pixel electrode via a second insulator. A matrix type display device in which a plurality of pixel regions are formed in a matrix form, wherein the upper and lower first signal lines horizontally forming the upper and lower boundaries of each pixel region, and vertically between the pixel regions. And a second signal line formed to be insulated from and intersecting the upper and lower first signal lines, a pixel electrode formed in the pixel area, and made of a transparent conductive material, and a first terminal connected to the upper first signal line and the first signal line. Matrix-type display device comprising a switching element having a second terminal connected to two signal lines and a third terminal connected to the pixel electrode, and connecting means for connecting the pixel electrode and the second signal line through an insulator. . The matrix display device of claim 14, further comprising an auxiliary signal line that forms a boundary of each pixel area. The matrix type display device of claim 15, wherein the auxiliary signal line connects the upper and lower first signal lines to each other. A matrix type display device in which a plurality of pixel regions are formed in a matrix form, the upper first signal line being formed horizontally along the boundary of each pixel region, and forming the left and right boundary systems of the pixel regions, respectively. Left and right auxiliary signal lines connected to a first signal line, a second signal line formed vertically between the pixel areas, insulated from and intersecting the upper first signal line, and the auxiliary signal lines on both sides of the second signal line; A lower first signal line connected to each other, a pixel electrode formed in the pixel area and made of a transparent conductive material, a first terminal connected to the upper first signal line, a second terminal connected to the second signal line, and the pixel An opening and closing element having a third terminal connected to an electrode, and connecting the pixel electrode and the second signal line through an insulator; A matrix type display device comprising a connecting means. A matrix type display device in which a plurality of pixel regions are formed in a matrix form, wherein upper and lower first signal lines horizontally forming the upper and lower boundaries of each pixel region, and left and right sides of each pixel region. A first auxiliary signal line formed in one of the boundaries and separated from one of the upper and lower first signal lines and connected to the other one, and formed vertically between the pixel areas and the upper and lower first A second signal line that is insulated from and crosses a signal line, a pixel electrode formed in the pixel area, a pixel electrode made of a transparent conductive material, a first terminal connected to the upper first signal line, and a second terminal connected to the second signal line; An opening and closing element having a third terminal connected to the pixel electrode, and connecting the first auxiliary signal line and the second signal line through an insulator; A matrix type display device comprising a connecting means. 19. The matrix display device of claim 18, further comprising a second auxiliary signal line forming a left and right boundary of each pixel area together with the first auxiliary signal line. The matrix type display device of claim 19, wherein the second auxiliary signal line connects the upper and lower first signal lines to each other. A matrix type display device in which a plurality of pixel regions are formed in a matrix form, comprising: an upper first signal line formed horizontally with a boundary of each pixel region, and forming one of left and right boundaries of each pixel region; A first auxiliary signal line separated from the upper first signal line, a second auxiliary signal line which is connected to the upper first signal line and forms a left and right boundary of each pixel area together with the first auxiliary signal line; A second signal line formed vertically between and insulated from and intersecting the upper and lower first signal lines; A lower first signal line connecting the auxiliary signal lines on both sides of the second signal line to each other, a pixel electrode formed in the pixel area and made of a transparent conductive material, a first terminal connected to the upper first signal line, and the second signal line And an opening and closing element having a second terminal connected to the pixel electrode and a third terminal connected to the pixel electrode, and a connecting means connecting the second auxiliary signal line and the second signal line through an insulator. . A matrix type display device in which a plurality of pixel regions are formed in a matrix form, the upper first signal line being formed horizontally along the upper boundary of each pixel region, and forming one of the left and right boundaries of each pixel region. A first auxiliary signal line separated from the upper first signal line, a second signal line formed vertically between each pixel area, and insulated from and intersecting the upper first signal line, and formed in the pixel area, and a transparent conductive material An opening and closing element having a pixel electrode consisting of: a first terminal connected to the upper first signal line, a second terminal connected to the second signal line, and a third terminal connected to the pixel electrode; First connection means for connecting one end of the first auxiliary signal line and the second signal line, and the first auxiliary signal line through the insulator. Other end to a matrix type display unit including a second connection means for connecting the second signal line. 23. The matrix display device of claim 22, further comprising a second auxiliary signal line which forms another one of a left boundary and a right boundary of each pixel area. The matrix type display device of claim 23, wherein the second auxiliary signal line is connected to the upper first signal line. 25. The matrix display device of claim 24, further comprising a lower first signal line that forms a lower boundary of each pixel area and is formed horizontally. The matrix type display device of claim 25, wherein the second auxiliary signal line is connected to the lower first signal line. 23. The matrix display device of claim 22, further comprising third connecting means for connecting the first auxiliary signal line with an insulator through upper and lower ends. An upper gate line formed along a horizontal line, a lower gate line formed along a horizontal line at intervals with the upper gate line, an auxiliary gate line connecting the upper gate line and a lower gate line to form a pair, or a part of the upper gate line or A gate electrode which is a branch, a first insulating layer formed on the front surface to cover the upper and lower gate lines and the auxiliary gate line, and the gate electrode, a semiconductor layer formed on the first insulating layer to cover the gate electrode, A data line formed vertically between the pair of neighboring auxiliary gate lines on the first insulating layer, a source electrode connected to the semiconductor layer as a part or branch of the data line, and connected to the semiconductor layer; Before the data electrode, the data line, the source electrode, and the drain separated from the electrode A second insulating layer formed on a front surface of the electrode to cover the first connection part, and a transparent pixel electrode formed in a closed area including the upper and lower gate lines and the auxiliary gate line on the second insulating layer; And the drain electrode is connected to a pixel electrode above the gate electrode, and a portion of the upper gate line and the data line overlap each other. 29. The thin film transistor substrate of claim 28, wherein the overlapping of the upper gate line and the data line is formed by a first connection part which is a branch of the data line. 30. The thin film transistor substrate of claim 29, wherein the point where the upper gate line and the data line overlap is positioned on the upper gate line not forming a closed region. 31. The thin film transistor substrate of claim 30, wherein a branch point of the first connection portion is positioned at a data line between an intersection point of the upper gate line and an intersection point of the lower gate line. 32. The thin film transistor substrate of claim 31, wherein the gate electrode is positioned between an intersection of the first gate and an upper gate line between an intersection of the upper gate line and the data line. 33. The thin film transistor substrate of claim 32, wherein the upper gate line has a parallel portion parallel to the data line, and one of the auxiliary gate lines is connected to a lower portion of the parallel portion. 34. The register substrate of claim 33, wherein the gate electrode is positioned in the parallel portion. 32. The display device of claim 31, further comprising: a protrusion protruding out of an area formed by the upper and lower gate lines and an auxiliary gate line as a branch of the pixel electrode, and a second connection portion which is a branch of the upper gate line and overlaps the protrusion of the pixel electrode. Thin film transistor substrate for matrix liquid crystal display. The thin film transistor substrate of claim 35, wherein a point at which the second connection portion branches from the upper gate line is between the gate electrode from a connection point of an upper gate line and an auxiliary gate line. 32. The method of claim 31, further comprising a second connection portion protruding out of an area formed by the upper and lower gate lines and the auxiliary gate line as a branch of the pixel electrode, wherein the second connection portion overlaps the upper gate line which does not form a closed region. Thin film transistor substrate for liquid crystal display device. 32. The thin film transistor substrate of claim 31, wherein the pixel electrode overlaps the upper and lower gate lines and the auxiliary gate line. 29. The thin film transistor substrate of claim 28, wherein the overlapping of the upper gate line and the data line is made by a third connection part which is a branch of the upper gate line. An upper gate line formed along a horizontal line, a lower gate line formed along a horizontal line at intervals with the upper gate line, an auxiliary gate line connecting the upper gate line and a lower gate line to form a pair, or a part of the upper gate line or A gate electrode which is a branch, a first insulating layer formed on the front surface to cover the upper and lower gate lines and the auxiliary gate line, and the gate electrode, a semiconductor layer formed on the first insulating layer to cover the gate electrode, A data line formed vertically between the pair of neighboring auxiliary gate lines on the first insulating layer, a source electrode connected to the semiconductor layer as a part or branch of the data line, and connected to the semiconductor layer; Before the data electrode, the data line, the source electrode, and the drain separated from the electrode A second insulating layer formed on an entire surface of the second insulating layer so as to cover a pole; and a transparent pixel electrode formed in a closed region formed of the upper and lower gate lines and the auxiliary gate line on the second insulating layer. A thin film transistor substrate for a matrix type liquid crystal display device connected to the pixel electrode above a gate electrode, wherein one of the auxiliary gate lines and a part of the data lines overlap each other. 41. The thin film transistor substrate of claim 40, wherein the auxiliary gate line overlaps the data line by a first connection part which is a branch of the data line. 42. The thin film transistor substrate of claim 41, wherein the first connection portion also overlaps the pixel electrode. 43. The thin film transistor substrate of claim 42, wherein the pixel electrode overlaps the upper and lower gate lines and the auxiliary gate line. 42. The thin film transistor substrate of claim 41, wherein the gate electrode is positioned on the upper gate line that does not form a closed region. 45. The matrix liquid crystal display device of claim 44, wherein the gate electrode is positioned on a fraudulent upper gate line between an intersection point of the upper gate line and the data line from a connection point of the auxiliary gate line and the upper gate line overlapping the first connector. Thin film transistor substrate. 46. The thin film transistor substrate of claim 45, wherein the gate line has a parallel portion parallel to the data line and the auxiliary gate line overlapping the first connection portion is connected to a lower portion of the parallel portion. 47. The thin film transistor substrate of claim 46, wherein the gate electrode is positioned in parallel. 42. The thin film transistor substrate of claim 41, wherein the drain electrode overlaps a lower gate line positioned directly under the pixel electrode connected to the drain electrode. 41. The thin film transistor substrate of claim 40, wherein the overlapping of the auxiliary gate line and the data line is formed by a first connection part which is a branch of the auxiliary gate line. An upper gate line formed along a horizontal line, a lower gate line formed along a horizontal line at intervals with the upper gate line, a first auxiliary gate line connecting the upper gate line and the lower gate line, one end of the upper and lower lines A second auxiliary gate line connected to one of the gate lines and open at the other end thereof, the second auxiliary gate line paired with the first auxiliary gate line to form a part of an open area defined by the upper gate line and the lower gate line; A gate electrode which is a part or a branch of a gate line, a first insulating layer formed on the front surface to cover the upper and lower gate lines and the auxiliary gate line, and the gate electrode, and is formed on the first insulating layer to cover the gate electrode A semiconductor layer on the first insulating layer, and formed along a length between the pair of neighboring auxiliary gate lines A data line, a source electrode connected to the semiconductor layer as a part or branch of the data line, a data electrode connected to the semiconductor layer and separated from the source electrode, and covering the data line, the source electrode and the drain electrode. And a transparent pixel electrode formed in the open area on the second insulating layer on the second insulating layer, wherein the drain electrode is connected to the pixel electrode on the gate electrode. 1 A thin film transistor substrate for a matrix type liquid crystal display device in which part of the auxiliary gate line and the data line overlap each other. 51. The thin film transistor substrate of claim 50, wherein the overlap of the first auxiliary gate line and the data line is formed by a first connection part which is a branch of the first auxiliary gate line. 52. The thin film transistor substrate of claim 51, wherein the gate electrode is positioned across the first auxiliary gate line with respect to the data line and at an upper gate line not forming a closed region. 53. The thin film transistor substrate of claim 52, wherein an overlapping point of the first connection part and the data line is positioned at the data line between a branch point of the source electrode at an intersection point of the upper gate line. 54. The thin film transistor substrate of claim 53, wherein the pixel electrode overlaps the upper and lower gate lines and the auxiliary gate line. 55. The thin film transistor substrate of claim 54, wherein the pixel electrode does not overlap the auxiliary gate line between an intersection point with the upper gate line at a branch point of the first connection portion. 54. The thin film transistor substrate of claim 53, wherein the drain electrode overlaps a lower gate line positioned directly below the pixel electrode connected to the drain electrode. The thin film transistor substrate of claim 51, wherein an open end of the second auxiliary gate line is positioned at a connection point between the pixel electrode and the drain electrode. An upper gate line formed along a horizontal line, a lower gate line formed along a horizontal line at intervals with the upper gate line, a first auxiliary gate line connecting the upper gate line and the lower gate line, one end of the upper and lower lines A second auxiliary gate line connected to one of the gate lines and open at the other end thereof, the second auxiliary gate line paired with the first auxiliary gate line to form a part of an open area defined by the upper gate line and the lower gate line; A gate electrode which is a part or a branch of a gate line, a first insulating layer formed on the front surface to cover the upper and lower gate lines and the auxiliary gate line, and the gate electrode, and is formed on the first insulating layer to cover the gate electrode A semiconductor layer on the first insulating layer, and formed along a length between the pair of neighboring auxiliary gate lines A data line, a source electrode connected to the semiconductor layer as a part or branch of the data line, a data electrode connected to the semiconductor layer and separated from the source electrode, covering the data line, the source electrode and the drain electrode. And a transparent pixel electrode formed in the open area on the second insulating layer on the second insulating layer, the drain electrode being connected to the pixel electrode on the gate electrode. A thin film transistor substrate for a matrix type liquid crystal display device, wherein an open end of the second auxiliary gate line overlaps the data line. 60. The thin film transistor substrate of claim 58, wherein the overlapping of the second auxiliary gate line and the data line is made by a first connection part which is a branch of an open end of the second auxiliary gate line. 60. The thin film transistor substrate of claim 59, wherein the pixel electrode overlaps the second auxiliary gate line. 61. The thin film transistor substrate of claim 60, wherein the pixel electrode does not overlap both ends of the second auxiliary gate line. 61. The thin film transistor substrate of claim 60, wherein the pixel electrode overlaps upper and lower gate lines and the first auxiliary gate line. 61. The display device of claim 60, wherein the second connection portion is formed on the second insulating layer and is formed to cover the data line between an overlapping point with the first connection portion at an intersection point with the gate line connected to a second auxiliary gate line. A thin film transistor substrate for a matrix type liquid crystal display device further comprising. 66. The thin film transistor substrate of claim 63, wherein a connection point of the second auxiliary gate line and the gate line is the same position as an intersection point of the gate line and the data line connected to the second auxiliary gate line. An upper gate line formed along a horizontal line, a lower gate line formed along a horizontal line at intervals with the upper gate line, a first auxiliary gate line connecting the upper gate line and the lower gate line, and both ends are open; A second auxiliary gate line paired with the first auxiliary gate line to form a part of an open area defined by the upper gate line and the lower gate line, a gate electrode which is a part or a branch of the upper gate line, the upper and lower gate lines, and the auxiliary A pair of gate lines, a first insulating layer formed on an entire surface of the gate electrode to cover the gate electrode, a semiconductor layer formed on the first insulating layer to cover the gate electrode, and a pair of neighboring auxiliary gate lines on the first insulating layer A data line formed vertically between the semiconductor layer as a part or branch of the data line A second insulating layer formed on a front surface of the source electrode connected to the semiconductor layer, the data electrode connected to the semiconductor layer and separated from the source electrode, the data line, the source electrode, and the drain electrode; A transparent pixel electrode formed in the open area on the layer, wherein the drain electrode is connected to the pixel electrode above the gate electrode, and both open ends of the second auxiliary gate line overlap each other. Thin film transistor substrate for matrix liquid crystal display. 66. The thin film transistor substrate of claim 65, wherein the overlapping of the second auxiliary gate line and the data line is formed by a first connection part and a second connection part which are branches of open ends of the second auxiliary gate line. 67. The thin film transistor substrate of claim 66, further comprising a third connection portion formed on the first insulating layer and overlapping both ends of the second auxiliary gate line adjacent to each other. 68. The thin film transistor substrate of claim 67, wherein the third connection portion comprises a double layer of a metal layer and an ITO layer. 66. The thin film transistor substrate of claim 65, further comprising a third connection portion formed on the second insulating layer and overlapping the ends of the second auxiliary gate line adjacent to each other. 70. The thin film transistor substrate of claim 65, wherein the pixel electrode overlaps the second auxiliary gate line at portions except at both ends of the second auxiliary gate line. 71. The thin film transistor substrate of claim 70, wherein the pixel electrode also overlaps the upper and lower gate lines and the first auxiliary gate line. 66. The thin film transistor substrate of claim 65, wherein the open ends of the second auxiliary gate line and the data line overlap each other by a first connection part and a second connection part which are two branches of the data line. 67. The method of claim 65, wherein the overlapping ends of the open second ends of the second auxiliary gate lines and the data lines are overlapped with the open ends of the second auxiliary gate lines and the first connection part, which is a branch of the data lines, of the second auxiliary gate line. A thin film transistor substrate for a matrix type liquid crystal display device, wherein a second connection portion, which is a branch of another open end, overlaps the data line. An upper gate line formed along a horizontal line, a lower gate line formed along a horizontal line at intervals with the upper gate line, an auxiliary gate line connected at two places with the lower gate line and forming a closed region together with the lower gate line, A bridge formed between the upper gate line and the upper gate line, a gate electrode which is a part or a branch of the upper gate line, the upper and lower gate lines and the auxiliary gate line, the legs, and the gate electrode to cover the gate electrode; 1 an insulating layer, a semiconductor layer formed on the first insulating layer so as to cover the gate electrode, a data line formed vertically between the pair of neighboring auxiliary gate lines on the first insulating layer, and a part of the data line Or a source electrode connected to the semiconductor layer as a branch, the semiconductor layer and A second insulating layer connected to the data electrode, the data line, the source electrode and the drain electrode and connected to and separated from the source electrode; the lower gate line and the auxiliary gate line on the second insulating layer. And a transparent pixel electrode formed in a closed area of the pixel electrode, wherein the drain electrode is connected to the pixel electrode above the gate electrode, and the auxiliary gate line and the data line partially overlap each other. Thin film transistor substrate. 75. The thin film transistor substrate of claim 74, wherein the overlapping of the auxiliary gate line and the data line is formed by a first connection part which is a branch of the auxiliary gate line. 76. The thin film transistor of claim 75, further comprising a second connection portion formed on the first insulating layer and overlapping the lower gate line and the bridge under the lower gate line. Board. 76. The thin film transistor of claim 75, further comprising a second connection portion formed on the second insulating layer and overlapping the lower gate line and the legs disposed below the lower gate line. Board. 76. The matrix liquid crystal display device of claim 75, further comprising a second connection part formed on the first insulating layer and overlapping the auxiliary gate line positioned below the lower gate line and the lower gate line. Transistor substrate. 76. The matrix liquid crystal display device of claim 75, further comprising a second connection part formed on the first insulating layer and overlapping the auxiliary gate line positioned below the lower gate line and the lower gate line. Transistor substrate. 79. The thin film transistor substrate of claim 74, wherein the pixel electrode is formed to overlap the auxiliary gate line and the lower gate line. 75. The thin film transistor substrate of claim 74, wherein the overlapping of the auxiliary gate line and the data line is formed by a first connection part which is a branch of the data line.