KR0156123B1 - Semiconductor manufacturing method - Google Patents
Semiconductor manufacturing method Download PDFInfo
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- KR0156123B1 KR0156123B1 KR1019940033460A KR19940033460A KR0156123B1 KR 0156123 B1 KR0156123 B1 KR 0156123B1 KR 1019940033460 A KR1019940033460 A KR 1019940033460A KR 19940033460 A KR19940033460 A KR 19940033460A KR 0156123 B1 KR0156123 B1 KR 0156123B1
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Abstract
본 발명은 디클로로 싸일레(SiH2Cl2)를 이용한 텅스텐 실리사이드(WSix) 증착에 관한 것으로 특히 메가 비트 메모리(Mega Bit Memory)소자에 적당하도록 한 WSix 증착방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to tungsten silicide (WSix) deposition using dichlorocyle (SiH 2 Cl 2 ) and, more particularly, to a WSix deposition method suitable for mega bit memory devices.
이와 같은 본 발명의 반도체 제조방법은 선택적으로 고농도(N+) 불순물이 확산된 기판상에 절연막을 증착하고, 상기 절연막상에 감광막을 도포하여 노광 및 식각공정으로 콘택홀영역을 선택적으로 패터닝한뒤 감광막을 제거하는 공정과, 상기 전면에 제1WSix층을 증착하는 공정과, 상기 제1WSix층상에 제2WSix층을 증착하는 공정을 포함한다.The semiconductor manufacturing method of the present invention selectively deposits an insulating film on a substrate on which a high concentration (N + ) impurity is diffused, and a photoresist film is coated on the insulating film to selectively pattern the contact hole region by an exposure and etching process. Removing a photoresist film; depositing a first WSix layer on the entire surface; and depositing a second WSix layer on the first WSix layer.
Description
제1도는 종래의 반도체 제조 공정단면도.1 is a cross-sectional view of a conventional semiconductor manufacturing process.
제2도는 본 발명의 반도체 제조 공정단면도.2 is a cross-sectional view of a semiconductor manufacturing process of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 기판 22 : 불순물확산영역21 substrate 22 impurity diffusion region
23 : 절연막 24 : 감광막23 insulating film 24 photosensitive film
25 : 제1텅스텐 실리사이드막 26 : 제2텅스텐 실리사이드막25: first tungsten silicide film 26: second tungsten silicide film
본 발명은 디클로로 싸일렌(Dichlorosilane : 이하 SiH2Cl2라 약칭함)을 이용한 텅스텐 실리사이드(Tungsten silicide : 이하 WSix라 약칭함) 증착에 관한 것으로, 특히 메가 비트 메모리(Mega Bit Memory)소자에 적당하도록 한 WSix 증착방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the deposition of tungsten silicide using dichlorosilane (abbreviated as SiH 2 Cl 2 hereinafter), particularly suitable for mega bit memory devices. A WSix deposition method is provided.
일반적으로 WSix Film을 증착하는 방법은 첨부된 도면을 참조하여 설명하면 다음과 같다.Generally, a method of depositing a WSix film is described below with reference to the accompanying drawings.
제1도는 종래의 반도체 제조 공정단면도이다.1 is a cross-sectional view of a conventional semiconductor manufacturing process.
제1도 (a)에서와 같이 선택적으로 고농도(N+) 불순물(2)이 확산된 기판(1)상에 절연막(3)을 증착한후 상기 절연막상에 감광막을 도포하여 제1도(b)에서와 같이 노광 및 식각공정으로 콘택홀영역을 선택적으로 패터닝한 뒤 상기 감광막을 제거한다. 이어서 제1도(c)에서와 같이 상기 전면에 WSix층을 증착한다.As shown in FIG. 1 (a), an insulating film 3 is deposited on the substrate 1 onto which the high concentration (N + ) impurity 2 is selectively diffused, and then a photosensitive film is coated on the insulating film. The photoresist layer is removed after the contact hole region is selectively patterned by an exposure and etching process. Subsequently, a WSix layer is deposited on the front surface as shown in FIG.
상기와 같이 종래에는 WSix Film을 증착하는데 두가지 방법이 있다.As described above, there are two methods for depositing a WSix film.
첫째, 실리콘 소오스(silicon source)로 Mono-Silane(SiH4)을 사용하는 방법이다. SiH4Gas를 사용하므로 증착온도는 300∼400℃의 낮은 온도에서 사용한다.First, Mono-Silane (SiH 4 ) is used as a silicon source. As SiH 4 Gas is used, the deposition temperature is used at low temperature of 300 ~ 400 ℃.
그러므로 피복율(step coverage)이 나쁘고, 공정의 변화에 따라 막질이 민감하게 변한다.Therefore, the step coverage is bad, and the film quality is sensitive to the change of the process.
즉, WSix의 x값이 2.9이상이 되면 비저항(Resistivity)이 커지게 되어 반도체 소자의 동작속도가 높아지게 되며, x값이 2.6 이하가 되면 비저항은 낮아지지만 WSix Film이 크랙(crack)이나 필링(peeling)현상이 일어나는 단점이 있다.In other words, if the x value of WSix is more than 2.9, the resistivity is increased and the operation speed of the semiconductor device is increased. If the x value is 2.6 or less, the resistivity is low, but the WSix film cracks or peels There is a disadvantage that occurs.
둘째, 실리콘 소오스(silicon source)로 SiH2Cl2을 사용하는 고온공정(600℃ 이상)이다.Second is a high temperature process (more than 600 ℃) using SiH 2 Cl 2 as a silicon source (silicon source).
그러나 두 번째 공정은 고온 공정이므로, 피복율은 상당히 좋아지고 막(Film)내에 실리콘(silicon)의 함유량이 많아 크랙(crack)이나 필링(peeling)을 현저히 감소하지만 막(Film)내에 실리콘(silicon)의 함유량이 많으므로 비저항은 상당히 높아지는 단점이 있다.However, since the second process is a high temperature process, the coverage is considerably improved and the silicon content in the film significantly reduces cracks and peeling, but the silicon in the film is significantly reduced. There is a disadvantage in that the specific resistance becomes considerably high since the content of is large.
상기와 같이 종래의 기술은 WSix Film을 증착함에 있어서는 다음과 같은 문제점이 있었다.As described above, the conventional technology has the following problems in depositing a WSix film.
첫째, SiH4Gas와 낮은 온도(350℃ 근방)를 사용함으로서 낮은 피복율(step coverage)을 갖게되므로 반도체 소자가 고집적화함에 따른 고단차를 극복하지 못하여 WSix Film의 단선을 유발시키는 불량을 발생한다.First, since SiH 4 gas and low temperature (near 350 ° C.) are used, it has a low step coverage, and thus a defect that causes disconnection of the WSix film does not occur due to high integration due to high integration of semiconductor devices.
둘째, 높은 피복율을 갖기 위해서 SiH4Gas대신 SiH2Cl2Gas를 사용하여 고온(600℃ 이상)에서 증착시키기도 하였으나, 이 막(Film)은 높은 피복률을 가지는 반면 고온 공정이므로 이로 인해 높은 비저항을 갖게되어 소자의 동작속도를 느리게 한다.Second, in order to have a high coverage, SiH 2 Cl 2 Gas was used instead of SiH 4 Gas for deposition at high temperature (above 600 ℃). However, this film has high coverage and high resistivity because of high temperature process. It will reduce the operating speed of the device.
본 발명은 이와 같은 종래 기술의 두가지 방법의 문제점을 해결하기 위해 안출한 것으로, silicon source로 SiH2Cl2를 사용하고, 온도는 SiH2Cl2Gas의 분해온도(500℃ 근방)보다는 조금 높은 500℃∼600℃ 영역에서 증착한다.The present invention has been made to solve the problems of the two methods of the prior art, using a SiH 2 Cl 2 as a silicon source, the temperature is slightly higher than the decomposition temperature of SiH 2 Cl 2 Gas (near 500 ℃) 500 Deposition is carried out in the range of ℃ to 600 ℃.
또한 비저항을 낮추기 위하여 WF6Gas의 Flow Rate를 종래 기술보다 증가시키고, 이로 인해 발생되는 크랙(crack)이나 필링(peeling)을 방지하기 위하여 WSix Film 증착초기에 핵생성 스텝(Nucleation step)을 추가시킨다.In addition, the flow rate of the WF 6 gas is increased in order to lower the resistivity, and a nucleation step is added at the beginning of WSix film deposition to prevent cracking or peeling caused by the conventional technique. .
즉, 증착초기에 silicon이 풍부한(Si-rich) WSix Film인 핵성성층(Nucleation layer)을 200∼500Å 정도로 형성시킴으로서 silicon과 WSix Film의 adhesion을 증가시켜 크랙(crack) 및 필링(peeling)을 방지하는데 그 목적이 있다.In other words, by forming a nucleation layer, which is a silicon-rich WSix film at about 200 to 500Å, it increases adhesion between silicon and WSix film to prevent cracking and peeling. Its purpose is to.
상기 같은 목적을 달성하기 위한 본 발명은 첨부된 도면을 참조하여 설명하면 하기와 같다.The present invention for achieving the above object is described below with reference to the accompanying drawings.
제2도는 본 발명의 반도체 제조 공정단면도이다.2 is a cross-sectional view of a semiconductor manufacturing process of the present invention.
제2도 (a)와 같이 선택적으로 고농도(N+) 불순물(22)이 확산된 기판(21)상에 절연막(23)을 증착한후 상기 절연막(23)상에 감광막(24)을 도포하여 제2도 (b)에서와 같이 노광 및 식각 공정으로 콘택홀 영역을 선택적으로 패터닝한 뒤 상기 감광막을 제거한다.As shown in FIG. 2A, an insulating film 23 is deposited on the substrate 21 on which the high concentration (N + ) impurity 22 is selectively deposited, and then a photosensitive film 24 is coated on the insulating film 23. As illustrated in FIG. 2B, the photoresist layer is removed after the contact hole region is selectively patterned by an exposure and etching process.
이어서 제2도 (c)와 같이 비저항을 낮추기 위하여 WF6Gas의 Flow Rate를 종래의 기술보다 증가시킴으로써, 야기되는 크랙(crack)이나 필링(peeling)을 방지하기 위하여 제1WSix(핵생성스텝)(Nucleation step)(25)을 추가로 형성한다.Subsequently, as shown in FIG. 2C, the flow rate of the WF 6 gas is increased in order to lower the specific resistance, so as to prevent cracking or peeling caused by the first WSix (nucleation step) ( Nucleation step 25 is further formed.
즉, 증착초기에 제1WSix층으로 silicon이 풍부한(Si-rich) WSix Film인 핵생성층을 200∼500Å 형성시킴으로써 silicon과 WSix Film의 adhesion을 증가시켜 필링(peeling) 및 크랙(crack)을 방지한다.That is, by forming a nucleation layer, which is a silicon-rich WSix film, as a first WSix layer at 200 to 500 Å in the initial deposition process, adhesion between silicon and WSix film is increased to prevent peeling and cracking. .
여기서, 핵생성층으로 사용하는 Si-Rich WSix Film의 x는 4이상이고, SiH2Cl2/WF6Gas의 Ratio는 45이상인 영역이고, 증착온도는 500∼700℃사이의 영역에서 제1WSix Film을 증착한다.Here, x of Si-Rich WSix Film used as the nucleation layer is at least 4, the ratio of SiH 2 Cl 2 / WF 6 Gas is at least 45, the deposition temperature is in the region of 500 ~ 700 ℃ 1WSix Film Deposit.
제2도(d)와 같이 상기 제1WSix Flim상에 제2WSix Film(26)을 증착한다.As shown in FIG. 2D, a second WSix Film 26 is deposited on the first WSix Flim.
이때 제2WSix Film은 SiH2Cl2Gas와 WF6Gas의 사용비 즉 SiH2CL2/WF6Gas의 Ratio가 25이상인 영역이고, 증착온도는 500℃∼600℃사이 영역에서 증착한다.In this case, the second WSix film is a region in which the ratio of SiH 2 Cl 2 Gas and WF 6 Gas is used, that is, the ratio of SiH 2 CL 2 / WF 6 Gas is 25 or more, and the deposition temperature is deposited in the region of 500 ° C. to 600 ° C.
상기에서 설명한 바와 같이 본 발명의 반도체 제조방법에 있어서는 다음과 같은 효과가 있다.As described above, the semiconductor manufacturing method of the present invention has the following effects.
첫째, SiH4Gas와 낮은 온도(300℃∼400℃)의 공정으로 인한 낮은 피복률과 WSix Film의 크랙(crack)이나 필링(peeling) 현상을 방지하기 위하여 핵생성층(Si-rich WSix Film, x4)를 200∼500Å정도 형성시킴으로써 silicon과 WSix Film의 adhesion을 증가시켜 크랙(crack) 및 필링(peeling)을 방지하여 단선 불량을 줄일 수 있다.First, SiH 4 Gas and low temperature (~400 ℃ ℃ 300) processes a low coverage rate and WSix Film crack (crack) or peeling (peeling) nucleation layer (Si-rich WSix to prevent the phenomenon due to the Film, By forming x4) at about 200 to 500Å, the adhesion between silicon and WSix film can be increased to prevent cracking and peeling, thereby reducing disconnection defects.
둘째, SiH2Cl2Gas와 높은 온도(600℃ 이상)의 공정으로 인한 높은 비저항(Resistivity, 12000μΩ㎝ 이상)을 낮추기 위하여 WF4Gas의 Flow rate를 종래 기술보다 증가시켜 비저항을 낮게 할 수 있어 반도체 소자의 동작속도를 빠르게 할 수 있다.Second, in order to lower the high resistivity (Resistivity, 12000μΩ㎝ or more) due to the process of SiH 2 Cl 2 Gas and high temperature (over 600 ℃), the specific resistance can be lowered by increasing the flow rate of WF 4 Gas than the prior art. The operation speed of the device can be increased.
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019940033460A KR0156123B1 (en) | 1994-12-09 | 1994-12-09 | Semiconductor manufacturing method |
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| KR1019940033460A KR0156123B1 (en) | 1994-12-09 | 1994-12-09 | Semiconductor manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101020124B1 (en) * | 2009-03-03 | 2011-03-07 | 난 희 황 | Replaceable LED Light |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101020124B1 (en) * | 2009-03-03 | 2011-03-07 | 난 희 황 | Replaceable LED Light |
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