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KR970018661A - Tungsten Polyside Gate Electrode Formation Method With Barrier Layer - Google Patents

Tungsten Polyside Gate Electrode Formation Method With Barrier Layer Download PDF

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Publication number
KR970018661A
KR970018661A KR1019950031107A KR19950031107A KR970018661A KR 970018661 A KR970018661 A KR 970018661A KR 1019950031107 A KR1019950031107 A KR 1019950031107A KR 19950031107 A KR19950031107 A KR 19950031107A KR 970018661 A KR970018661 A KR 970018661A
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KR
South Korea
Prior art keywords
barrier layer
tungsten
depositing
barrier
deposition
Prior art date
Application number
KR1019950031107A
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Korean (ko)
Inventor
배대록
박병률
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950031107A priority Critical patent/KR970018661A/en
Publication of KR970018661A publication Critical patent/KR970018661A/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/664—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a barrier layer between the layer of silicon and an upper metal or metal silicide layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 장벽층(Barrier Layer)을 이용한 텅스텐 실리사이드 증착방법에 관한 것으로서, 다결정 실리콘상에 장벽 금속(barrier metal)을 증착하는 단계; 및 SiH2Cl2를 이용하여 텅스텐 실리사이드를 증착하는 단계를 포함함을 특징으로 한다.The present invention relates to a tungsten silicide deposition method using a barrier layer, comprising: depositing a barrier metal on polycrystalline silicon; And depositing tungsten silicide using SiH 2 Cl 2 .

본 발명에 의한 텅스텐 장벽층을 갖는 텅스텐 폴리사이드 게이트전극 형성방법은 텅스텐 실리사이드 하부에 장벽층(barrier layer)증착시 WF6와 NH3를 이용하여 증착을 하기 때문에 WF6와 다결정실리콘과의 반응에 의한 실리콘 소모를 크게 억제시킬 수 있다. 이는 장벽층을 플라즈마(plasma)상태로 증착을 하고 저온 공정이 가능하기 때문에 장벽층(barrier layer) 증착과정에서 웜홀(wormhole)의 생성 없이 텅스텐질화막을 증착할 수 있기 때문이다. 따라서 후속 공정인 고온 공정인 SiH2Cl2-기반 텅스텐 실리사이드 증착시 텅스텐 질화막의 장벽(barrier) 특성 때문에 초기 증착에서의 웜홀(wormhole)의 발생을 억제하는 장점을 가지고 있다.Tungsten polycide gate electrode forming method having a tungsten barrier layer according to the invention because the deposition by using the barrier layer (barrier layer) deposited upon WF 6 and NH 3 in the tungsten suicide lower the reaction with WF 6 and polysilicon It is possible to greatly suppress the silicon consumption caused by. This is because the barrier layer is deposited in a plasma state and a low temperature process is possible, so that a tungsten nitride film can be deposited without generating a wormhole during the barrier layer deposition process. Therefore, the SiH 2 Cl 2 -based tungsten silicide deposition, which is a subsequent high temperature process, has the advantage of suppressing the occurrence of wormholes in the initial deposition due to the barrier property of the tungsten nitride film.

Description

장벽층을 갖는 텅스텐 폴리사이드 게이트 전극 형성 방법Tungsten Polyside Gate Electrode Formation Method With Barrier Layer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3A도 내지 제3C도는 본 발명의 텅스텐 폴리사이드 게이트 전극 형성방법을 설명하기 위해 도시한 단면도들이다.3A to 3C are cross-sectional views illustrating a method of forming a tungsten polyside gate electrode of the present invention.

Claims (5)

반도체 기판상의 장벽층을 갖는 게이트 전극을 형성하는 방법에 있어서, 실리콘 기판상에 게이트 산화막을 증착한 후 전도성을 갖는 도핑된 다결정실리콘층을 형성하는 단계; 상기 다결정실리콘층 상에 금속장벽을 증착하는 단계; 텅스텐 실리사이드를 화학기상증착법으로 증착하고, 감광제를 도포하는 단계; 상기 감광막을 사진 공정으로 패터닝하여 감광막 패턴을 형성하는 단계; 상기 감광막 패턴을 마스크로 사용하여 상기 텅스텐 실리사이드층과 금속장벽층 및 상기 다결정실리콘층을 연속적으로 식각하여 텅스텐 실리사이드 패턴, 금속방벽 패턴 및 다결정실리콘 패턴을 형성하는 단계; 및 상기 감광막 패턴을 제거하는 단계를 포함함을 특징으로 하는 장벽층을 갖는 텅스텐 폴리사이드 게이트전극 형성방법9. A method of forming a gate electrode having a barrier layer on a semiconductor substrate, comprising: forming a conductive doped polysilicon layer after depositing a gate oxide film on a silicon substrate; Depositing a metal barrier on the polysilicon layer; Depositing tungsten silicide by chemical vapor deposition and applying a photosensitizer; Patterning the photoresist film by a photo process to form a photoresist pattern; Continuously etching the tungsten silicide layer, the metal barrier layer and the polysilicon layer using the photoresist pattern as a mask to form a tungsten silicide pattern, a metal barrier pattern and a polysilicon pattern; And removing the photosensitive film pattern. 제1항에 있어서, 상기 장벽금속층을 형성하는 단계는 텅스텐 실리사이드 하부에 텅스텐 질화물, TiN 막을 증착하는 단계로 이루어짐을 특징으로 하는 장벽층을 갖는 텅스텐 폴리사이드 게이트전극 형성방법The method of claim 1, wherein the forming of the barrier metal layer comprises depositing a tungsten nitride and a TiN film under the tungsten silicide. 제2항에 있어서, 상기 텅스텐 질화물을 증착하는 단계는 PECVD와 CVD 및 스퍼터링(sputtering) 방법을 이용함을 특징으로 하는 장벽층을 갖는 텅스텐 폴리사이드 게이트전극 형성방법The method of claim 2, wherein the depositing tungsten nitride is performed using PECVD, CVD, and sputtering. 제2항에 있어서, 상기 TiN막을 증착하는 단계는 CVD, 스퍼터링(sputtering)을 이용하여 증착함을 특징으로 하는 장벽층을 갖는 텅스텐 폴리사이드 게이트전극 형성방법The method of claim 2, wherein the depositing of the TiN film is performed by CVD or sputtering. 제2항에 있어서, 상기 장벽 막의 증착 두께는 20Å 내지 200Å임을 특징으로 하는 장벽층을 갖는 텅스텐 폴리사이드 게이트전극 형성방법3. The method of claim 2, wherein the deposition thickness of the barrier film is 20 kPa to 200 kPa.
KR1019950031107A 1995-09-21 1995-09-21 Tungsten Polyside Gate Electrode Formation Method With Barrier Layer KR970018661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950031107A KR970018661A (en) 1995-09-21 1995-09-21 Tungsten Polyside Gate Electrode Formation Method With Barrier Layer

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100433509B1 (en) * 1998-08-21 2004-05-31 미크론 테크놀로지,인코포레이티드 Field effect transistors, integrated circuitry, methods of forming field effect transistor gates, and methods of forming integrated circuitry
KR100475897B1 (en) * 1997-12-29 2005-06-21 주식회사 하이닉스반도체 Manufacturing method of semiconductor device
KR100500924B1 (en) * 1999-12-30 2005-07-14 주식회사 하이닉스반도체 Method for forming tungsten electrode in memory device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100475897B1 (en) * 1997-12-29 2005-06-21 주식회사 하이닉스반도체 Manufacturing method of semiconductor device
KR100433509B1 (en) * 1998-08-21 2004-05-31 미크론 테크놀로지,인코포레이티드 Field effect transistors, integrated circuitry, methods of forming field effect transistor gates, and methods of forming integrated circuitry
US6882017B2 (en) 1998-08-21 2005-04-19 Micron Technology, Inc. Field effect transistors and integrated circuitry
US6939799B2 (en) 1998-08-21 2005-09-06 Micron Technology, Inc. Method of forming a field effect transistor and methods of forming integrated circuitry
KR100500924B1 (en) * 1999-12-30 2005-07-14 주식회사 하이닉스반도체 Method for forming tungsten electrode in memory device

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PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19950921

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