KR0151040B1 - Device Separation Method of Semiconductor Device - Google Patents

Abstract

A method of separating semiconductor devices by a local oxidation method of silicon (LOCOS) and a trench isolation method is disclosed.

The present invention provides a device isolation method for a semiconductor device having a cell array portion and a peripheral circuit portion on a semiconductor substrate, wherein each active region of the cell array portion and the peripheral circuit portion is defined using a single photolithography process. It is isolated by a trench using a trench isolation method between negative active regions, and between the active regions of the peripheral circuit portion is separated by a field oxide film using a local oxidation (LOCOS) method. Accordingly, the present invention can simplify the manufacturing process while using stable device isolation characteristics.

Description

Device Separation Method of Semiconductor Device

1A to 1B are cross-sectional views illustrating a device isolation method using a conventional local oxidation (LOCOS).

2a to 2d are process cross-sectional views illustrating a device isolation method using conventional trench isolation at each step.

3 is a plan view of a cell after a photolithography process for defining respective active regions of the cell array unit and the peripheral circuit unit in the present invention.

Figures 4a to 4h is a process cross-sectional view showing each step of the LOCOS and trench combination device separation method according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a highly integrated semiconductor device, and more particularly, to a method of separating a semiconductor device using a combination of trench isolation technology and local oxidation of silicon (LOCOS) technology.

As the semiconductor industry is highly integrated, device isolation or shrinking is required, requiring 0.45 micron technology in 64M DRAM (Mega Dynamic Random Access Memory) class and 0.25 micron technology in 256M DRAM class.

Formation of device isolation regions is an important technique in the early stages of all manufacturing process steps that determines the size of the active region and the process margin of subsequent process steps.

Isolation techniques include trench and LOCOS methods.

In general, an isolation method by LOCOS widely used in semiconductor devices will be briefly described with reference to FIGS. 1A through 1B. First, after the pad oxide film 3 and the nitride film 5 are formed on the silicon substrate 1, the nitride film of the field region (inactive region: 9) is removed by photolithography, and then the field region 9 is removed. The channel blocking ion 7 is implanted to define the inactive region 9 and the active region 11 as shown in FIG. 1A. Referring to FIG. 1B, a wafer of a structure in which the field region 9 and the active region 11 are separated is charged into an oxidation furnace, and a thermal oxidation process under a predetermined condition is performed to perform a field oxide film ( 13).

In the LOCOS isolation method, a channel blocking region 15 under which the impurity ions are redistributed due to thermal diffusion of impurity ions is provided below the field oxide layer 13 and is adjacent to the field region 9 during the thermal oxidation process. The side surface of the pad oxide film 3 is also oxidized together in the direction of the active region, causing a bird's beak phenomenon, and the field length becomes larger by the Buzz beak generation region 19 than the first field region 17. The size of 20 is made by including the length of the buzz beating area 19 in the initial field length 17 in the design arrangement. On the other hand, the size of the active area is reduced by the size of the buzz beak generation area 19 in the active area 11 of the original design arrangement, the actual active area 23 is reduced, the above-mentioned buzz beak phenomenon By limiting the limit of the fine pattern (64M or more) design rule, high integration of the semiconductor device becomes an obstacle. In addition, the LOCOS method thermally grows a field oxide film by an average of 5,000 mV. In the lower part of the nitride film selectively covered by the silicon substrate, crystal defects are generated by stress near the interface of the active region, thereby increasing leakage current between the device and the device. There is a problem.

The isolation method by LOCOS has problems such as bleed's beak due to side oxidation, crystal defects of substrate silicon due to buffer layer stress caused by thermal process, and redistribution of impurities implanted for channel blocking. As a result, the electrical characteristics and high integration of semiconductor devices have become a challenge.

In view of the problems of the LOCOS method, in particular, as the gap between devices becomes narrower, a trench isolation method capable of device separation even in a small area has been proposed. 2A to 2D are process cross-sectional views for explaining a device molecule method by trenches.

Referring to FIG. 2A, a pad oxide film 2 of about 240 kPa is grown on the silicon substrate 1 by thermal oxidation, and then the nitride film 4 is about 1,500 kPa by LPCVD (Low Pressure Chemical Vapor Deposition) method. Then, the high temperature thermal oxide film 6 is sequentially laminated to a thickness of about 1,000 mm 3, and then the high temperature thermal oxide film in the inactive region is removed by a photolithography process. In this case, the etching process uses dry etching.

Referring to FIG. 2B, the reactive ion is etched from the nitride film 4 and the pad oxide film 2 using the high temperature thermal oxide film remaining in the active region as an etching mask, and then the silicon substrate 1 is subsequently etched by dry etching. To form a trench. At this time, the high temperature thermal oxide film as an etching mask is etched together according to the etching selectivity during the nitride film / pad oxide film and the trench etching, so that a small amount remains. In addition, the trench allows narrow and wide trenches to coexist on the silicon substrate according to the design arrangement requirements of the semiconductor device. Subsequently, the sidewall oxide film 8 is formed in the trench by thermal oxidation, and the polysilicon 10 is deposited to a thickness of about 5,000 kPa or more, and then anisotropic etching is performed to fill the polysilicon only in the trench. At this time, the trench of the narrow region is completely filled, but the trench of the wide region is recessed in the center portion, thereby causing a kind of loading effect in which the filling profile varies depending on the size of the trench region.

Referring to FIG. 2C, the field oxide film 12 is formed on the top of the polysilicon filled with the trench by the thermal oxidation method, but the recessed portion of the trench in the wide region is not corrected. Subsequently, as shown in FIG. 2D, the buffer layer (high temperature thermal oxide film, nitride film, pad oxide film) is wet-etched with BOE (Buffered Oxide Etchant) and phosphoric acid solution, and then a sacrificial oxide film (not shown) is grown to wet again. By etching, the device isolation process is completed.

In the trench isolation method, the gate line and bit line are short-circuited or adversely affect the wiring characteristics during the subsequent process due to the depression of the polysilicon in the central portion of the trench, and the manufacturing yield is also reduced. Due to the Buzzbee phenomenon (R) induced during formation, it not only has a certain system to reduce the separation area, but also a certain thickness of the field oxide film is etched at the same time when BOE etching the high temperature thermal oxide film of the buffer layer. In view of this, the formation thickness of the field oxide film must be further increased, which makes the buzz bequee more prominent, which poses a significant challenge to high integration of semiconductor devices.

Recently, a trench device isolation method using CMP (Chemical Mechanical Polishing) has been developed, and many studies have been conducted. Since the trench isolation method using CMP is not based on the thermal oxidation process like the LOCOS type, the disadvantages of the LOCOS type caused by the thermal oxidation process can be reduced to some extent, but the problem of filling the trench region without voids and landfill material Other technical limitations include problems of densification, problems of dishing due to polishing of buried materials, and non-uniformity of refilled insulation profiles.

In view of this situation, in recent years, a trench isolation method is used for a cell region having a narrow separation of devices, and a trench type and a LOCOS combination type employs a LOCOS method for a peripheral circuit region with a large separation of devices. Technology is being researched.

However, the biggest problem of the above-described trench + LOCOS combination technique is that the isolation between the cells of the cell region is a trench and the isolation between the active region and the inactive region of the peripheral circuit region is performed separately by LOCOS. ) Process is required. In addition, when trenches are formed in a line, alignment between the two masks is also applied, resulting in manufacturing cost and lack of process margins in addition to the complexity of the process.

Accordingly, an object of the present invention is to provide a trench and LOCOS assembled device isolation method that can simplify the manufacturing process while improving the problems of the conventional LOCOS method and trench isolation method.

A device isolation method according to the present invention for achieving the above object is a device isolation method for a semiconductor device having a cell array portion and a peripheral circuit portion on a semiconductor substrate, wherein each active region of the cell array portion and the peripheral circuit portion is provided once. Limited using a photolithography process, and isolated by trenches using trench isolation between the active regions of the cell array, and between the active regions of the peripheral circuitry by the field oxide film using a local oxidation (LOCOS) method. It features.

According to another aspect of the present invention, in the element separation method of a semiconductor device having a cell array portion and a peripheral circuit portion on a semiconductor substrate,

Sequentially forming a pad oxide film, a first nitride film and a CVD oxide film on the entire surface of the semiconductor substrate;

Patterning the first nitride film and the CVD oxide film using a single photolithography process to define respective active regions and inactive regions of the peripheral circuit portion and the cell array portion;

Forming a field oxide layer using local oxidation (LOCOS) in an inactive region of the patterned peripheral circuit portion;

Forming a trench in an inactive region of the cell array;

Widening the trench width to connect the trenches with each other;

Forming an insulating layer on an inner wall of the trench; And

After applying the insulator to the entire surface of the resultant, using the first nitride film as a polishing stop film, the device comprising the step of separating the insulating material to the chemical mechanical polishing (CMP) characterized in that it is separated.

According to the trench and LOCOS combination device isolation method of the present invention, since the process for defining the active region of the peripheral circuit portion and the process for defining the active region of the cell array portion are performed by one photolithography process, trench isolation and LOCOS are performed. The benefits of isolation are retained while simplifying the manufacturing process.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view of a cell after a photolithography process for defining an active region, and FIGS. 4a to 4h are process cross-sectional views showing the LOCOS and trench combination device separation method according to the present invention in each step.

FIG. 4A shows a cross-sectional structure of FIG. 3 taken in the XX 'direction, in which part A represents a cell array consisting of a narrow active region and an inactive region, and part B represents an inactive region and an active region having a very wide width. A peripheral circuit region composed of regions is shown. Although not shown in FIGS. 4B to 4H, portions corresponding to those of FIG. 4A represent the same region. Part a in FIG. 3 represents an active region and part b represents an inactive region. The narrow pattern connecting the active regions a becomes an inactive region after device isolation. This will be described later.

Referring to FIG. 4A, the first step is a step of defining respective active and inactive regions of the peripheral circuit portion and the cell array portion of the semiconductor device.

Specifically, a pad oxide film 33 of about 240 mW is grown on a predetermined semiconductor substrate 31, for example, a silicon substrate by thermal oxidation, and the first nitride film 35 is laminated to a thickness of 1,500 to 2,500 mW. Thereafter, the CVD oxide film 36 is formed to a thickness of about 300 to 700 kPa by a low pressure chemical vapor deposition (LPCVD) method.

Subsequently, the first nitride film 35 and the CVD oxide film 37 in the inactive region (element isolation region) are removed by only one photolithography process using a mask having a pattern corresponding to the top view of FIG. 3. Each active area and inactive area of the part A and the peripheral circuit part B are defined. In the present invention, the first nitride film 35 and the CVD oxide film 37 are used in one photolithography process to define each active region and each non-active region of the peripheral circuit portion B and the cell array portion A. By patterning. The photolithography process of this process opens the entire area of the peripheral circuit portion (B) and the cell array portion (A), and is a simplified process without causing problems of limitation and misalignment of the photolithography pattern formation.

The second process is a process of forming the field oxide film 40 using local oxidation (LOCOS) in the inactive region of the patterned peripheral circuit portion (B).

At this time, in order to protect the region other than the high temperature thermal oxidation process for forming the field oxide film 40, before performing the LOCOS process, as shown in FIG. A step of forming a second nitride film 39 which is buried between the cells of (A) and formed on both side walls of the active region of the peripheral circuit portion is added.

That is, after coating the insulator, for example, SiN, to a thickness sufficient to cover the CVD oxide film 37 on the entire surface of the resultant after the first process, the cell array portion A having a narrow field region is The CVD oxide film 37 is used as an etching deposition film, and the field region of the peripheral circuit portion B performs an etch-back process using the pad oxide film 33 as an etching stop film. As a result, as shown in FIG. 4B, the second nitride film 39a is buried in the narrow cell region, and spacers 39b are formed on both sides of the inactive region of the exposed peripheral circuit portion.

Subsequently, the pad oxide film 33 exposed by the etch-back process is selectively oxidized (LOCOS) to perform a field oxide film 40 having a thickness of about 3000 to 5000 kPa as shown in FIG. 4C. To form. At this time, the inactive region of the cell array unit A is not thermally oxidized by the buried second nitride film 39a.

The third step is to form at least one trench 42 in the inactive region of the cell array unit A. FIG. Referring to FIG. 4D, after the buried second nitride layer 39a is removed, the silicon substrate 30 is etched using the first nitride layer 35 and the CVD oxide layer 37 as an etch mask to form a trench 42. To form. In this case, the peripheral circuit portion B is protected by the field oxide film 40. The trench 42 formed in the cell array may reduce its width to 0.3 μm or less to facilitate the subsequent investment. In addition, the trench 42 may be configured as a narrow area and a wide area on the silicon substrate according to the design arrangement requirements of the semiconductor device.

The fourth step is to widen the trench width in order to connect the trenches 42 with each other. That is, when the silicon substrate 31 is etched by using an isotropic etching process, as shown in FIG. 4E, the trench pattern is widened and the silicon below the active region in which the pad oxide layer 33 is formed is removed, thereby adjoining the trenches 42. ) Are connected to each other and the active region is isolated. The process of expanding the trench width is performed by isotropic etching using chemical dry etching (CDE). The CDE process is also performed until adjacent trenches are connected to each other.

Referring to FIG. 4E, the fifth process is a process of forming the insulating layer 44 on the inner wall of the trench 42 widened through the above process, and performs the thermal oxidation process to form the insulating layer 44.

In the sixth step, after the insulation including the trench 42 is sufficiently coated on the entire surface with a thickness sufficient to cover the CVD oxide film 37, the first nitride film 35 is polished. It is used to process the insulator CMP (Chemical Mechanical Polishing).

First, referring to FIG. 4F, an insulator 46 for filling the trench 42 is coated. At this time, the insulating material 46 is preferably applied by using a CVD oxide film, for example, low pressure CVD (LPCVD) or physical enhansed CVD (PECVD), the thickness is determined in consideration of the subsequent polishing process.

Next, as shown in FIG. 4G, a mechanical chemical polishing process (CMP) is performed until the surface of the first nitride film pattern 35 is exposed. Instead of the CMP, the surface of the first nitride layer 35 may be exposed through reactive ion etching. In this case, the pad oxide film 33 and the first nitride film turn 35 are formed in the active regions of the cell array portion and the peripheral circuit portion.

At this time, since the peripheral circuit portion B having a large inactive region (field region) is isolated by the field oxide film 40 having a small thickness, a fundamental problem of CMP, which occurs frequently in this region, improves dishing. can do. The reason is that since the trench having a large step height is not widely formed in the field region, the CMP process can be performed in a state where the level of the insulation 46 buried shell cell region A and the peripheral circuit region B is approximately equal. to be. In addition, when the field oxide film 40 is densified, dishing may be further reduced.

Furthermore, since the field oxide film 40 in the wide area is made of a thermal oxide film having a significantly lower polishing rate than other oxide films, it helps to planarize the substrate surface.

Finally, as shown in FIG. 4H, the remaining first nitride film 35 and the pad oxide film 33 pattern are removed to complete the separation process between the devices. In this case, the first nitride layer 35 pattern is removed by using reactive ion etching, and the pad oxide layer 33 is removed by wet etching using a solution of any one of diluted HF and BOE (Buffered Oxide Etchant). It is desirable to.

As described above, according to the trench and LOCOS combination device isolation method according to the present invention, a peripheral circuit portion having a wide field region is isolated by a field oxide film without a step, and a cell region having a narrow field region is isolated by a trench. Dishes can be reduced. As a result, stable element isolation characteristics can be obtained. In addition, the process for defining the active region of the peripheral circuit portion and the process for defining the active region of the cell array portion are performed by one photolithography process, thus simplifying the manufacturing process while using the advantages of trench isolation and LOCOS isolation. It has an effect that can be done.

Claims (9)

In a device isolation method of a semiconductor device having a cell array portion and a peripheral circuit portion on a semiconductor substrate, each active region of the cell array portion and the peripheral circuit portion is defined by one photolithography process, and the cell array portion is activated. The region is separated by a trench using a trench isolation method, and the active region of the peripheral circuit portion is separated by a field oxide film using a local oxidation (LOCOS) method. The method of claim 1, wherein the cell and the cell of the cell array unit are connected to each other by a line narrower than the width of the cell. A device isolation method for a semiconductor device having a cell array portion and a peripheral circuit portion on a semiconductor substrate, comprising: a) sequentially forming a pad oxide film, a first nitride film, and a CVD oxide film on an entire surface of the semiconductor substrate; b) patterning the first nitride film and the CVD oxide film using a single photolithography process to define respective active regions and inactive regions of the peripheral circuit portion and the cell array portion; c) forming a field oxide film using local oxidation (LOCOS) in an inactive region of the patterned peripheral circuit portion; d) forming a trench in an inactive region of the cell array; e) widening the trench width to connect the trenches with each other; f) forming an insulating layer on an inner wall of the trench; And e) applying the insulating material to the entire surface of the resultant, and then using the first nitride film as a polishing stop film, and performing the chemical mechanical polishing (CMP) of the insulating material. 4. The method of claim 3, wherein, before the step (c), in order to protect the device from the high temperature LOCOS process for forming the field oxide film, the peripheral circuit portion is embedded between the cells and the cells of the cell array portion having a narrow spacing. And forming a second nitride film remaining as a spacer on the sidewalls. The method of claim 4, wherein the second nitride layer is formed by an etch-back process. 4. The method of claim 3, wherein the step (e) of widening the trench width is performed by isotropic etching using chemical dry etching (CDE). 7. The method of claim 3 or 6, wherein the CDE process is performed until adjacent trenches are connected to each other. 4. The device isolation method according to claim 3, further comprising a step of removing the remaining first nitride film and pad oxide film pattern after the CMP process of step (e). The method of claim 8, wherein the first nitride layer pattern is removed by using reactive ion etching, and the pad oxide layer is removed by wet etching using a solution of any one of diluted HF and buffered oxide etchant (BOE). A device isolation method for a semiconductor device.