KR100269623B1 - A method of isolating semiconductor devices - Google Patents
A method of isolating semiconductor devices Download PDFInfo
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- KR100269623B1 KR100269623B1 KR1019980034793A KR19980034793A KR100269623B1 KR 100269623 B1 KR100269623 B1 KR 100269623B1 KR 1019980034793 A KR1019980034793 A KR 1019980034793A KR 19980034793 A KR19980034793 A KR 19980034793A KR 100269623 B1 KR100269623 B1 KR 100269623B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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Abstract
본 발명은 반도체장치의 소자격리방법에 관한 것으로서, 특히, 소자격리를 위한 반도체기판의 트렌치를 매립하는 절연물질의 트렌치 상단 모서리부위에서의 모양을 둥글게 형성하도록 하여 소자격리 공정이 완성되었을 때 기판의 표면과 절연물질의 표면이 완만하게 연결되도록 하므로서 게이트유도 누설전류(3-dimensional gate induced leakage)를 크게 감소시키고 이후 형성되는 게이트산화막의 신뢰성을 향상시키도록한 트렌치(trench)를 이용한 반도체장치의 소자격리방법에 관한 것이다. 본 발명은 반도체기판 상에 마스크층을 형성하고 반도체기판의 소정 부분이 노출되도록 패터닝하여 소자격리영역과 활성영역을 한정하는 공정과, 반도체기판의 노출된 부분에 소정 깊이의 트렌치를 형성하는 공정과, 트렌치 부위의 노출된 반도체기판의 표면에 버퍼산화막을 형성하는 공정과, 트렌치를 채우는 절연층을 기판의 전면에 형성하는 공정과, 절연층의 일부를 제거하여 트렌치 내부에 위치하는 제 1 절연층과 마스크층 위에 위치하는 제 2 절연층으로 분리시켜서 트렌치 상부 모서리 부위의 버퍼산화막 일부를 노출시키는 단계와, 기판의 전면에 희생산화막을 형성하는 단계와, 트렌치 상부 모서리 부위의 일부 희생산화막을 제외하는 희생산화막과 제 2 절연층 그리고 마스크층을 제거하여 제 1 절연층의 표면과 반도체기판의 표면을 노출시키는 단계로 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, and more particularly, to form a shape at a top edge of a trench of an insulating material filling a trench of a semiconductor substrate for device isolation. The device of the semiconductor device using a trench to smoothly connect the surface and the surface of the insulating material to greatly reduce the 3-dimensional gate induced leakage current and improve the reliability of the gate oxide film formed later To containment methods. The present invention provides a method of forming a mask layer on a semiconductor substrate and patterning the semiconductor substrate to expose a predetermined portion of the semiconductor substrate to define an isolation region and an active region, and forming a trench having a predetermined depth in the exposed portion of the semiconductor substrate. Forming a buffer oxide film on the exposed surface of the semiconductor substrate in the trench, forming an insulating layer filling the trench on the entire surface of the substrate, and removing a portion of the insulating layer, the first insulating layer being located inside the trench. Exposing a portion of the buffer oxide film in the upper corner portion of the trench, forming a sacrificial oxide film on the entire surface of the substrate, and removing a portion of the sacrificial oxide film in the trench upper corner portion. When the sacrificial oxide film, the second insulating layer and the mask layer are removed, the surface of the first insulating layer and the surface of the semiconductor substrate are exposed. The key consists of steps.
Description
본 발명은 반도체장치의 소자격리방법에 관한 것으로서, 특히, 소자격리를 위한 반도체기판의 트렌치를 매립하는 절연물질의 트렌치 상단 모서리부위에서의 모양을 둥글게 형성하도록 하여 소자격리 공정이 완성되었을 때 기판의 표면과 절연물질의 표면이 완만하게 연결되도록 하므로서 게이트유도 누설전류(3-dimensional gate induced leakage)를 크게 감소시키고 이후 형성되는 게이트산화막의 신뢰성을 향상시키도록한 트렌치(trench)를 이용한 반도체장치의 소자격리방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, and more particularly, to form a shape at a top edge of a trench of an insulating material filling a trench of a semiconductor substrate for device isolation. The device of the semiconductor device using a trench to smoothly connect the surface and the surface of the insulating material to greatly reduce the 3-dimensional gate induced leakage current and improve the reliability of the gate oxide film formed later To containment methods.
반도체장치의 집적화가 거듭되면서 반도체장치의 상당한 면적을 점유하는 소자격리영역을 줄이기 위한 기술 개발이 활발히 진행되고 있다.As the integration of semiconductor devices continues, technology development for reducing the device isolation region occupying a considerable area of the semiconductor device is actively progressing.
반도체장치의 집적화가 거듭되면서 반도체장치의 상당한 면적을 점유하는 소자격리영역을 줄이기 위한 기술 개발이 활발히 진행되고 있다.As the integration of semiconductor devices continues, technology development for reducing the device isolation region occupying a considerable area of the semiconductor device is actively progressing.
일반적으로 반도체장치는 LOCOS(Local Oxidation of Silicon) 방법으로 소자를 격리하였다. LOCOS 방법은 활성영역을 한정하는 산화마스크인 질화막과 반도체기판의 열적 특성이 다르기 때문에 발생하는 스트레스를 해소하기 위하여 질화막과 반도체기판 사이에 박막의 버퍼산화막(buffer oxide)을 형성하고 산화시켜 소자격리영역으로 이용되는 필드산화막를 형성한다. 상기에서 필드산화막은 반도체기판의 수직 방향으로 성장할 뿐만 아니라 산화체(Oxidant : 02)가 버퍼산화막을 따라 수평 방향으로도 확산되므로 질화막의 패턴 엣지(edage)밑으로 성장되게 되는 특징을 갖는다.In general, semiconductor devices have isolated devices by a local oxide of silicon (LOCOS) method. In the LOCOS method, a thin film buffer oxide is formed between the nitride film and the semiconductor substrate and oxidized to eliminate stress caused by the thermal characteristics of the nitride film and the semiconductor substrate, which are the oxide masks that define the active region. A field oxide film to be used is formed. The field oxide film is grown not only in the vertical direction of the semiconductor substrate but also in the oxidant (Oxidant: 0 2 ) in the horizontal direction along the buffer oxide film, so that it is grown under the pattern edge of the nitride film.
이와같이 필드산화막이 활성 영역을 잠식하는 현상을 그 형상이 새의 부리 모양과 유사하여 버즈 비크(Bird's Beak)이라 한다. 이러한 버드 비크의 길이는 필드산화막 두께의 1/2이나 된다. 그러므로, 활성 영역의 크기가 감소되는 것을 줄이기 위하여는 버즈 비크의 길이를 최소화 하여야 한다.The phenomenon in which the field oxide film encroaches on the active region is called Bird's Beak because its shape is similar to that of a bird's beak. This bird beak is half the thickness of the field oxide film. Therefore, the length of the buzz bek should be minimized to reduce the size of the active area.
버즈 비크의 길이를 줄이기 위한 방법으로 필드산화막의 두께를 감소시키는 방식이 도입되었으나 16M DRAM급 이상에서 필드산화막의 두께를 감소시키면 배선과 반도체기판 사이의 정전 용량이 증가되어 신호전달 속도가 저하되는 문제가 발생된다. 또한, 소자의 게이트로 사용되는 배선에 의해 소자 사이의 격리영역에 형성되는 기생 트랜지스터의 문턱전압(Vt)이 저하되어 소자 사이의 격리특성이 저하되는 문제점이 있다.In order to reduce the length of the buzz beak, a method of reducing the thickness of the field oxide film was introduced. However, when the thickness of the field oxide film is reduced in the 16M DRAM class or higher, the capacitance between the wiring and the semiconductor substrate increases and the signal transmission speed decreases. Is generated. In addition, there is a problem that the threshold voltage Vt of the parasitic transistor formed in the isolation region between the elements is lowered by the wiring used as the gate of the element, thereby lowering the isolation characteristic between the elements.
따라서, 버즈 비크의 길이를 감소시키면서 소자격리를 하는 방법이 개발되었다. 버즈 비크의 길이를 감소시키면서 소자격리를 하는 방법으로는 스트레스 완충용 버퍼산화막의 두께를 낮추고 반도체기판과 질화막 사이에 다결정실리콘층을 개입시킨 PBLOCOS(Poly Si Buffered LOCOS), 버퍼산화막의 측벽을 질화막으로 보호하는 SILO(Sealed Interface LOCOS), 그리고, 반도체기판 내에 필드산화막을 형성시키는 리세스(Recessed) LOCOS 기술들이 있다.Thus, a method for device isolation while reducing the length of the buzz bee has been developed. As a method of isolation of the device while reducing the length of the buzz beak, the thickness of the stress buffer buffer oxide film is reduced, and the polysilicon buffer layer (PBLOCOS) and the sidewall of the buffer oxide film are interposed between the semiconductor substrate and the nitride film. There are shielded interface LOCOS (SILO) to protect, and recessed LOCOS techniques to form a field oxide film in a semiconductor substrate.
그러나, 상기 기술들은 격리 영역 표면의 평탄도와 정밀한 디자인 룰(Design Rule) 등의 이유로 256M DRAM급 이상의 집적도를 갖는 차세대 소자의 소자격리기술로 적합하지 않게 되었다.However, the above techniques are not suitable for device isolation technology of next-generation devices having an integration level of 256M DRAM or more due to the flatness of the isolation region surface and the precise design rule.
따라서, 기존의 여러 소자격리기술들의 문제점을 극복할 수 있는 BOX(buried oxide)형 얕은트렌치소자격리(shallow trench isolation) 기술이 개발되었다. BOX형 소자격리기술 반도체기판에 트렌치를 형성하고 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 산화실리콘 또는 불순물이 도핑되지 않은 다결정실리콘을 매립한 구조를 갖는다. 그러므로, 버즈 비크가 발생되지 않아 활성영역의 손실이 전혀 없으며, 또한, 산화막을 메립하고 에치 백(etch back)하여 평탄한 표면을 얻을 수 있다.Therefore, a BOX (buried oxide) type shallow trench isolation technology has been developed that can overcome the problems of various device isolation technologies. BOX type device isolation technology A trench is formed on a semiconductor substrate and has a structure in which silicon oxide or polycrystalline silicon which is not doped with impurities is embedded by chemical vapor deposition (hereinafter referred to as CVD). Therefore, no buzz beaking occurs, there is no loss of the active region, and a flat surface can be obtained by embedding and etching back the oxide film.
도 1a 내지 도 1d는 종래 기술에 따른 얕은 트렌치를 이용한 소자격리방법을 도시하는 공정도이다.1A to 1D are process diagrams illustrating a device isolation method using a shallow trench according to the prior art.
도 1a를 참조하면, 반도체기판(11) 상에 열산화 방법으로 버퍼산화막(13)을 형성하고, 이 버퍼산화막(13) 상에 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 질화실리콘을 증착하여 마스크층(15)을 형성한다.Referring to FIG. 1A, a buffer oxide film 13 is formed on a semiconductor substrate 11 by a thermal oxidation method, and chemical vapor deposition (hereinafter referred to as CVD) is performed on the buffer oxide film 13. Silicon nitride is deposited to form a mask layer 15.
그리고, 마스크층(15) 및 버퍼산화막(13)을 포토리쏘그래피 방법으로 반도체기판(11)이 노출되도록 순차적으로 패터닝하여 소자격리영역과 활성영역을 한정한다.The mask layer 15 and the buffer oxide film 13 are sequentially patterned to expose the semiconductor substrate 11 by a photolithography method to define the device isolation region and the active region.
도 1b를 참조하면, 마스크층(15)을 마스크로 사용하여 반도체기판(11)의 노출된 소자격리영역을 소정 깊이로 식각하여 트렌치(17)를 형성한다. 상기에서 트렌치(17)를 반응성이온식각(Reactive Ion Etching : 이하, RIE라 칭함)이나 플라즈마 식각 등으로 이방성 식각하여 형성한다.Referring to FIG. 1B, the trench 17 is formed by etching the exposed device isolation region of the semiconductor substrate 11 to a predetermined depth using the mask layer 15 as a mask. The trench 17 is formed by anisotropic etching by reactive ion etching (hereinafter referred to as RIE) or plasma etching.
도 1c를 참조하면, 마스크층(15) 상에 산화실리콘을 트렌치(17)를 채우도록 CVD 방법으로 증착한다. 그리고, 산화실리콘을 마스크층(15)이 노출되어 화학-기계적연마(Chemical-Mechanical Polishing : 이하, CMP라 칭함) 방법 또는 RIE 방법으로 에치 백하여 트렌치(17) 내에만 잔류되도록 한다. 이 때, 트렌치(17) 내에 잔류하는 산화실리콘은 소자를 분리하는 필드산화막(19)이 된다.Referring to FIG. 1C, silicon oxide is deposited on the mask layer 15 by CVD to fill the trench 17. Then, the silicon oxide is exposed to the mask layer 15 to be etched back by chemical-mechanical polishing (hereinafter referred to as CMP) method or RIE method so as to remain only in the trench 17. At this time, the silicon oxide remaining in the trench 17 becomes a field oxide film 19 separating the elements.
도 1d를 참조하면, 마스크층(15) 및 버퍼산화막(13)을 습식 식각 방법으로 순차적으로 제거하여 반도체기판(11)의 활성영역을 노출시킨다. 이 때, 필드산화막(19)의 반도체기판(11)의 표면 보다 높은 부분도 식각되어 단차가 감소된다.Referring to FIG. 1D, the mask layer 15 and the buffer oxide film 13 are sequentially removed by a wet etching method to expose the active region of the semiconductor substrate 11. At this time, a portion higher than the surface of the semiconductor substrate 11 of the field oxide film 19 is also etched to reduce the level difference.
상술한 종래의 반도체장치의 소자격리방법은 마스크층 및 버퍼산화막을 습식 식각하여 제거하면서 필드산화막의 반도체기판 표면 보다 높은 부분도 식각할 때 이 필드산화막은 습식 식각에 의해 트렌치와 접합 부분의 상부에 홈(recess hump)이 형성된다.The device isolation method of the conventional semiconductor device described above uses a wet etching process to remove the mask layer and the buffer oxide film while etching the portion higher than the surface of the semiconductor substrate of the field oxide film, and the field oxide film is formed on the upper portion of the trench and the junction by wet etching. A recess hump is formed.
이 후에 게이트산화막과 다결정실리콘으로 게이트를 형성할 때 홈이 형성된 부분에서 게이트산화막의 두께가 감소되고 이 홈의 내부에 다결정실리콘이 잔류하게 되므로 게이트가 활성영역을 에워싸는 구조가 된다. 그러므로, 소자 구동시 홈의 내부에 잔류하는 다결정실리콘에 의해 전계가 증가되어 누설 전류가 흐르며, 또한, 게이트산화막의 두께가 감소에 의해 전계가 집중되어 소자 특성을 저하시키는 문제점이 있다.Subsequently, when the gate is formed of the gate oxide film and the polysilicon, the thickness of the gate oxide film is reduced in the grooved portion, and the polysilicon remains in the groove so that the gate surrounds the active region. Therefore, there is a problem that the electric field is increased due to the polycrystalline silicon remaining inside the groove during device driving, and the leakage current flows, and the electric field is concentrated by decreasing the thickness of the gate oxide film, thereby degrading device characteristics.
따라서, 본 발명의 목적은 트렌치와 접합 부분의 상부에 홈이 형성되는 것을 방지하여 소자의 신뢰성을 향상시킬 수 있는 반도체장치의 소자격리방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a device isolation method of a semiconductor device that can improve the reliability of the device by preventing the groove formed on the trench and the junction portion.
상기 목적을 달성하기 위해 본 발명에 따른 반도체장치의 소자격리방법은 반도체기판 상에 마스크층을 형성하고 반도체기판의 소정 부분이 노출되도록 패터닝하여 소자격리영역과 활성영역을 한정하는 공정과, 반도체기판의 노출된 부분에 소정 깊이의 트렌치를 형성하는 공정과, 트렌치 부위의 노출된 반도체기판의 표면에 버퍼산화막을 형성하는 공정과, 트렌치를 채우는 절연층을 기판의 전면에 형성하는 공정과, 절연층의 일부를 제거하여 트렌치 내부에 위치하는 제 1 절연층과 마스크층 위에 위치하는 제 2 절연층으로 분리시켜서 트렌치 상부 모서리 부위의 버퍼산화막 일부를 노출시키는 단계와, 기판의 전면에 희생산화막을 형성하는 단계와, 트렌치 상부 모서리 부위 및 제 1 절연층 위의 일부 희생산화막을 제외하는 희생산화막과 제 2 절연층 그리고 마스크층을 제거하여 제 1 절연층의 표면과 반도체기판의 표면을 노출시키는 단계를 포함하는 공정으로 이루어진다.In order to achieve the above object, a device isolation method of a semiconductor device according to the present invention includes forming a mask layer on a semiconductor substrate and patterning the semiconductor substrate to expose a predetermined portion of the semiconductor substrate, thereby defining a device isolation region and an active region. Forming a trench having a predetermined depth in the exposed portion of the trench, forming a buffer oxide film on the surface of the exposed semiconductor substrate in the trench, forming an insulating layer filling the trench on the entire surface of the substrate, and Removing a portion of the insulating layer to form a first insulating layer in the trench and a second insulating layer on the mask layer to expose a portion of the buffer oxide layer in the upper corner portion of the trench, and forming a sacrificial oxide layer on the entire surface of the substrate. And the sacrificial oxide and the second insulation except for the trench upper corner portion and some sacrificial oxide on the first insulating layer. And it consists of a process comprising the step of removing the mask layer to expose the surface of the semiconductor substrate surface of the first insulating layer.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 소자격리방법을 도시하는 공정단면도1A to 1D are process cross-sectional views showing a device isolation method of a semiconductor device according to the prior art.
도 2a 내지 도 2e는 본 발명에 따른 반도체장치의 소자격리방법을 도시하는 공정단면도2A to 2E are process cross-sectional views showing a device isolation method for a semiconductor device according to the present invention.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 얕은 트렌치를 이용한 반도체장치의 소자격리방법을 도시하는 공정도이다.2A to 2E are process diagrams illustrating a device isolation method of a semiconductor device using a shallow trench according to the present invention.
도 2a를 참조하면, 반도체기판(21) 상에 열산화 방법으로 제 1 버퍼산화막(22)을 형성하고, 이 제 1 버퍼산화막(22) 상에 CVD 방법으로 질화실리콘을 증착하여 마스크층(23)을 형성한다.Referring to FIG. 2A, a first buffer oxide film 22 is formed on a semiconductor substrate 21 by a thermal oxidation method, and silicon nitride is deposited on the first buffer oxide film 22 by a CVD method to form a mask layer 23. ).
그리고, 마스크층(23) 및 제 1 버퍼산화막(22)을 포토리쏘그래피 방법으로 반도체기판(21)이 노출되도록 순차적으로 패터닝하여 소자격리영역과 활성영역을 한정한다.The mask layer 23 and the first buffer oxide film 22 are sequentially patterned to expose the semiconductor substrate 21 by a photolithography method to define the device isolation region and the active region.
그 다음, 마스크층(23)을 마스크로 사용하여 반도체기판(21)의 노출된 부분, 즉, 소자격리영역을 소정 깊이로 식각하여 트렌치를 형성한다. 상기에서 트렌치를 RIE 또는 플라즈마 식각 등으로 이방성 식각하여 형성한다.Next, using the mask layer 23 as a mask, an exposed portion of the semiconductor substrate 21, that is, an isolation region, is etched to a predetermined depth to form a trench. The trench is formed by anisotropic etching using RIE or plasma etching.
도 2b를 참조하면, 노출된 기판(21)의 표면 즉, 트렌치 표면에 열산화를 실시하여 제 2 버퍼산화막(24)을 노출된 트렌치 vuaisdp 형성한다.Referring to FIG. 2B, thermal oxidation is performed on the exposed surface of the substrate 21, that is, the trench surface, to form the exposed trench vuaisdp of the second buffer oxide layer 24.
그리고 마스크층(23) 표면 및 제 2 버퍼산화막(24) 표면에 산화실리콘으로 에이치엘디층(high temperature low pressure dielectric, 250)을 트렌치를 채우도록 CVD 방법으로 증착하여 형성한다.A high temperature low pressure dielectric (250) 250 is formed on the surface of the mask layer 23 and the surface of the second buffer oxide film 24 by CVD to fill the trench.
도 2c를 참조하면, 노출된 에이치엘디층(250)에 습식식각을 실시하여 트렌치 상부 모서리 부위의 제 2 버퍼산화막(24)의 일부 표면이 형성하도록 한다. 따라서, 잔류한 에이치엘디층(250)은 제 1 에이치엘디층(251)과 제 2 에이치엘디층(252)으로 분리되며, 트렌치 내에 잔류하는 제 1 에이치엘디층(251)은소자를 분리하는 필드산화막이 된다. 이와 같이 제 2 버퍼산화막(24)의 일부를 노출시키는 이유는 종래기술에서 트렌치 상부 모서리 부위에 홈이 생기는 것을 방지하기 위하여 이 부위에 별도의 산화막을 형성하기 위해서이다.Referring to FIG. 2C, wet etching is performed on the exposed HDL layer 250 to form a part of the surface of the second buffer oxide layer 24 in the upper corner portion of the trench. Therefore, the remaining HLC layer 250 is separated into a first HLC layer 251 and a second HLC layer 252, and the first HLC layer 251 remaining in the trench is a field oxide film that separates devices. Becomes The reason for exposing a part of the second buffer oxide film 24 is to form a separate oxide film in this portion in order to prevent grooves in the upper corner portion of the trench in the prior art.
도 2d를 참조하면, 기판(21)의 전면에 습식산화를 실시하여 제 1 에이치엘디층(251)의 표면, 제 2 에이치엘디층(252)의 노출된 표면과 노출된 제 2 버퍼산화막(24)의 표면에 희생산화막(26)을 형성한다. 이때, 산화막은 트렌치 상부 모서리(A1) 부위에서도 형성되어 도면에서와 같이 마스크층(23)의 하부에도 일부 침투되어 부풀어오른 모습을 같게 된다.Referring to FIG. 2D, wet oxidation is performed on the entire surface of the substrate 21 to expose the surface of the first HDL layer 251, the exposed surface of the second HDL layer 252, and the exposed second buffer oxide layer 24. A sacrificial oxide film 26 is formed on the surface of the substrate. At this time, the oxide film is also formed in the upper portion of the trench (A1), and partially penetrates into the lower portion of the mask layer 23 as shown in the figure to have a swelling state.
도 2e를 참조하면, 제 1 절연층(251) 상부의 희생산화막(26)의 일부와 제 2 절연층(252) 표면의 희생산화막(26) 그리고 제 2 에이치엘디층(252), 마스크층(23) 및 제 1 버퍼산화막(22)을 습식 식각 방법으로 순차적으로 제거하여 반도체기판(21)의 활성영역을 노출시킨다.Referring to FIG. 2E, a portion of the sacrificial oxide film 26 on the first insulating layer 251, the sacrificial oxide film 26 on the surface of the second insulating layer 252, the second HDL layer 252, and the mask layer ( 23) and the first buffer oxide layer 22 are sequentially removed by a wet etching method to expose the active region of the semiconductor substrate 21.
이 때, 종래 기술에서는 필드산화막이 트렌치의 상부 모서리 부분에서 수직 및 수평방향으로 식각되므로 트렌치와 접합 부분의 상부에 홈이 형성되지만, 본 발명에서는 이 부위(A2)에 희생산화막(26)이 형성되어 있으므로 이러한 홈(recess hump)이 형성되는 것을 방지할 수 있다.At this time, in the prior art, since the field oxide film is etched in the vertical and horizontal directions at the upper edge portion of the trench, a groove is formed in the upper portion of the trench and the junction portion, but in the present invention, the sacrificial oxide film 26 is formed in this portion A2. Since the recess hump can be prevented.
따라서 종래기술에서 홈이 생기는 이 부위(A2)는 희생산화막(26) 일부와 제 1 버퍼산화막(24) 일부가 형성하는 단면이 둥근 형태를 갖는 트렌치 상부 모서리의 프로필을 갖는다.Therefore, the region A2 in which the groove is formed in the prior art has a profile of a trench upper corner having a rounded cross section formed by a portion of the sacrificial oxide layer 26 and a portion of the first buffer oxide layer 24.
상술한 바와 같이 소자격리공정이 완성된 반도체기판의 표면은 소자격리 필드산화막의 표면과 완만하게 연결되는 즉, 평탄화된 형태를 갖는다.As described above, the surface of the semiconductor substrate on which the device isolation process is completed has a flattened shape that is gently connected to the surface of the device isolation field oxide film.
따라서, 본 발명은 이후 공정인 게이트산화막 및 게이트 형성시 게이트산화막이 얇게 형성되거나 게이트의 식각 잔류물이 남는 것을 방지할 수 있어서 게이트유도 누설전류(3-dimensional gate induced leakage)를 크게 감소시키고 이후 형성되는 게이트산화막의 신뢰성을 향상시키는 장점이 있다.Accordingly, the present invention can prevent the gate oxide film from being thinly formed or the etching residue of the gate from remaining during the gate oxide film and the gate formation, thereby greatly reducing the gate induced leakage current (3-dimensional gate induced leakage) and then forming the gate oxide film. There is an advantage of improving the reliability of the gate oxide film.
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