KR0147156B1 - Film on chip package and manufacturing method - Google Patents
Film on chip package and manufacturing methodInfo
- Publication number
- KR0147156B1 KR0147156B1 KR1019950009995A KR19950009995A KR0147156B1 KR 0147156 B1 KR0147156 B1 KR 0147156B1 KR 1019950009995 A KR1019950009995 A KR 1019950009995A KR 19950009995 A KR19950009995 A KR 19950009995A KR 0147156 B1 KR0147156 B1 KR 0147156B1
- Authority
- KR
- South Korea
- Prior art keywords
- chip
- film
- insulating film
- package
- conductor
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 18
- 239000004020 conductor Substances 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 239000011347 resin Substances 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 6
- 238000007906 compression Methods 0.000 claims 1
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 21
- 229910052737 gold Inorganic materials 0.000 abstract description 19
- 239000010931 gold Substances 0.000 abstract description 19
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 241000416536 Euproctis pseudoconspersa Species 0.000 description 1
- 238000003912 environmental pollution Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
본 발명은 반도체 패키지에서 필름 온 칩(FILM ON CHIP) 패키지에 관한 것으로, 특히 절연 필름상에 칩을 부착하여 골드(GOLD) 프린팅에 의한 패턴을 형성하는 반도체 패키지에 관한 것이다. 칩의 본드패드부분과 절연 필름의 펀치부가 정확히 일치하도록 절연 필름상에 칩을 부착하고, 이러한 상태에서 필름에 골드(GOLD)로 프린팅하여 패턴을 형성토록 함을 특징으로 하여, 칩 설계 및 리드 구성 설계등에 구애를 받지 않고 사용자가 리드를 변경하여 설계가능토록 제작이 가능한 패키지를 제공할 수 있어서 매우 유용하다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a film on chip package in a semiconductor package, and more particularly, to a semiconductor package in which a chip is attached to an insulating film to form a pattern by gold printing. The chip is attached to the insulating film so that the bond pad portion of the chip and the punched portion of the insulating film are exactly matched, and in this state, the film is printed with gold to form a pattern. Regardless of the design, it is very useful to provide a package that allows the user to change the lead and make the design possible.
Description
제1도는 본 발명 필름 온 칩(FILM ON CHIP) 패키지의 일 실시예를 보여주는 구성 단면도.1 is a cross-sectional view showing an embodiment of the present invention film on chip (FILM ON CHIP) package.
제2도는 제1도의 평면도.2 is a plan view of FIG.
제3도는 본 발명 필름 온 칩(FILM ON CHIP) 패키지의 제조 공정을 보여주는 도면으로,3 is a view showing a manufacturing process of the film on chip (FILM ON CHIP) package of the present invention,
(a)도는 칩과 절연 필름을 접착하는 과정을 나타내는 실시도.(a) is an embodiment showing a process of bonding the chip and the insulating film.
(b)도는 칩과 절연 필름을 접착 후 골드 프린팅을 실시한 상태의 사시도.(b) is a perspective view of a state where gold printing is performed after bonding a chip and an insulating film.
(c)도는 (b)도의 단면도.(c) is sectional drawing of (b).
(d)도는 골드 프린팅 완료후 절연필름을 접착한 상태의 단면도.(d) is a sectional view of the insulating film bonded after the completion of gold printing.
(e)도는 칩 하면에 도포를 실시한 상태의 단면도.(e) is sectional drawing of the state which apply | coated to the lower surface of a chip | tip.
(f)도는 필름을 커팅하여 완성된 필름 온 칩(FILM ON CHIP) 패키지를 보여주기 위한 도면이다.(f) is a view showing a film on chip (FILM ON CHIP) package completed by cutting the film.
본 발명은 반도체 패키지에서 필름 온 칩(FILM ON CHIP) 패키지에 관한 것으로, 특히 칩 위에 절연 필름을 부착하여 필름에 도전체를 프린팅하는 방식을 사용한 반도체 패키지 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a film on chip package in a semiconductor package, and more particularly, to a semiconductor package using a method of printing a conductor on a film by attaching an insulating film on the chip, and a method of manufacturing the same.
일반적으로, 반도체 패키지를 제조하는 공정은 웨이퍼를 단일 칩으로 분리하여, 분리된 칩을 리드 프레임에 접합한 후 칩과 리드 프레임을 배선하는 와이어본딩을 하고, 수지에 의해 칩을 봉하는 몰딩 과정(이후 과정은 생략한다)을 순차적으로 수행하였다.In general, a process of manufacturing a semiconductor package is to separate the wafer into a single chip, to bond the separated chip to the lead frame, and to wire bond the wiring between the chip and the lead frame, and to seal the chip by resin ( The procedure is omitted).
상기와 같은 일반적인 반도체 패키지를 형성함에 있어서, 와이어본딩은 금선(골드)을 열압착법, 초음파법 등을 이용하여 본드패드와 내부리드를 결합하는데, 이때 칩이 복잡해짐에 따라 칩의 설계 및 리드를 구성하는 과정에서 많은 장애가 발생하였다.In forming the general semiconductor package as described above, wire bonding combines the bond pad and the inner lead by using a gold wire (gold) by thermocompression method, ultrasonic method, etc. At this time, the chip design and lead as the chip becomes complicated Many obstacles occurred in the process of constructing.
이를 위해 리드 온 칩 방식이 개발되었으나, 여전히 와이어 본딩이 요구되고 이에따른 와이어 본딩 자체의 문제점은 해소되지 않았다. 또한 칩을 보드에 플립칩 형태로 표면 실장하는 방식이 개발되어 있으나, 본드 자체가 설정 패턴을 에칭 등의 방식으로 대량생산 하여야 하기에 환경오염의 문제가 있고, 사용자가 쉽게 패턴을 구현 변경하기 어려운 단점이 있었다.Although a lead-on chip method has been developed for this purpose, wire bonding is still required and the problem of wire bonding itself has not been solved. In addition, a method of surface-mounting chips in the form of flip chips on a board has been developed, but there is a problem of environmental pollution since the bond itself has to mass-produce a set pattern by etching or the like, and it is difficult for a user to easily change the pattern. There was a downside.
본 발명은 상기와 같은 기존의 문제점을 해결코자 하는 것으로, 칩의 본드패드부분과 절연 필름의 펀치부가 정확히 일치하도록 절연 필름상에 칩을 부착하고, 이러한 상태에서 필름에 도전체로 프린팅 방식의 패턴을 구현시킴을 특징으로 하여, 칩 설계 및 리드 구성 설계등에 구애를 받지 않고 리드를 변경하여 설계가능토록 제조 가능한 패키지를 제공하고자 하는 것이다.The present invention is to solve the above-described problems, the chip is attached to the insulating film so that the bond pad portion of the chip and the punch portion of the insulating film exactly, and in this state the pattern of the printing method with a conductor on the film Characterized by the implementation, it is to provide a package that can be manufactured to be able to design by changing the lead regardless of chip design and lead configuration design.
즉, 본 발명은 칩의 본드패드부분과 제1절연필름의 펀치부가 정확히 일치하도록 절연 필름상에 칩을 부착하고, 이 상태에서 원하는 패턴을 형성하기 위한 수단으로 필름에 골드(GOLD) 등의 도전체로 프린팅하며, 이때 프린팅에 의해 골드가 필름의 펀치부에 인입되어 칩의 본드 패드와 적정하중에 의한 접착이 이루어지도록 한 후, 일정시간동안 가공한 상태에서 프린팅한 상면에 다시 제2절연필름을 제1절연필름의 컨텍트부가 덮히지 않토록 열 압착에 의해 부착하고, 이 상태에서 칩의 하면에 코팅수지로 일정부위를 도포하며, 코팅이 완료되면 사용자가 요구하는 형상으로 필름을 커팅함으로서 완성된 패키지를 얻을 수 있다. 이때 골드 프린팅은 사용자가 원하는 패턴의 형태를 미리 설계하고, 이를 실크스크린과 같은 방법으로 프린팅 함이 바람직하다.That is, according to the present invention, the chip is attached to the insulating film so that the bond pad portion of the chip and the punch portion of the first insulating film are exactly matched, and in this state, a conductive film such as gold is applied to the film as a means for forming a desired pattern. In this case, gold is introduced into the punch portion of the film by printing to bond the chip to the bond pad by the proper load, and then the second insulating film is placed on the upper surface of the printed surface after processing for a predetermined time. The contact portion of the first insulating film is attached by thermocompression so as not to be covered. In this state, a predetermined portion is applied to the lower surface of the chip by coating resin, and when the coating is completed, the film is cut into a shape required by the user. You can get a package. At this time, gold printing is preferably designed in advance the shape of the pattern desired by the user, it is preferable to print in the same way as silk screen.
이하 도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the drawings will be described in detail.
제1도는 본 발명 필름 온 칩(FILM ON CHIP) 패키지의 일 실시예를 보여주는 구성 단면도이다.1 is a configuration cross-sectional view showing an embodiment of the film on chip package according to the present invention.
즉, 상기와 같은 본 발명의 실시예에서는, 본드패드(7)를 포함하고 있는 칩(1)의 상면에, 본드패드(7)들과 펀치부(7-1)가 정확히 일치하도록 펀치부(7-1)를 포함하여 이루어진 제1절연필름(2)이 접착되고, 접착된 제1절연필름(2)의 위에 골드(3)가 원하는 패턴을 형성토록 프린팅되며, 골드(3)가 프린팅 되어 있는 제1절연필름(2)의 컨텍트부(8)가 덮히지 않을 정도로 제1절연필름(2)의 위에 제2절연필름(4)이 열압착되어 있으며, 상기 제1절연필름(2)의 하면 일부(컨텍트부(8)를 제외한 부분)와 칩(1)의 상면을 제외한 부분이 코팅 수지(5)로 코팅되어 있다.That is, in the embodiment of the present invention as described above, the punch portion (1) so that the bond pads 7 and the punch portion 7-1 exactly coincide with the upper surface of the chip 1 including the bond pad 7. 7-1) is bonded to the first insulating film 2 is bonded, the gold 3 is printed on the bonded first insulating film 2 to form a desired pattern, the gold (3) is printed The second insulating film 4 is thermally compressed on the first insulating film 2 such that the contact portion 8 of the first insulating film 2 is not covered. Part of the lower surface (part except the contact part 8) and the part except the upper surface of the chip 1 are coated with the coating resin 5.
이때 칩의 본드패드와 골드의 접착은 골드를 프린팅때의 적정하중에 의해 이루어진다. 이것을 평면도로 도시하면 제2도와 같이 도시할 수 있다(도면의 생략은 제3(f)도와 동일하므로 생략한다).At this time, bonding of the bond pad of the chip and the gold is performed by the proper load when printing the gold. If this is shown in a plan view, it can be shown as in FIG. 2 (omitting of the drawing is omitted since it is the same as in FIG. 3 (f)).
이것을 제조할 때에는 제3도에서와 같은 과정을 통해 이루어진다.When manufacturing this is done through the same process as in FIG.
제3도는 본 발명 필름 온 칩(FILM ON CHIP) 패키지의 공정을 보여주는 도면으로, (a)도는 칩과 절연 필름을 접착하는 과정을 나타내는 실시도, (b)도는 칩과 절연 필름을 접착 후 골드 프린팅을 실시한 상태의 사시도, (c)도는 (b)도의 단면도, (d)도는 골드 프린팅 완료 후 절연 필름을 접착한 상태의 단면도, (e)도는 칩 하면에 도포를 실시한 상태의 단면도, (f)도는 필름을 커팅하여 완성된 필름 온 칩(FILM ON CHIP) 패키지를 보여주기 위한 도면이다.Figure 3 is a view showing the process of the film on chip (FILM ON CHIP) package of the present invention, (a) is an embodiment showing a process of bonding the chip and the insulating film, (b) is a gold after bonding the chip and the insulating film (C) is a sectional view of the printing state, (c) is a sectional view of (b), (d) is a sectional view of a state in which an insulating film is bonded after completion of gold printing, (e) is a sectional view of a coating applied to the lower surface of the chip, (f ) Is a view showing a film on chip (FILM ON CHIP) package completed by cutting the film.
즉, (a)도와 같이 칩(1) 상면의 본드패드(7)와 동일한 위치에 동일한 크기의 형태로 펀치(7-1)되어 있는 제1절연필름(2)을 칩(1) 위에 정확히 정렬하여 제1절연필름(2)과 칩(1)을 접착/부착한다. 이때 칩(1)의 본드 패드부(7)는 제1절연필름(2)의 펀치부(7-1)와 정확히 일치하도록 한다.That is, as shown in (a), the first insulating film 2 having the punches 7-1 in the same size at the same position as the bond pad 7 on the upper surface of the chip 1 is exactly aligned on the chip 1. Thus, the first insulating film 2 and the chip 1 are adhered / attached. At this time, the bond pad portion 7 of the chip 1 is made to exactly match the punch portion 7-1 of the first insulating film 2.
(a)도에 의해 제1절연필름(2)과 칩(1)을 접착상태에서, (b)도와 같이 제1절연필름(2)의 상면에 골드(또는 알루미늄)를 이용하여 요구되어 지는 패턴을 프린팅한다. 이때 골드를 프린팅 하는 방법은 실크스크린 또는 등사기의 원리를 이용하는 것이 바람직하며, 형성되는 패턴이 지나는 경로는 절연필름(2)의 상면으로 지나게 되므로 최소의 경로를 형성할 수 있다.The pattern required by using gold (or aluminum) on the upper surface of the first insulating film 2 as shown in (b) in the state in which the first insulating film 2 and the chip 1 are bonded to each other according to (a). Print At this time, the method of printing gold is preferably using the principle of silk screen or a copy machine, and the path through which the formed pattern passes through the upper surface of the insulating film 2 can form a minimum path.
이때, 칩(1)상의 본드패드(7)와 패턴은 (c)도와 같이 절연필름(2)의 펀치부(7-1)에 골드가 인입하여 접속되는데, 본드패드(7)에 골드의 접착은 프린팅시 적정 하중에 의하여 행해진다.At this time, the bond pad 7 and the pattern on the chip 1 are connected to the punch portion 7-1 of the insulating film 2 by drawing gold as shown in (c). Is carried out by an appropriate load during printing.
상기와 같이 골드에 의한 패턴 프린팅 완료 후, 일정시간 가공한 상태의 자재(c도의 상태)에 (d)도와 같이 제2절연필름(4)을 덮어 열압착에 의해 부착시킴으로써 골드 프린팅 된 패턴을 보호토록 한다. 이때, 제1절연필름의 컨텍트부는 덮지 않도록 한다.After the pattern printing by gold is completed as described above, the second printed film 4 is covered with the second insulating film 4 as shown in (d) and attached by thermocompression to protect the gold printed pattern as shown in (d). Do it. At this time, the contact portion of the first insulating film is not covered.
그리고, (e)도와 같이 칩(1)의 하면에 코팅수지로 일정부위 코팅을(도포)를 실시한다.Then, as shown in (e), a predetermined portion is coated (coated) with a coating resin on the lower surface of the chip 1.
코팅이 (e)도와 같이 완료된 상태의 자재를 (f)도와 같이 요구되는 형상으로 필름을 절단한다.The film is cut into the required shape as shown in (f) of the material in which the coating is completed as shown in (e).
상기 제2도의 (a)에서 (f)도의 공정을 거쳐 필름 온 칩(FILM ON CHIP;FOC)이 완성된다.A film on chip (FOC) is completed through the process of FIGS. 2 (a) to 2 (f).
상술한 바와 같이 본 발명은 반도체 칩의 패턴을 형성함에 있어서, 골드 또는 알루미늄등을 이용하여 프린팅함으로써 원하는 형상의 패턴을 용이하게 생성할 수 있을 뿐만 아니라, 프린팅시 절연필름 상면으로 패턴을 형성할 수 있으므로 최소경로로 패턴을 형성할 수 있어서 매우 유용하다.As described above, in forming the pattern of the semiconductor chip, the present invention may not only easily generate a pattern having a desired shape by printing using gold or aluminum, but also form a pattern on the upper surface of the insulating film during printing. Therefore, the pattern can be formed with the minimum path, which is very useful.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950009995A KR0147156B1 (en) | 1995-04-26 | 1995-04-26 | Film on chip package and manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950009995A KR0147156B1 (en) | 1995-04-26 | 1995-04-26 | Film on chip package and manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960039228A KR960039228A (en) | 1996-11-21 |
| KR0147156B1 true KR0147156B1 (en) | 1998-11-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950009995A KR0147156B1 (en) | 1995-04-26 | 1995-04-26 | Film on chip package and manufacturing method |
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| Country | Link |
|---|---|
| KR (1) | KR0147156B1 (en) |
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1995
- 1995-04-26 KR KR1019950009995A patent/KR0147156B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR960039228A (en) | 1996-11-21 |
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