KR0146198B1 - Synchronous Compact Disc Playback Speed Switching Circuit of Block Synchronization Signal - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compact disc reproducing speed switching circuit synchronized with a block synchronizing signal, which receives a speed switching command signal, a command latch clock signal, and a system reset signal (SYSTEM RESET) from a microcomputer and decodes the input signal. Command decoder 10 for generating and outputting a constant speed, double speed or quadruple speed designation signal, a speed designation signal (constant speed, double speed, quadruple speed) output from the command decoder 10, and a system reset signal (SYSTEM RESET) And a block sync synchronizing circuit 20 which receives the block synchronizing signal BLOCK SYNC of the compact disc as an input and outputs the input speed specifying signal in synchronization with the block synchronizing signal BLOCK SYNC, and the reproduction speed of the compact disc. To convert the playback speed to the beginning of the block by adjusting the irregular playback speed switching timing that occurs during block playback. It is directed to a compact disk playback speed switching circuit to be synchronized with the block sync signal to eliminate the processing cost.

Description

Compact disc playback speed switching circuit synchronized with the block sync signal

1 is a block diagram of a compact disc playback speed designation circuit to which the prior art playback speed designation method is applied.

FIG. 2 is a timing diagram showing a change of the speed specifying signal in the reproduction speed specifying circuit shown in FIG.

3 is a block diagram to which a compact disc reproduction speed switching circuit synchronized with the block synchronizing signal according to the embodiment of the present invention is applied;

4 is a detailed circuit diagram of a block sync synchronization circuit in the reproduction speed switching circuit shown in FIG.

FIG. 5 is a timing diagram showing a change of the speed specifying signal in the reproduction speed switching circuit shown in FIG.

The present invention relates to a compact disc playback speed switching circuit synchronized with a block synchronizing signal. More specifically, in converting a playback speed of a compact disc, an irregular playback speed switching timing that occurs during block playback is matched to a block playback start time. The present invention relates to a compact disc reproducing speed switching circuit synchronized with a block synchronizing signal which eliminates processing loss occurring during reproducing speed switching.

Hereinafter, a conventional compact disc reproduction speed specifying circuit will be described with reference to the accompanying drawings.

1 is a block diagram of a compact disc playback speed designation circuit to which the prior art playback speed designation method is applied.

FIG. 2 is a timing diagram showing a change in the speed specifying signal in the reproduction speed specifying circuit shown in FIG.

As shown in FIG. 1, the conventional compact disc reproducing speed designating circuit receives a speed switching command signal and a command latch clock signal from a microcomputer as inputs, decodes the input signal, and specifies a constant speed, double speed, or quadruple speed designation. And a command decoder 10 for generating and outputting a signal.

On a conventional compact disc, i.e., any type of disc recorded in a CD format, the position of a track to be read must be controlled by reading the cue data (Q data) called a block. The block sync signal is extracted from the subcodes of the first two frames of the block.

By the way, in the conventional compact disc playback speed designation circuit shown in FIG. 1, if the playback speed is changed from constant speed to double speed or from double speed to constant speed while reading an arbitrary block (corresponding to one sector on a CD-ROM), One block of data that has been read up to then is lost, so there is a problem of rereading the lost block.

In other words, since the microcomputer cannot adjust the switching timing to the block synchronizing signal in relation to the processing with the microcomputer, as shown in the timing diagram of FIG. 2, the timing of the change of the speed designation signal output from the command decoder 10 is a block. Since the code is changed irrespective of the synchronization signal, the cue code, which is the control data in units of blocks read, becomes incomplete, and the block read immediately before the change of the speed designation signal becomes meaningless data.

The loss time generated by this corresponds to 13 msec, and there is a problem that the processing loss remains as much.

Accordingly, an object of the present invention is to solve the conventional problems as described above. In converting a playback speed of a compact disc, the playback speed switching time is adjusted by matching an irregular playback speed switching time that occurs during block playback to a block start instant. SUMMARY OF THE INVENTION An object of the present invention is to provide a compact disc reproducing speed switching circuit synchronized with a block synchronizing signal that eliminates the processing loss that occurs.

The configuration of the present invention for achieving the above object, receives a speed switching command signal, a command latch clock signal and a system reset signal from the microcomputer as an input, and decodes the input signal to give a constant speed, double speed or quadruple speed designation signal. A command decoder for generating and outputting the command decoder; And a block sync synchronizing circuit which receives a speed specifying signal, a system reset signal, and a block synchronizing signal output from the command decoder, and outputs the input speed specifying signal in synchronization with the block synchronizing signal.

The block sync synchronization circuit may be configured to receive a system reset signal as a set or reset input, receive a block synchronization signal as a common clock input, and receive as a respective input a speed specifying signal output from the command decoder. And a synchronizing means for synchronizing and outputting the speed specifying signal in accordance with the input block synchronizing signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention in detail.

3 is a block diagram of a compact disc reproducing speed switching circuit synchronized with a block synchronizing signal according to an embodiment of the present invention, and FIG. 4 is a detailed circuit diagram of a block sync synchronizing circuit in the reproducing speed switching circuit shown in FIG. .

As shown in FIG. 3, the structure of the compact disc reproducing speed switching circuit synchronized with the block synchronizing signal according to the embodiment of the present invention includes a speed switching command signal, a command latch clock signal, and a system reset signal (SYSTEM) from the microcomputer. A command decoder 10 which receives RESET) as an input, decodes the input signal and generates and outputs a constant speed, double speed or quadruple speed designation signal; A speed specifying signal (constant speed, double speed, quadruple speed), a system reset signal (SYSTEM RESET), and a block sync signal (BLOCK SYNC) of a compact disc are output from the command decoder 10 and input. Is composed of a block sync synchronizing circuit 20 which outputs in synchronization with the block synchronizing signal BLOCK SYNC.

The configuration of the block sync synchronization circuit 20 described above is

Receives a system reset signal (SYSTEM RESET) as a set (S) or reset (R) input, specifies the initial playback speed, receives a block sync signal (BLOCK SYNC) as a common clock input (CK), and executes the above command. A flip-flop that receives the speed designation signals (constant speed, double speed, and 4x speeds) output from the decoder 10 to the respective inputs D, and synchronizes the speed designation signals with the input block synchronization signal BLOCK SYNC. It consists of the latches DFF1 to DFF3.

The operation of the compact disc reproducing speed switching circuit synchronized with the block synchronizing signal according to the embodiment of the present invention made as described above is as follows.

3 is a block diagram of a compact disc reproducing speed switching circuit synchronized with a block synchronizing signal according to an embodiment of the present invention, and there may be various equivalent circuits corresponding to the block sync synchronizing circuit 20 depending on the application. If necessary, the instruction decoder 10 itself may be incorporated.

Importantly, as can be seen in the detailed circuit diagram of the block sync synchronization circuit 20 shown in FIG. 4, the block synchronization signal BLOCK SYNC or its equivalent signal is the clock of the flip-flop or latches DFF1 to DFF3. By entering the input CK, the speed switching timing is designed to be performed at the next starting point of the minimum or constant unit of control data such as the block synchronization signal BLOCK SYNC.

FIG. 5 is a timing diagram showing a change of the speed specifying signal in the reproduction speed switching circuit shown in FIG.

As shown in FIG. 5, it can be seen that the change of the signal specifying the reproduction speed occurs at a point coinciding with the block synchronization signal BLOCK SYNC.

Therefore, the effect of the compact disc reproduction speed switching circuit synchronized with the block synchronizing signal according to the embodiment of the present invention operating as described above is that the irregular reproduction speed switching timing occurring during block reproduction in converting the reproduction speed of the compact disc. To match the start of the block, eliminating the processing loss that occurs when switching playback speeds.

Claims (3)

A command decoder 10 that receives a speed switching command signal, a command latch clock signal, and a system reset signal from the microcomputer as an input, decodes the input signal, and generates and outputs a constant speed, double speed, or quadruple speed designation signal. Wow; The speed input signal received from the command decoder 10 (constant speed, double speed, quadruple speed), the system reset signal (SYSTEM RESET) and the block synchronization signal (BLOCK SYNC) or an equivalent signal thereof is inputted and inputted. And a block sync synchronizing circuit (20) for synchronizing and outputting a specified signal in synchronism with a block synchronizing signal (BLOCK SYNC). The block sync synchronization circuit 20 of claim 1, wherein the block sync synchronization circuit 20 receives a system reset signal SYSTEM RESET as a set S or reset R input, respectively, and receives a block synchronization signal BLOCK SYNC from a common clock. It receives the input CK and receives the speed designation signal (constant speed, double speed, quadruple speed) output from the command decoder 10 as described above to the respective inputs D, and the speed corresponds to the input block synchronization signal BLOCK SYNC. A compact disc reproduction speed switching circuit synchronized with a block synchronizing signal, comprising synchronization means (DFF1 to DFF3) for synchronizing and outputting a designated signal. 3. The compact according to claim 2, wherein the synchronization means (DFF1 to DFF3) comprise a flip-flop or a latch having a function of outputting the output Q in accordance with the clock input CK. Disc playback speed switching circuit.