KR0133965B1 - Semiconductor device having MOS transistor and manufacturing method thereof - Google Patents

Abstract

Disclosed are a semiconductor device and a method of manufacturing the same, which can effectively prevent diffusion of impurities between heat treatments for electrical activation of impurities.

In this semiconductor device, a diffusion barrier layer having a depth equal to or greater than the junction depth of the source / drain regions is formed along the entire junction region of the source drain region.

Further, a diffusion barrier layer is formed in the vicinity of the surface of the gate insulating layer side containing the impurity.

Description

Semiconductor device having MOS transistor and manufacturing method thereof

1 is a cross-sectional view showing a semiconductor device including a P-channel MOS transistor according to the first embodiment of the present invention.

FIG. 2 is a sectional view for explaining a first step of the manufacturing process of the semiconductor device of the first embodiment shown in FIG.

3 is a cross-sectional view for illustrating a second step of the manufacturing process of the semiconductor device of the first embodiment shown in FIG.

4 is a cross-sectional view for explaining a third step of the manufacturing process of the semiconductor device of the first embodiment shown in FIG.

FIG. 5 is a sectional view for explaining a fourth step of the manufacturing process of the semiconductor device of the first embodiment shown in FIG.

6 is a cross-sectional view for illustrating a fifth step of the manufacturing process of the semiconductor device of the first embodiment shown in FIG.

FIG. 7 is a sectional view for explaining a sixth step in the manufacturing process of the semiconductor device of the first embodiment shown in FIG.

8 is a cross-sectional view for explaining a seventh step of the manufacturing process of the semiconductor device of the first embodiment shown in FIG.

9 is a cross-sectional view for explaining an eighth step of the manufacturing process of the semiconductor device of the first embodiment shown in FIG.

FIG. 10 is a correlation diagram showing the relationship between the depth immediately after the injection and the nitrogen concentration in the nitrogen injection step shown in FIG. 7. FIG.

FIG. 11 is a correlation diagram showing the relationship between depth and nitrogen concentration after 800 ° C. annealing in the annealing (heat treatment) step shown in FIG. 9.

FIG. 12 is a correlation chart showing the relationship between depth and boron concentration immediately after injection in the boron injection step shown in FIG.

FIG. 13 is a correlation chart showing the relationship between depth and boron concentration after annealing at 800 ° C. in the annealing (heat treatment) step shown in FIG.

14 is a cross-sectional view showing a semiconductor device including a P-channel MOS transistor according to a second embodiment of the present invention.

FIG. 15 is a sectional view for explaining a first step in the manufacturing process of the semiconductor device of Example 2 shown in FIG.

FIG. 16 is a sectional view for explaining a second step of the manufacturing process of the semiconductor device of the second embodiment shown in FIG.

17 is a cross-sectional view for illustrating a third step of the manufacturing process of the semiconductor device of the second embodiment shown in FIG.

18 is a cross-sectional view for illustrating a fourth step of the manufacturing process of the semiconductor device of the second embodiment shown in FIG. 14.

FIG. 19 is a correlation diagram showing the relationship between the depth from the gate electrode surface after annealing, the boron concentration, and the nitrogen concentration in the nitrogen and boron implantation steps shown in FIGS. 16 and 17. FIG.

FIG. 20 is a correlation diagram showing the relationship between the depth from the gate electrode surface, boron concentration, and nitrogen concentration in the annealing (heat treatment) process shown in FIG. 18. FIG.

21 is a cross-sectional view for explaining a first step of the manufacturing process in the semiconductor device of the second embodiment shown in FIG. 14 when the gate electrode is formed of doped polysilicon.

FIG. 22 is a cross-sectional view for explaining a second step of the manufacturing process in the case where the gate electrode is formed of doped polysilicon in the semiconductor device of the second embodiment shown in FIG.

FIG. 23 is a sectional view for explaining a third step of the manufacturing process in the case where the gate electrode is formed of doped polysilicon in the semiconductor device of the second embodiment shown in FIG.

24 is a cross-sectional view showing a semiconductor device including a MOS transistor according to a third embodiment of the present invention.

25 is a cross sectional view for explaining a first step of the manufacturing process for the semiconductor device of the third embodiment shown in FIG.

FIG. 26 is a sectional view for explaining a second step of the manufacturing process of the semiconductor device of the third embodiment shown in FIG.

FIG. 27 is a sectional view for explaining a third step of the manufacturing process of the semiconductor device of the third embodiment shown in FIG.

FIG. 28 is a sectional view for explaining a fourth step of the manufacturing process of the semiconductor device of the third embodiment shown in FIG.

FIG. 29 is a sectional view for explaining a fifth step of the manufacturing process of the semiconductor device of the third embodiment shown in FIG.

FIG. 30 is a sectional view for explaining a sixth step in the manufacturing process of the semiconductor device of Example 3 shown in FIG.

FIG. 31 is a sectional view for explaining a seventh step of the manufacturing process for the semiconductor device of the third embodiment shown in FIG.

32 is a cross sectional view for explaining an eighth step of the manufacturing process of the semiconductor device of the third embodiment shown in FIG.

33 is a cross sectional view for explaining a ninth step of the manufacturing process for the semiconductor device of the third embodiment shown in FIG.

34 is a cross-sectional view for explaining a tenth step in the manufacturing process of the semiconductor device of the third embodiment shown in FIG.

35 is a sectional view of a semiconductor device including a conventional PMOS transistor.

36 is a cross-sectional view illustrating a first step of the manufacturing process of the conventional semiconductor device shown in FIG.

37 is a cross-sectional view illustrating a second step of the manufacturing process of the conventional semiconductor device shown in FIG.

FIG. 38 is a sectional view for explaining a third step of the manufacturing process of the conventional semiconductor device shown in FIG.

FIG. 39 is a sectional view for explaining a fourth step of the manufacturing process of the conventional semiconductor device shown in FIG.

40 is a cross sectional view for explaining a fifth step of the manufacturing process of the conventional semiconductor device shown in FIG.

FIG. 41 is a sectional view for explaining a sixth step of the manufacturing process of the conventional semiconductor device shown in FIG.

42 is a cross-sectional view illustrating a problem of a conventional semiconductor device.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a metal-oxide-semiconductor (MOS) transistor and a method of manufacturing the same.

As one of the conventional semiconductor devices, it is sectional drawing which shows the semiconductor device containing a P-channel MOS transistor.

35 shows a conventional semiconductor device including a conventional P-channel MOS transistor. Referring to FIG. 35, in the conventional semiconductor device, a separation oxide film 102 for device isolation is formed in a predetermined region on the main surface of the n-type silicon substrate 101. FIG.

P-type source / drain regions 106a and 106b are formed on the active region surrounded by the separation oxide film 102 at predetermined intervals to sandwich the channel region 110.

The gate electrode 104 is formed on the channel region 110 via the gate oxide film 103. Sidewall oxide films 105 are formed on both sidewall portions of the gate electrode 104. P-channel MOS transistors are formed by the P-type source / drain regions 106a and 106b, the gate oxide film 103, and the gate electrode 104.

The gate electrode 104 is made of polysilicon containing P-type impurities such as boron (B), for example, and has a thickness of about 2000 GPa. 36 to 41 are cross-sectional views for explaining the manufacturing method of the conventional semiconductor device shown in FIG.

35 to 41, a manufacturing process of a conventional semiconductor device will be described next.

First, as shown in FIG. 36, the isolation oxide film 102 is formed in a predetermined region on the main surface of the n-type silicon substrate 101 by using the LOCOS (Local Oxidation of Silicon) method. After forming a silicon oxide film (not shown) and a non-doped polysilicon film (not shown) having a thickness of about 2000 GPa on the entire surface, the gate oxide film 103 made of silicon oxide film is patterned for patterning. A gate electrode 104 made of non-doped polysilicon is formed.

Next, as shown in FIG. 37, the resist 111 is formed using photolithography so as to cover an area other than the gate electrode 104. As shown in FIG. In order to activate the impurity (boron) ion-implanted into the gate electrode 104 by using the resist 111 as a mask, heat treatment is performed at 800 ° C to 1000 ° C for about 30 minutes.

Next, as shown in FIG. 39, a silicon oxide film (not shown) is formed on the entire surface, and then anisotropic etching is performed to form sidewall oxide films 105 on both side barrier portions of the gate electrode 104. Next, as shown in FIG. 40, a resist 112 is formed on the gate electrode 104 using a photolithography technique.

Thereafter, as shown in FIG. 41, P-type impurities such as boron, for example, boron or the like are implanted into the silicon substrate 101 using the resist 112, the sidewall oxide film 105, and the separation oxide film 102 as masks. .

As a result, P-type ion implantation regions 107a and 107b are formed. Thereafter, the resist 112 is removed. Then, by performing heat treatment at 800 ° C. for about 30 minutes, the boron introduced into the ion implantation regions 107a and 107b is electrically activated.

As a result, impurity diffusion regions (source / drain regions) 106a and 106b are formed as shown in FIG. In this way, a semiconductor device having conventional P-channel MOS transistors was formed.

In the above-described conventional semiconductor device, there is a disadvantage that redistribution of impurities occurs by heat treatment when activating the impurities introduced into the P-type impurity implantation regions 107a and 107b shown in FIG. That is, the impurities introduced into the P-type impurity implantation regions 107a and 107b by the heat treatment are diffused in all directions inside the silicon substrate 101.

As a result, P-type impurity diffusion regions (source / drain regions) 106a and 106b (see FIG. 35) that are wider than P-type impurity implantation regions 107a and 107b (see FIG. 41) are formed. . 42 is a cross-sectional view for explaining the problem of the conventional semiconductor device.

Referring to FIG. 42, when the size of the P-type source / drain regions 106a and 106b is increased by diffusion of impurities by heat treatment, the channel length L is shortened.

As a result, for example, a so-called punch in which the depletion layer near one region of the source / drain regions 106a and 106b spreads to the other region, and the current cannot be controlled by the gate voltage. There was a problem that the through phenomenon occurs.

This punch-through phenomenon is particularly remarkable with the miniaturization of the device.

In addition, as another problem, the P-type impurity (boron) in the gate electrode 104 passes through the gate oxide film 103 to the channel region 110 by heat treatment when activating the P-type impurity in the gate electrode 104. There was also a problem of spreading.

When the P-type impurities in the gate electrode 104 diffuse into the channel region 110, there is a problem in that the threshold voltage of the MOS transistor is changed.

One object of the present invention is to effectively prevent punch-through phenomenon in a semiconductor device. Another object of the present invention is to effectively prevent the variation of the threshold voltage caused by diffusion of impurities in the gate electrode into the channel region in the semiconductor device.

Still another object of the present invention is to effectively suppress diffusion of impurities by heat treatment when forming a source / drain region in a method of manufacturing a semiconductor device.

Still another object of the present invention is to effectively prevent diffusion of impurities in the gate electrode into the channel region by heat treatment for activation in the method of manufacturing a semiconductor device.

In a first aspect of the invention, a semiconductor device includes a first conductive semiconductor region having a major surface and a second conductive layer having a predetermined junction depth formed at predetermined intervals so as to sandwich a channel region on the major surface of the semiconductor region. A group consisting of a pair of source / drain regions of a type and a junction region of source / drain regions having a depth equal to or greater than the junction depth of the source / drain regions, and consisting of nitrogen, fluorine, argon, oxygen, and carbon; And a gate electrode formed on the channel region via a gate insulating layer.

In addition, it is preferable that the above-described injection layer has a depth larger than the junction depth of the source / drain regions and covers the source / drain regions.

In this semiconductor device, since an injection layer having a depth equal to or greater than the junction depth of the source / drain regions is formed along the entire region of the junction region of the source / drain regions, impurities are diffused by heat treatment during formation of the source / drain regions. Effectively prevented.

As a result, the channel length is prevented from being shortened by diffusion of impurities as in the prior art, and as a result, the punch-through phenomenon is effectively reduced.

In addition, when the above-described injection layer is formed to have a depth larger than the junction depth of the source / drain regions and to cover the source / drain regions, the diffusion of impurities by heat treatment at the time of forming the source / drain regions is further suppressed.

In another aspect of the present invention, a semiconductor device includes a semiconductor region of a first conductive type having a major surface and a pair of source / types of a second conductive type formed at predetermined intervals so as to sandwich a channel region on the major surface of the semiconductor region. A gate electrode formed on the drain region and its channel region via a gate insulating layer is provided.

The gate electrode contains impurities, and an injection layer including one selected from the group consisting of nitrogen, fluorine, argon, oxygen, and carbon is formed near the surface of the gate insulating layer side of the gate electrode.

In this semiconductor device, since an injection layer is formed near the surface of the gate insulating layer side of the gate electrode containing impurities, impurities in the gate electrode pass through the gate insulating layer to the channel region by heat treatment when activating the impurities in the gate electrode. Diffusion is effectively prevented.

This prevents fluctuations in threshold voltage due to diffusion of impurities into the channel region.

Another aspect of the present invention provides a method of manufacturing a semiconductor device, including forming a gate electrode through a gate insulating layer in a predetermined region on a main surface of a semiconductor region of a first conductivity type, and using the gate electrode as a mask for a semiconductor region. Ion-implanted one selected from the group consisting of nitrogen, fluorine, argon, oxygen, and carbon into the first projection amorphous phase, and the second conductive type in the semiconductor region using the gate electrode as a mask. And a step of forming a pair of impurity regions of the second conductivity type by ion implantation into the second projection ratio smaller than the first projection ratio described above, and then performing a heat treatment.

In this method of manufacturing a semiconductor device, an implantation layer is formed by ion implantation of one selected from the group consisting of nitrogen, fluorine, argon, oxygen, and carbon into the first projection semiconductor into the semiconductor region of the first conductivity type. Since a pair of impurity regions of the first conductivity type are formed by ion implantation into a second projection amorphous having a conductivity smaller than the first projection ratio information, and then a heat treatment is performed, the above-described injection layer is used between the heat treatments. Diffusion of impurities in the impurity region is effectively suppressed.

This prevents the channel length from being shortened as in the prior art, and as a result, the punch-through phenomenon is effectively reduced.

In another aspect of the present invention, a method of manufacturing a semiconductor device includes a process of forming a gate electrode through a gate insulating layer on a predetermined region on a main surface of a semiconductor region of a first conductivity type, and introducing impurities into the gate electrode to introduce a gate electrode. Forming an impurity region having a predetermined depth from the upper surface of the gate electrode, and ion-implanting one selected from the group consisting of nitrogen, fluorine, argon, oxygen, and carbon into the gate electrode so that the above-described impurity regions The process of forming the injection layer which has it, and the process of heat processing after that are provided.

In the method of manufacturing the semiconductor device, an implantation layer having a depth equal to or greater than that of the impurity region is obtained by ion implanting one selected from the group consisting of nitrogen, fluorine, argon and oxygen carbon into a gate electrode including an impurity region having a predetermined depth. Is formed, and then heat treatment is performed, whereby the impurity in the impurity region is prevented from diffusing into the gate insulating layer by the injection layer and invading the channel region. This prevents the variation of the threshold voltage.

Example

EMBODIMENT OF THE INVENTION Hereinafter, the Example of this invention is described based on drawing.

1 is a cross-sectional view showing a semiconductor device having a P-channel transistor according to the first embodiment of the present invention.

Referring to FIG. 1, in the semiconductor device according to the first embodiment, a separation oxide film 1 is formed in a predetermined region on the main surface of the n-type silicon substrate 1.

Source / drain regions 6a and 6b are formed on the main surface of the silicon substrate 1 surrounded by the separation oxide film 2 at predetermined intervals so as to sandwich the channel region 10. On the channel region 10, a gate electrode 4 made of a polysilicon film containing impurities is formed via a gate oxide film 3 having a thickness of 500 to 2000 GPa.

Side wall oxide films 5 are formed on both side wall portions of the gate electrode 4.

In this first embodiment, the nitrogen injection regions 7a and 7b are formed to cover the junction regions of the source / drain regions 6a and 6b, respectively.

By the nitrogen injection regions 7a and 7b, impurities in the heat treatment process at the time of forming the source / drain regions 6a and 6b are perpendicular to the main surface of the silicon substrate 1 and in the horizontal direction. The diffusion can be effectively prevented.

This eliminates the disadvantage that the channel length is shortened by diffusion of impurities in the horizontal direction as in the conventional semiconductor device shown in FIG.

As a result, the punch through phenomenon can be effectively prevented.

2 to 8 are cross-sectional views for explaining the manufacturing process of the semiconductor device of the first embodiment shown in FIG.

With reference to FIGS. 1-8, the manufacturing process of the semiconductor device of a 1st Example is demonstrated.

First, as shown in FIG. 2, the isolation oxide film 2 is formed in a predetermined region on the main surface of the n-type silicon substrate 1 by using the LOCOS method.

By forming and patterning a silicon oxide film (not shown) and a non-doped polysilicon film (not shown) having a thickness of about 2000 GPa on the entire surface, the gate oxide film 3 and the non-doped polysilicon film made of silicon oxide film are patterned. A gate electrode 4 is formed.

Next, as shown in FIG. 3, the resist 11 is formed using photolithography so as to cover an area other than the gate electrode 4.

Boron B is ion implanted into the gate electrode 4 using the resist 11 as a mask.

Thereafter, the resist 11 is removed.

As shown in FIG. 4, an impurity (boron) injected into the gate electrode is activated by performing heat treatment for 30 minutes under a temperature condition of about 800 to 900 占 폚.

Next, after forming a silicon oxide film (not shown) on the entire surface, the sidewall oxide film 5 is formed on both side wall portions of the gate electrode 4 as shown in FIG. 5 by anisotropic etching. Subsequently, as shown in FIG. 6, a resist 12 is formed on the gate electrode 4 using a photolithography technique.

Thereafter, as shown in FIG. 7, nitrogen is implanted into the silicon substrate 1 using the resist 12, the sidewall oxide film 5 and the separation oxide film 2 as masks.

The conditions for the ion implantation were set to a value (concentration of 1E15 to 1E16 particles / cm 2) and a value larger than the projection ratio (0.032 μm at 10 KeV = 0.032 μm) of the boron implanted in the subsequent step (0.065 μm at 30 KeV).

By performing ion implantation under the above implantation conditions, nitrogen implantation regions 7a and 7b are formed. In addition, ion implantation for formation of the nitrogen implantation regions 7a and 7b may be performed before the sidewall oxide film 5 is formed.

Next, as shown in FIG. 8, boron is implanted into the silicon substrate 1 using the resist 12, the sidewall oxide film 5 and the separation oxide film 2 as masks.

This ion implantation is carried out under the condition that the implantation energy is 10 KeV, a projection ratio of 0.032 µm, and an impurity concentration is 5E15 particles / cm 2.

As a result, impurity implantation regions 8a and 8b are formed.

These impurity implantation regions 8a and 8b are surrounded by nitrogen implantation regions 7a and 7b.

The resist is then removed.

Next, as shown in FIG. 9, heat treatment is carried out for 30 minutes in a nitrogen atmosphere under a temperature condition of (800 ° C.) by an electric furnace annealing for electrically activating boron in the impurity injection regions 8a and 8b. Is done.

By this heat treatment, boron in the impurity implantation regions 8a and 8b diffuses toward the inside of the silicon substrate 1, while nitrogen in the nitrogen implantation region 7a diffuses toward the surface of the silicon substrate 1. .

By diffusion of this nitrogen to the silicon substrate 1 surface, the diffusion of boron into the silicon substrate 1 is suppressed. That is, the diffusion of boron into the silicon substrate 1 can be suppressed by mutually diffusing with boron of nitrogen. As a result, the diffusion of boron in the direction along the main surface of the silicon substrate 1 is also suppressed, so that the channel length can be effectively prevented as in the prior art. As a result, punch-through phenomenon can be reduced.

FIG. 10 is a correlation chart showing the relationship between the nitrogen concentration immediately after the nitrogen ion implantation and the depth from the substrate surface. FIG. 11 is a correlation chart showing the relationship between the nitrogen concentration after 800 ° C. annealing and the depth from the substrate surface.

FIG. 12 is a correlation chart showing the relationship between the boron concentration immediately after implantation of boron ions and the depth from the substrate surface, and FIG. 13 is the relationship between the boron concentration after 800 ° C. annealing and the depth from the substrate surface. Is a correlation diagram shown in comparison with the conventional.

First, referring to FIGS. 10 and 11, in the case where the nitrogen injection amounts are set to 1E15 / cm 2 and 1E16 / cm 2, after 800 ° C. annealing, the portion where the nitrogen concentration is lower than immediately after injection is diffused from the substrate surface. It can be seen that the depth is shallow.

In other words, it can be seen that nitrogen is diffused toward the substrate surface by annealing.

As for the boron concentration, as shown in Figs. 12 and 13, when there is no conventional nitrogen injection, it can be seen that the diffusion depth becomes extremely deep after annealing, as compared with immediately after the injection.

On the other hand, when nitrogen injection is performed, the distribution of boron concentration hardly changes immediately after the injection and after the annealing, and it is understood that the redistribution is hardly seen.

In other words, it can be seen that diffusion of boron into the substrate by heat treatment can be suppressed by performing nitrogen injection.

However, as is clear from FIGS. 10 and 12, it can be seen that it is necessary to inject nitrogen more deeply than boron in the ion implantation step.

As described above, when the deep nitrogen injection regions 7a and 7b are formed at the same time and the impurity implantation regions 8a and 8b (see Fig. 8) having a shallower depth are formed, heat treatment is performed. The source / drain regions 6a and 6b having less diffusion of substrates from impurities can be formed.

14 is a cross-sectional view of a semiconductor device including a P-channel MOS transistor according to a second embodiment of the present invention.

Referring to FIG. 14, in this second embodiment, nitrogen injection regions 7a and 7b are formed so as to cover the source / drain regions 6a and 6b as in the first embodiment described above. . Further, in this second embodiment, unlike the first embodiment, the nitrogen injection region 15 is formed on the surface of the gate oxide film 3 side of the gate electrode 14.

The boron injection region 16 is formed on the nitrogen injection region 15 in the gate electrode 14. By the nitrogen injection region 15, it is possible to effectively prevent the boron from diffusing into the channel region 10 through the gate oxide film 3 during the heat treatment to activate the boron in the boron injection region 16.

As a result, fluctuations in the threshold voltage caused by diffusion of impurities into the channel region 10 can be effectively prevented. 15 to 18 are cross-sectional views for explaining the manufacturing process of the gate electrode portion of the semiconductor device of the second embodiment shown in FIG. 15 to 18, a manufacturing process of the semiconductor device of the second embodiment will next be described.

First, as shown in FIG. 15, the isolation oxide film 2 is formed in a predetermined region on the main surface of the silicon substrate 1 by using the LOCOS method.

A gate oxide film made of silicon oxide film is formed by forming and patterning a silicon oxide film (not shown) having a thickness of about 500 to 2000 GPa and a non-doped polysilicon film (not shown) having a thickness of about 2000 GPa so as to cover the entire surface. (3) and a gate electrode 14 made of a non-doped polysilicon film.

The resist 17 is formed using photolithography so as to cover portions other than the gate electrode 14.

Next, as shown in FIG. 16, nitrogen is implanted into the gate electrode 14 using the resist 17 as a mask. This nitrogen ion implantation is performed at an implantation energy (e.g., 90 KeV) in which nitrogen ions are implanted to a surface vicinity of the gate oxide film 3 side of the gate electrode 14 at a concentration of 1E15 to 1E16 atoms / cm < 2 >. As a result, the ion implantation region 15 is formed.

Next, as shown in FIG. 17, the injection energy which makes the depth of the boron to the gate electrode 1 at a concentration of 5E15 pieces / cm < 2 > For example, ion implantation at 30 KeV). As a result, the boron injection region 16 is formed. Thereafter, the resist 17 is removed.

In order to electrically activate the boron in the boron injection region 16, heat treatment is performed by annealing an electric furnace at 800 ° C to 1000 ° C.

By this heat treatment, the boron in the boron injection region 16 diffuses toward the gate oxide film 3 while the nitrogen in the nitrogen injection region 15 diffuses upward.

By the mutual diffusion of boron and nitrogen, diffusion of boron in the direction of the gate oxide film 3 is suppressed as compared with the prior art. Finally, as shown in FIG. 18, the structure is such that the nitrogen injection region 15 is interposed between the boron injection region 16 and the gate oxide film 3.

FIG. 19 is a correlation diagram showing the relationship between the depth from the gate electrode surface immediately after the ion implantation and the boron concentration and the nitrogen concentration. FIG. 20 shows the depth, boron concentration and nitrogen concentration from the gate electrode surface after annealing (after heat treatment). Correlation chart showing the relationship.

Referring to FIGS. 19 and 20, it can be seen that after annealing, a portion of the lower concentration of the boron concentration distribution is slightly moved toward the gate oxide film 3 than immediately after the injection.

On the other hand, it can be seen that after annealing, the portion of the higher concentration of the nitrogen concentration distribution slightly shifts to the side opposite to the gate oxide film 3 as compared with immediately after the injection.

This shows that boron and nitrogen mutually diffuse.

The diffusion of boron in the direction of the gate oxide film 3 is suppressed by the mutual diffusion of boron and nitrogen.

As shown in FIG. 20, it can be seen that after annealing, only nitrogen exists in the vicinity of the gate oxide film 3.

When such a state is displayed in cross section, it becomes a cross-sectional shape as shown in FIG. After forming the gate electrode 14 containing the impurity as described above, the sidewall oxide film shown in FIG. 14 is manufactured using the same manufacturing process as in the first embodiment shown in FIGS. 5), source / drain regions 6a and 6b, and nitrogen injection regions 7a and 7b. In this manner, the semiconductor device of the second embodiment is completed.

21 to 23 are cross-sectional views for explaining a manufacturing process when the gate electrode of the semiconductor device of the second embodiment is formed of a dope polysilicon film.

21 to 23, a manufacturing process in the case of using doped polysilicon as the gate electrode will be described.

First, as shown in FIG. 21, a gate oxide film 3 made of a silicon oxide film and a gate electrode 24 made of doped polysilicon are formed in a predetermined region on the main surface of the silicon substrate 1.

The resist 26 is formed to cover portions other than the gate electrode 24.

Next, as shown in FIG. 22, nitrogen is implanted into the gate electrode 24 using the resist 26 as a mask.

The injection condition of the dinitrogen is performed at an implantation energy (90 KeV) in which nitrogen is injected to the vicinity of the gate oxide film 3, for example, at an impurity concentration of 1E15 to 1E16 atoms / cm 2.

As a result, the nitrogen injection region 25 is formed. Thereafter, the resist 26 is removed.

Then, the doped impurities are activated in the gate electrode 24, and heat treatment is performed by annealing an electric furnace under a temperature condition of 800 to 1000 占 폚.

By this heat treatment, impurities in the gate electrode 24 diffuse in the direction of the gate oxide film 3 while nitrogen in the nitrogen injection region 25 diffuses in the direction opposite to the gate oxide film 3.

As a result, impurities and nitrogen diffuse to each other, and diffusion of impurities into the gate oxide film 3 is suppressed. As a result, impurities in the gate electrode 24 are prevented from diffusing through the gate oxide film 3 to the channel region. As a result, even when a doped polysilicon film is used as the gate electrode 24, it is possible to prevent the variation of the threshold voltage caused by diffusion of impurities into the channel region.

After the heat treatment described above, as shown in FIG. 23, a small amount of impurities are contained in the nitrogen injection region 25. As shown in FIG.

24 is a cross-sectional view showing a semiconductor device including a CMOS transistor according to a third embodiment of the present invention.

Referring to FIG. 24, in this third embodiment, the separation oxide film 32 is formed in a predetermined region on the main surface of the silicon substrate 31. As shown in FIG. The N well 33 and the P well 34 are formed adjacent to each other on the main surface of the silicon substrate 31.

Source / drain regions 40a and 40b are formed on the main surface of the N well 33 at predetermined intervals so as to sandwich the channel region 51. Nitrogen injection regions 41a and 41b are formed to cover the source / drain regions 40a and 40b, respectively. The gate electrode 36a is formed on the channel region 51 through the gate oxide film 35a.

A nitrogen injection region 38a is formed on the gate oxide film 35a side in the gate electrode 36a.

The boron injection region 37a is formed on the nitrogen injection region 38a.

A sidewall oxide film 39a is formed on the sidewall portion of the gate electrode 36a.

On the main surface of the P well 34, n + source / drain regions 43a and 43b are formed at predetermined intervals so as to sandwich the channel region 52. As shown in FIG.

On the channel region 52 side of the n + source / drain regions 43a and 43b, n− source / drain regions 42a and 43b are formed, respectively.

The gate electrode 36b is formed on the channel region 52 through the gate oxide film 35b.

A nitrogen injection region 38b is formed on the gate oxide film 35b side of the gate electrode 36b, and a boron injection region 37b is formed on the nitrogen injection region 38b.

Sidewall oxide films 39b are formed on both sidewall portions of the gate electrode 36b. The P-channel MOS transistor is formed by the source / drain regions 40a and 40b and the gate electrode 36a in the N well 33.

N + source / drain regions 43a and 43b in the P well 34, n- source / drain regions 42a and 42b, and the gate electrode 36 to form a lightly doped drain (LDD) structure. An N-channel MOS transistor is formed.

In this third embodiment, the nitrogen injection regions 41a and 41b are formed to cover the source / drain regions 40a and 40b constituting the P-channel MOS transistor, respectively. The impurities in the source / drain regions 40a and 40b are transferred to the N well 33 by heat treatment at the time of forming the source / drain regions 40a and 40b by the nitrogen injection regions 41a and 41b. Diffusion toward the inside of the diffusion of impurities in the drain region 40b to the channel region 51 side is also suppressed, so that the channel length can be prevented from being shortened.

As a result, punch-through phenomenon can be effectively prevented.

This effect is particularly effective when the device is miniaturized.

In addition, the nitrogen injection region covering the n + source / drain regions 43a and 43b constituting the N-channel MOS transistor is not provided because n-type impurities are less converted by heat treatment than P-type impurities.

These are for example IEEE TRANSACTION ON ELECTRON DEVICES. VoL. 35. 5, 1988 pp. 659-668.

In this third embodiment, nitrogen is injected into regions of the gate oxide films 35a and 35b of the gate electrode 36a constituting the P-channel MOS transistor and the gate electrode 36b constituting the N-channel MOS transistor, respectively. The areas 38a and 38b are formed.

Boron injection regions 37a and 37b are formed on the nitrogen injection regions 38a and 38b, respectively.

By the nitrogen injection regions 38a and 38b, in the heat treatment for activating boron in the boron injection regions 37a and 37b, the boron passes through the gate oxide films 35a and 36b to the channel region 51. And diffusion in 52 can be effectively prevented.

As a result, fluctuations in the threshold voltage due to boron diffusion into the channel regions 51 and 52 can be prevented.

As a result, deterioration in characteristics of the CMOS transistor can be effectively prevented.

25 to 34 are cross-sectional views for explaining the manufacturing process of the semiconductor device of the third embodiment shown in FIG.

24 to 34, a manufacturing process of the semiconductor device of the third embodiment will be described.

First, as shown in FIG. 25, the N well 33 and the P well 34 are formed adjacent to the main surface of the silicon substrate 31. As shown in FIG.

The isolation oxide film 32 is formed using a predetermined region LOCOS range on the main surface of the silicon substrate 31.

Next, as shown in FIG. 26, a gate oxide film made of a silicon oxide film is formed by forming and patterning a silicon oxide film (not shown) and a non-doped polysilicon film (not shown) having a thickness of about 2000 microseconds on the entire surface. 35a and 35b and gate electrodes 36a and 36b made of a non-doped polysilicon film are formed.

Next, as shown in FIG. 27, the resist 44 is formed using photolithography so as to cover portions other than the gate electrodes 36a and 36b.

Nitrogen is implanted into the gate electrodes 36a and 36b using the resist 44 as a mask. The nitrogen implantation conditions are performed at an implantation energy (e.g., 90 KeV) so that nitrogen ions are implanted to the vicinity of the gate oxide films 35a and 35b at a concentration of 1E15 to 1E16 atoms / cm < 2 >. As a result, the nitrogen injection regions 38a and 38b are formed.

Next, as shown in FIG. 28, boron is implanted into the gate electrodes 36a and 36b using the resist 44 as a mask.

The boron implantation conditions are performed at an implantation energy (e.g., 30 KeV) so that the concentration of 5E16 / cm2 impurity is shallower than that of the nitrogen injection regions 38a and 38b.

As a result, the boron injection regions 37a and 37b are formed. Thereafter, the resist 44 is removed.

Then, heat treatment such as annealing in an electric furnace is performed under a temperature condition of 800 to 1000 ° C.

By this heat treatment, the boron in the boron injection regions 37a and 37b diffuses toward the gate oxide films 35a and 35b, while the nitrogen in the nitrogen injection regions 38a and 38b causes the gate oxide films 35a, It spreads toward the opposite direction to 35b.

As a result, boron and nitrogen diffuse together, whereby diffusion of boron in the directions of the gate oxide films 35a and 35b is suppressed. As a result, it is effectively prevented that the boron by the heat treatment for activating the boron passes through the gate oxide films 35a and 35b and diffuses into the channel region. As a result, the variation of the threshold voltage can be prevented.

By the mutual diffusion of boron and nitrogen as described above, nitrogen injection regions 38a, 38b and boron injection regions 37a, 37b are finally formed as shown in FIG.

Next, as shown in FIG. 30, the resist 45 is formed using photolithography so as to cover the N well 33, the gate electrodes 36a, and 36b.

Phosphorus (P) is ion-implanted into the P well 34 using the resist 45 as a mask.

As a result, low concentration impurity n-source / drain regions 42a and 42b are formed. Thereafter, the resist 45 is removed.

Next, as shown in FIG. 31, after forming a silicon oxide film (not shown) on the whole surface, and performing anisotropic etching, the sidewall oxide films 39a and 39b are formed on the sidewall portions of the gate electrodes 36a and 36b. ).

Next, as shown in FIG. 32, the resist 46 is formed using photolithography so as to cover the N well 33, the gate electrodes 36a, and 36b.

Arsenic (As) is implanted into the P well 34 as a high concentration impurity using the resist 46 as a mask. As a result, n + source / drain regions 43a and 43b are formed. Thereafter, the resist 46 is removed.

Subsequently, as shown in FIG. 33, the resist 47 is formed using photolithography so as to cover the P wells 34 and the gate electrodes 36a and 36b.

Using the resist 47 and the sidewall oxide film 39a as a mask, nitrogen is implanted into the N well 33 at a concentration of 1E15 to 1E16 atoms / cm 2.

The injection energy is set to a value (0.065 μm at 30 KeV) larger than the projection ratio (0.032 μm at 10 KeV) of boron injected in the subsequent step.

In this way, nitrogen implantation regions 41a and 41b are formed by ion implantation of nitrogen.

Next, as shown in FIG. 34, boron is ion-implanted into the N well 33 using the resist 47 and the sidewall oxide film 39a as a mask.

This boron ion implantation is performed at an implantation energy of 0.032 μm at an impurity concentration of 5E15 particles / cm 2 and 10 KeV. As a result, boron injection regions 40a and 40b that are shallower than the nitrogen injection regions 41a and 41b are formed. In other words, the boron injection regions 40a and 40b are surrounded by nitrogen injection regions 41a and 41b, respectively. Thereafter, the resist 47 is removed.

In order to electrically activate the boron, heat treatment is performed for 30 minutes in an atmosphere of nitrogen under a temperature condition of 800 ° C. by annealing with an electric furnace. By this heat treatment, the boron in the boron injection regions 40a and 40b diffuses toward the inside of the N well 33 while the nitrogen in the nitrogen injection regions 41a and 41b is the surface of the N well 33. Spread out towards you.

By such diffusion of boron and nitrogen, diffusion of boron into the N well 33 is suppressed. As a result, the diffusion of the boron injection regions 40a and 40b in the direction of the channel region 51 is also suppressed.

This can effectively prevent the channel length from being shortened, and as a result, the punch-through phenomenon can be reduced.

By mutual diffusion of such boron and nitrogen, source / drain regions 40a and 40b in which diffusion is suppressed as shown in FIG. 24 are finally formed.

In addition, in the manufacturing process of the semiconductor device of the first to third embodiments described above, boron ions are implanted after the implantation of nitrogen ions, but the same effect is obtained even if boron ions are implanted before the implantation of nitrogen ions.

In the manufacturing process of the semiconductor device of the first to third embodiments described above, although annealing is used as the heat treatment method for activating the impurity, the same effect is obtained even when rapid thermal treatment (RPA) is used.

Furthermore, although the boron was used as the P-type impurity contained in the source / drain regions in the semiconductor devices of the first to third embodiments, the present invention is not limited thereto, and for example, BF3, BF2, BF, BCI, etc. Boron compounds may be used.

In addition, although nitrogen was used as the prevention of the diffusion of boron in the first to third embodiments described above, the same effect can be obtained even when fluorine, argon, oxygen, carbon or the like is used. As described above, according to one semiconductor device of the present invention, an injection layer having a depth equal to or greater than the junction depth of the source / drain regions is formed along the entire region of the junction region of the source / drain regions, and the source layer is formed by the injection layer. In the heat treatment for activating the impurities in the / drain region, the impurities can be effectively prevented from diffusing toward the inside of the semiconductor region.

As a result, it is possible to prevent the impurities in the source / drain regions from diffusing to the channel region side by heat treatment, thereby preventing the disadvantage of shortening the channel length.

As a result, punch-through phenomenon can be effectively prevented.

In addition, if the above-described injection layer is formed so that the source / drain regions have a depth larger than the junction depth and cover the source / drain regions, diffusion of impurities in the source / drain regions can be more effectively prevented.

According to another semiconductor device of the present invention, by forming an injection layer in the vicinity of the surface of the gate insulating layer side of the gate electrode containing impurities, impurities in the gate electrode diffuse toward the gate insulating layer side during heat treatment for activating the impurities in the gate electrode. Can be effectively suppressed.

As a result, it is possible to prevent impurities in the gate electrode from diffusing through the gate insulating layer to the channel region. As a result, fluctuations in threshold voltage due to diffusion of impurities into the channel region can be prevented.

According to one method of manufacturing a semiconductor device of the present invention, an implantation layer is formed by ion implantation into a first projection amorphous region selected from nitrogen, fluorine, argon, oxygen, and carbon in a semiconductor region of a first conductivity type. Since the second conductive type is ion-implanted into the same semiconductor region at a second projection ratio smaller than the first projection ratio, a pair of impurity regions of the second conductive type are formed, and the impurity region is surrounded by the injection layer. .

As a result, in the subsequent heat treatment, impurities in the impurity region diffuse toward the inside of the semiconductor region, while nitrogen in the injection layer diffuses toward the surface of the semiconductor region.

As a result, it is possible to suppress diffusion of impurities into the semiconductor region by interdiffusion with impurities and nitrogen. This can prevent the channel length from being shortened.

As a result, the semiconductor device which can prevent the punch-through phenomenon effectively can be manufactured easily.

According to another semiconductor device manufacturing method of the present invention, an impurity region is formed in a gate electrode by introducing an impurity into the gate electrode, and ion implantation of one selected from the group consisting of nitrogen, fluorine, argon, oxygen, and carbon into the gate electrode. Therefore, by forming an injection layer having a depth equal to or greater than that of the impurity region, when annealing thereafter, impurities in the impurity region diffuse toward the gate insulating layer, while nitrogen in the injection layer is opposite to that of the gate insulating layer. Diffusion towards the direction.

As a result, the diffusion of impurities into the gate insulating layer can be suppressed while the impurities and nitrogen diffuse together.

As a result, it is possible to effectively prevent impurities from diffusing through the gate insulating layer to the channel region.

Thereby, the semiconductor device which can prevent the fluctuation of a threshold voltage can be manufactured easily.

Claims (15)

A pair of source / drain regions of the first conductivity type semiconductor region having a major surface, and a second junction type having a predetermined junction depth formed at predetermined intervals so as to sandwich channel regions on the main surface of the semiconductor region; And a depth equal to or greater than the junction depth of the source / drain region, and formed along the entire region of the junction region of the source / drain region and including one selected from the group consisting of nitrogen, fluorine, argon, oxygen, and carbon. A semiconductor device comprising a first injection layer and a gate electrode formed on the channel region via a gate insulating layer. The semiconductor device according to claim 1, wherein the first injection layer has a depth greater than the junction depth of the source / drain regions and covers the source / drain regions. The second injection layer according to claim 1, wherein the gate electrode contains an impurity, and a second injection layer comprising one selected from the group consisting of nitrogen, fluorine, argon, oxygen, and carbon near the surface of the gate insulating impingement side of the gate electrode. The semiconductor device is formed. The semiconductor device according to claim 3, wherein the impurity is a P-type impurity. The semiconductor device according to claim 1, wherein the source / drain region has a P-type conductivity. A semiconductor region of a first conductive type having a major surface, a pair of source / drain regions of a second conductive type formed at predetermined intervals so as to sandwich a channel region on the main surface of the semiconductor region, and on the channel region A gate electrode formed through a gate insulating layer, wherein the gate electrode contains impurities, and one selected from the group consisting of nitrogen, fluorine, argon, oxygen, and carbon near the surface of the gate insulating layer side of the gate electrode; A semiconductor device in which an injection layer is formed. The semiconductor device according to claim 6, wherein the impurity contained in the gate electrode is a P-type impurity. On the first semiconductor region of the first conductive type having a major surface, the second semiconductor region of the second conductive type having a major surface and formed adjacent to the first semiconductor region, and on the major surface of the first semiconductor region. A pair of first source / drain regions of the second conductive type having a predetermined junction depth formed to sandwich the first channel region, and having a depth equal to or greater than a junction depth of the first source / drain region; And a first injection layer comprising one selected from the group consisting of nitrogen, fluorine, argon, oxygen, and carbon formed over the junction region of the first source / drain region, and a first gate on the first channel region. A first gate electrode formed through an insulating layer, a pair of second source / drain regions of a first conductive type formed at predetermined intervals so as to sandwich a second channel region on a main surface of the second semiconductor region; The second channel A semiconductor device having a second gate electrode formed on a region via a second gate insulating layer. 10. The method of claim 8, wherein the first and second gate electrodes both contain impurities of a second conductivity type, and nitrogen is entirely located near the surface of the first and second gate insulating layers of the first and second gate electrodes. And a second injection layer comprising one selected from the group consisting of fluorine, argon, oxygen and carbon. The semiconductor device of claim 8, wherein the first injection layer has a depth greater than a junction depth of the first source / drain region and is formed to cover the first source / drain region. Forming a gate electrode through a gate insulating layer on a predetermined region on the main surface of the semiconductor region of the first conductive type, and using the gate electrode as a mask in the semiconductor region of nitrogen, fluorine, argon, oxygen, and carbon. Ion implantation of one selected from the group into a first projection amorphous, and a second projection amorphous having a second conductivity type impurity smaller than the first projection amorphous in the semiconductor region using the gate electrode as a mask; And a step of forming a pair of impurity regions of the second conductive type by ion implantation, followed by a step of heat treatment thereafter. 12. The method of claim 11, wherein the nitrogen ion is implanted at an implantation energy of 30 KeV, at an impurity concentration of 1E15 to 1E16 particles / cm 2, and the ion implantation of the impurities is at an implantation energy of 10 KeV and at an impurity concentration of 5E15 particles / cm 2. And the heat treatment is performed for 30 minutes in a nitrogen atmosphere under a temperature condition of 800 ° C to 900 ° C. Forming a gate electrode through a gate insulating layer in a predetermined region on a main surface of the semiconductor region of the first conductivity type, introducing impurities into the gate electrode, and a predetermined depth at the upper surface of the gate electrode in the gate electrode; Forming an impurity region having an ion, and implanting one selected from the group consisting of nitrogen, fluorine, argon, oxygen, and carbon into the gate electrode to form an injection layer having a depth equal to or greater than that of the impurity region; Then, the manufacturing method of a semiconductor device provided with the process of heat processing. The method for manufacturing a semiconductor device according to claim 13, further comprising the step of introducing the impurity by ion implantation of the impurity into the gate electrode. The method for manufacturing a semiconductor device according to claim 13, wherein the introduction of the impurity is performed simultaneously with deposition of the gate electrode.