JPH0818047A - Misfet and its manufacturing method - Google Patents

Abstract

PURPOSE:To prevent channel impurity from being spread at an increased speed by performing the ion implantation of a channel impurity through a gate electrode after the activation heat treatment of the source/drain impurity. CONSTITUTION:Ions are implanted to silicon substrate 1 after forming an element isolation insulation film 6, a gate insulation film 4, and a gate electrode 5 to form source/drain regions 3A. Then, by performing heat treatment at a high temperature, point defect flows outside the substrate 1 by diffusion. Then, boron is ion-implanted at approximately 10<12>-10<13>-cm<-2> to form a high- concentration channel region 2A. At this time, the depth of peak of the concentration is set to a value which is equivalent to the lower edge (junction depth) of source/drain regions 3B to suppress short channel effect. Then, heat treatment is performed at a high temperature again, thus activating the boron at the electrically inactive region 2A and hence forming an electrically inactive p-type high-concentration channel region 2B. At this time, no defect exists any more, thus preventing the diffusion of boron at an increased speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and manufacturing method of a semiconductor device, and more particularly to a MISFET and a manufacturing method thereof.

[0002]

2. Description of the Related Art A very general MISFET manufacturing method will be described with reference to FIG. 8 by taking a silicon (Si) / n-channel device as an example. After forming an isolation insulating film for isolating each element on the Si substrate by the LOCOS method or the like, the threshold voltage V _{TH of the} FET is set to a desired value and the short channel effect and punch through are suppressed. P that works
Boron, which is a type impurity, is introduced into the substrate by ion implantation.
Since this step determines the characteristics of the channel of the device, it is referred to as channel ion implantation here. Next, after sequentially forming a gate oxide film and a gate electrode on the substrate surface,
A gate electrode having a desired shape is formed by photolithography and etching. Next, arsenic, which is an n-type impurity, is introduced into the substrate by ion implantation using this gate electrode as a mask to form the source / drain in a self-aligned manner with the gate electrode. After this, it is necessary to perform heat treatment at a high temperature (800 degrees or more in the case of a Si substrate) at least once. As a result, the ion-implanted impurities are contained in the crystal lattice position and become electrically active.

In the above-mentioned manufacturing method, the source / drain implantation introduces a large amount of ions (10 ¹⁵ cm ^-2 or more), so that the crystal structure of the Si substrate is destroyed and a large number of point defects (which are not originally lattice sites). "Interstitial atoms" in which atoms are present and "vacancy" in which atoms at the lattice position are missing are generated. The presence of such point defects causes thermal diffusion of impurity atoms. Particularly, boron (B) and phosphorus (P) are remarkably easily diffused by forming a pair with an interstitial atom (accelerated diffusion).
Therefore, in the above example, in the heat treatment step of activating the impurities in the source / drain, the boron introduced in advance in the substrate forms a pair with the point defect generated at the time of implanting the source / drain, and the boron is introduced for a very short time. It moves largely within the substrate in (1 second or less). This enhanced diffusion is almost uncontrollable even if the temperature and time of the heat treatment are adjusted, which makes it difficult to design the substrate impurity distribution for obtaining desired device characteristics. For example, in a fine MISFET, there is a design requirement to reduce V _TH while suppressing the short channel effect. For this purpose, a short channel effect can be suppressed by arranging a boron peak in a slightly deeper portion of the substrate, while V _TH can be lowered by making the concentration near the substrate surface low. Such a distribution can be realized by adjusting the energy of boron ion implantation and the dose amount. However, such a distribution intended by the device designer is destroyed by the uncontrollable enhanced diffusion during the subsequent heat treatment, and the completed device has a high V _TH and a short channel effect against the intention. Will grow. FIG. 9 shows a characteristic example of the element in which V _TH is increased due to such a phenomenon (channel length dependence of deviation of V _{TH from} the long channel element). Since the enhanced diffusion occurs due to the point defects generated in the source / drain regions,
The shorter the distance between the source and the drain, and the shorter the channel elements in which the influences of both are added, the larger V _TH is (this phenomenon is called the reverse short channel effect). In a practically important short channel device, V _TH becomes higher than a desired value (equal to V _TH at approximately infinite channel length).
Moreover, this increase is a major problem because it reflects the lack of controllability of enhanced diffusion, and fluctuates due to slight process changes. Further, the enhanced diffusion lowers the impurity concentration in the deep portion of the substrate, so that the short channel effect is also deteriorated. Therefore, the short channel effect of the device actually obtained is always worse than the result of the simulation performed without the enhanced diffusion.

On the other hand, a method of reducing the parasitic capacitance between the source / drain and the substrate by modifying the general manufacturing method shown in FIG. 8 is proposed in Japanese Patent Laid-Open No. 4-286364. This method will be described with reference to FIG. The feature of this method is that the channel ion implantation which is usually performed before the gate electrode formation is performed after the gate electrode formation. That is, in the example of FIG. 10, after forming the gate electrode, boron is ion-implanted so as to penetrate the gate electrode and reach the substrate. At this time, in the source / drain region where the gate electrode does not exist, boron is introduced deeper than the region where the channel is formed by the height of the gate electrode. After that, heat treatment for implanting source / drain impurities and activation is performed as usual. By using this method, the channel ion-implanted boron can be made deeper than the source / drain. For this reason, the concentration of the p-type portion of the substrate in contact with the n-type source / drain is lower than that in the case where the channel ion implantation is performed by the usual method. As a result, the depletion layer of the pn junction is widened, the parasitic capacitance generated between the source / drain and the substrate is reduced, and the circuit operation is speeded up.

In the above method, the enhanced diffusion poses the same problem as in the normal manufacturing method, but in addition to that, the threshold voltage V _TH
However, the controllability of is poor. This point will be described below. The ion implantation depth distribution is mountain-shaped, and in the above-mentioned channel implantation, the peak of the mountain-shaped distribution is equal to the depth of the source / drain just under the gate electrode (usually 100 to 300 nm) in order to prevent punch-through.
It is necessary to set so that In the channel ion implantation, the implantation energy is set so that the range is the sum of the depth inside the substrate and the height of the gate electrode. However, the height of the gate electrode (typical value is 100 to 50
It is inevitable that a variation of 10 to 50 nm will occur in the process (0 nm). In particular, the film thickness variation is likely to occur in the phosphorus diffusion to the polysilicon gate and the etchback process for forming the gate sidewall. Therefore, the implantation depth is ±
Uncertainties of 10-50 nm occur. As described above, the ion-implanted impurity distribution is mountain-shaped and has a large concentration gradient in the depth direction on the substrate surface. Therefore, such a variation in the depth causes a variation in the impurity concentration on the surface of the substrate, resulting in variation in V _TH . That is, the shallower the impurity depth, the higher the concentration and the higher V _TH . As an example, boron is implanted so as to penetrate a gate electrode having a thickness of 150 nm and have a peak at 100 nm in the substrate, and V _TH = 0.
When designed to 4V, the gate electrode height shift is 10nm
On the other hand, V _TH fluctuates by about 50 mV. Note that FIG.
Also in the normal manufacturing method shown in (1), it is usual to provide an oxide film (sacrificial oxide film) of 10 to 30 nm on the substrate and to perform channel ion implantation from above in order to prevent substrate contamination and channeling. , Because the oxide film is originally thin,
The absolute value of the variation in the thickness is one digit smaller than that of the gate electrode, which is not a problem.

[0006]

The above-mentioned ordinary MIS
In the FET manufacturing method, there is a problem in that the channel impurities cause accelerated diffusion due to point defects generated during the source / drain implantation, and it is difficult to control the distribution of the channel impurities.

Further, when the channel ion implantation is performed through the gate electrode, there is a problem that the threshold voltage V _{TH of the} element sensitively changes due to the height change of the gate electrode.

[0008]

In order to solve the first problem of enhanced diffusion, channel ion implantation is performed after ion implantation and activation of source / drain impurities. More specifically, after ion-implanting the source / drain in a self-aligned manner with respect to the gate electrode, a heat treatment for activation is performed, and thereafter, channel ion implantation is performed through the gate electrode.

When channel ion implantation is performed through the gate electrode as described above, there is a second problem that the threshold value V _TH varies. The same problem also occurs when channel ion implantation is performed through the gate electrode simply for the purpose of reducing the parasitic capacitance of the source / drain. In order to solve this, the element structure is formed so that the relatively high concentration impurity region formed by the channel ion implantation has a substantially uniform impurity distribution in the depth direction. Therefore, at least one of the channel ion implantation processes through the gate electrode
In the third step, the implantation is performed so that the depth peak under the gate is located on the substrate surface.

[0010]

[Function] Most of the crystal defects caused by the source / drain ion implantation are eliminated by the subsequent heat treatment for activation. Therefore, if the channel impurities are subsequently introduced, their diffusion is not affected by point defects. Therefore, the channel impurity distribution can be controlled by the ion implantation energy and the dose amount, and the impurity distribution as intended by the device designer can be realized.

The effect on the variation of the threshold V _TH depending on the gate electrode thickness is as follows. First, from the viewpoint of the device structure, the impurity distribution is made substantially flat from the deep portion of the substrate to the surface. This allows
Even if the depth of the entire impurity region fluctuates, the surface concentration does not change, and the fluctuation of V _TH can be suppressed. From the viewpoint of the manufacturing method, in the channel ion implantation step, the implantation is performed at least once so that the peak of the depth under the gate is located on the substrate surface. As a result, the gradient of the impurity concentration in the depth direction on the substrate surface immediately after the ion implantation becomes almost zero. Therefore, even if the depth of the implantation peak fluctuates to some extent, the change in the surface concentration is small, and the fluctuation in V _TH can be suppressed.

[0012]

FIG. 1 is a first embodiment according to the present invention.
Here, an n-channel device is taken as an example. Silicon substrate 1
After the element isolation insulating film 6, the gate insulating film 4, and the gate electrode 5 are formed on (the region of interest is p-type doped by well formation, etc.), arsenic (As) is applied to the gate electrode 5. As a mask, ion implantation of about 5 × 10 ¹⁵ cm ^{−2 is performed} to form the source / drain regions 3A. At this stage, the source / drain region 3A is electrically inactive, the crystal structure is broken around the source / drain region 3A, and many point defects are present (FIG. 1a).

Next, a high temperature heat treatment (for example, 1 at 1000 ° C.
0 seconds or 850 ° C. for 10 minutes). As a result, the injected As is settled in the lattice position and the inactive source
The drain region 3A is converted into an electrically active source / drain region 3B. On the other hand, at this time, point defects flow out of the substrate due to diffusion, or interstitials and vacancies are recombined and almost disappear (FIG. 1b).

Next, boron (B) is ion-implanted at about 10 ¹² to 10 ¹³ cm ^-2 to form a high concentration channel region 2A (FIG. 1c). At this time, the depth of the concentration peak is set to the source / drain region 3B in order to suppress the short channel effect.
Set to a depth equivalent to the bottom edge (joint depth) of. next,
The high temperature heat treatment is performed again to activate the boron in the electrically inactive region 2A. Thereby, the electrically active p-type high concentration channel region 2B is formed. At this time, the source
Since the defects caused by the drain implantation no longer exist, the accelerated diffusion of boron is prevented.

In the above embodiment, channel injection was performed only once. In that case, the peak position of boron injected into the channel is usually selected to be almost equal to the depth of the source / drain under the gate in order to suppress the short channel effect. However, in that case, a gradient occurs in the impurity distribution on the substrate surface, and the controllability of the threshold value V _TH becomes poor. FIG. 2 shows a second embodiment according to the present invention, which takes measures against this point. Implantation and activation of the source / drain are performed in the same manner as in FIGS. Then, just below the gate electrode 5, boron is implanted so that the concentration peak is near the surface of the substrate 1 (FIG. 2a). This implantation prevents variations in V _TH . Next, just below the gate electrode 5, boron is injected again so that the concentration peak is near the depth of the source / drain 3 (FIG. 2B). Finally, high temperature heat treatment is performed to activate the implanted boron. As a result, a band-shaped p-type high-concentration channel region 2B having a substantially uniform concentration distribution in the depth direction is formed (FIG. 2).
c). According to this embodiment, it is possible to prevent accelerated diffusion of impurities in the channel and suppress an increase in variations in V _TH . The order of the first and second boron implantations may be exchanged.

FIG. 3 and FIG. 4 show typical examples of the boron depth distribution in the gate electrode portion in the above two embodiments. The former is a simulation result immediately after boron implantation, and the latter is a simulation result after boron activation heat treatment. The vertical axis has a logarithm on the left side and a linear scale on the right side. The depth of the source / drain is assumed to be 100 nm. In the figure, "single-step implantation" refers to the case where boron implantation is performed in one step as in the first embodiment, and the peak position of the distribution is set near 100 nm, which is the same as the source / drain. This is to suppress the short channel effect. Here B is 7
We have driven 1.3 × 10 ¹³ cm ^-2 at 0 keV. Then, in FIG. 3 immediately after the implantation, the concentration gradient is large on the substrate surface. Therefore, the thickness of the gate electrode (design value 150 nm)
Even with a slight fluctuation, the boron concentration on the substrate surface fluctuates greatly.

On the other hand, the "two-step implantation" is that the boron implantation is performed in two steps as in the second embodiment, and one of them is set so as to have a peak on the substrate surface. The shallower implant sets the threshold and the deeper implant prevents the short channel effect. In this example, boron is 45 ke
4 × 10 ¹² cm ^-2 at V and 9 × 10 ¹² cm ^{-2 at} 80 keV
I am driving. In this case, the impurity concentration gradient on the substrate surface is close to zero. Therefore, the threshold value does not change much even if the thickness of the gate electrode fluctuates to some extent. When heat treatment is performed (FIG. 4), boron diffuses out of the substrate, and as a result, the surface concentrations of the first-step implantation and the second-step implantation are almost the same. Therefore, the threshold values of both are equal. When the two-step implantation is performed, the distribution in the depth direction becomes almost flat, and two peaks remain in the concentration distribution. FIG. 5 is a simulation result of a change in threshold value in the above-mentioned first-step implantation and second-step implantation when the gate electrode thickness is changed. For the reasons already mentioned, the threshold value varies greatly in the former case, but is almost suppressed in the latter case.

In the above, the depth of the source / drain is 10
Although it is assumed that the depth is about 0 nm or more, when a shallower source / drain is used, even if the second boron implantation is omitted in the second embodiment, the depth is larger than the source / drain depth. It is conceivable that the substrate concentration can be increased sufficiently to a slightly deep position. In this case, it is possible to sufficiently suppress the short channel effect and suppress the variation in the threshold value V _TH by performing the boron implantation having the peak on the substrate surface only once under the gate electrode. That is, in the second embodiment, the second boron implantation can be omitted. This is shown in FIG. 6 as a third embodiment. Source·
The formation of the drain 3B is performed in the same manner as in FIGS. Then, as in FIG. 2c, boron is implanted through the gate electrode 5. However, the peak position after the implantation should be located on the surface of the substrate 1 directly below the gate electrode 5 (see FIG. 6).
a). Then, the implanted boron is activated by high temperature heat treatment (FIG. 6b). In this method, the source / drain 3B
If it is not sufficiently shallow (approximately 100 nm or less), the short channel effect may deteriorate.

In the above first, second and third embodiments,
The case where the source / drain region 3 and the high-concentration channel region 2 do not overlap with each other except for a partial region near the channel is shown. This situation is desirable to keep the source / drain parasitic capacitance low. However, the essence of the present invention in these embodiments is to suppress the enhanced diffusion and to realize it without variations in the threshold value. Therefore, the fact that the two regions do not overlap in these embodiments is not necessarily the essence of the present invention, and may overlap.

On the other hand, the reduction of the threshold variation according to the present invention is effective even when only the source / drain capacitance is intended to be reduced and the prevention of the enhanced diffusion is not taken into consideration. Figure 7
Shows a fourth embodiment according to the present invention in such a case. After forming the element isolation insulating film 6, the gate insulating film 4, and the gate electrode 5 on the silicon substrate 1, boron penetrates through the gate electrode, and the range of the peak is the gate electrode 5.
Implanted so as to be the surface of the substrate 1 immediately below (FIG. 7).
a). At this time, the source / drain depth and the gate electrode height are set so that the high-concentration channel region 2 is deeper than the source / drain region 3. Next, just below the gate electrode 5, boron is injected again so that the peak of the range is near the depth of the source / drain (FIG. 7b). Next, arsenic (As) was used for 5 × 10 5 with the gate electrode as a mask.
Ions are implanted at about ¹⁵ cm ^-2 to form the source / drain regions 3A (FIG. 7c). Finally, the source / drain 3 and the high concentration channel region 2 are activated by high temperature heat treatment (FIG. 7d).

If the purpose is merely to reduce the parasitic capacitance without considering the enhanced diffusion, the order of the above ion implantation is arbitrary. In addition, if the source / drain is sufficiently shallow, the second boron implantation can be omitted.
This is the same as the embodiment.

Although an n-channel device is used as an example in the above description, this does not limit the scope of the present invention. p
In the channel device, boron (P) is used as the channel impurity, and arsenic (source / drain impurity) is replaced with boron or boron fluoride (BF ₂ ), and the p-type and the n-type are interchanged. Applicable. Although the source / drain structure is the simplest single / drain structure, the present invention can be easily applied to various modifications such as an LDD structure in which the source / drain implantation is performed in two steps. That is clear.

[0023]

EFFECTS OF THE INVENTION By activating heat treatment of source / drain impurities, channel impurities are ion-implanted through the gate electrode to prevent accelerated diffusion of channel impurities and increase abnormal threshold value V _TH. The instability of _{TH and} the increase in the short channel effect due to the concentration decrease in the deep part of the base are prevented. Since the unpredictable accelerated diffusion is eliminated, the device characteristics as designed can be easily realized.

When channel impurities are implanted through the gate electrode, the channel impurities are implanted so as to have a peak on the surface of the substrate under the gate, so that variations in the threshold voltage V _TH of the element due to variations in the thickness of the gate electrode. Can be suppressed. As a result, the source / drain capacitance can be reduced without increasing the V _TH variation.

There is a band-shaped high-concentration channel impurity region having a substantially flat concentration distribution in the depth direction and a substantially constant width in the depth direction, and the upper end of the high-concentration region is in contact with the substrate surface immediately below the gate electrode, and By providing an element structure in which the high concentration region does not contact the surface of the substrate in the source / drain region, it is possible to prevent accelerated diffusion or reduce the source / drain capacitance without increasing V _TH variation.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment according to the present invention.

FIG. 2 is a sectional view showing a second embodiment according to the present invention.

FIG. 3 is a diagram showing an example of a substrate impurity distribution immediately after ion implantation according to the present invention.

FIG. 4 is a distribution of substrate impurities at the time of completion of the device according to the present invention.
It is a figure showing an example.

FIG. 5 is a diagram for explaining the effect of the two-step injection method.

FIG. 6 is a sectional view showing a third embodiment according to the present invention.

FIG. 7 is a sectional view showing a fourth embodiment according to the present invention.

FIG. 8 is a cross-sectional view showing a method of manufacturing a general conventional MISFET.

FIG. 9 is a diagram showing a characteristic example of an nMISFET affected by enhanced diffusion.

FIG. 10 Conventional MI with reduced source / drain capacitance
It is sectional drawing which shows the manufacturing method of SFET.

[Explanation of symbols]

 1 semiconductor substrate 2 high concentration channel impurity region 2A before activation 2B after activation 3 source / drain region 3A before activation 3B after activation 4 gate insulating film 5 gate electrode 6 element isolation insulating film 7 cover insulating film

Claims (8)

[Claims] 1. A gate insulating film formed on a semiconductor substrate doped with impurities of a first conductivity type, a gate electrode formed on the gate insulating film, and both sides of the gate electrode in the semiconductor substrate. A source / drain region of the second conductivity type formed in
The first conductivity type impurity distribution has a band-shaped high concentration region having a substantially flat concentration distribution in the depth direction and a substantially constant width in the depth direction, and the upper end of the high concentration region has the gate electrode. Immediately below (channel region), in contact with the surface of the substrate,
In addition, the high concentration region does not contact the surface of the substrate in the source / drain regions. 2. An upper end of a belt-shaped high-concentration region is the source.
The MIS transistor according to claim 1, wherein the drain region is deeper than the source / drain. 3. The MIS transistor according to claim 1, wherein the strip-shaped high-concentration region has at least two local maximum points. 4. A semiconductor substrate of a first conductivity type having a gate electrode formed on a surface thereof with a gate insulating film interposed between the first conductivity type impurity and a portion of a first conductivity type impurity immediately below the gate electrode. 2. A method of manufacturing a MIS transistor, further comprising the step of implanting ions so that a peak is located near the surface of the semiconductor substrate. 5. A first-conductivity-type semiconductor substrate having a gate electrode formed on its surface with a gate insulating film interposed between the first-conductivity-type impurity and the first-conductivity-type impurity immediately below the gate electrode. A first implantation step of ion-implanting so that a peak is located near the surface of the semiconductor substrate, and a first conductivity type of ion implantation that penetrates the gate electrode and is deeper than the first implantation step. A second implantation step of ion-implanting an impurity, and a method of manufacturing a MIS transistor. 6. A source / drain region is formed by ion-implanting a second conductivity type impurity into a semiconductor substrate having a gate electrode formed on the surface thereof via a gate insulating film, using the gate electrode as a mask. A heating step for activating impurities in the source / drain regions, and a step of injecting a first conductivity type impurity through the gate electrode following the heating step. A method for manufacturing a featured MIS transistor. 7. The MIS transistor according to claim 6, wherein the step of ion-implanting the impurity of the first conductivity type includes the step of ion-implanting so that a peak is located near the surface of the semiconductor substrate immediately below the gate electrode. Manufacturing method. 8. A first implanting step of implanting ions of a first conductivity type impurity so that a peak is located near the surface of the semiconductor substrate immediately below the gate electrode, and the peak is 7. A method of manufacturing a MIS transistor according to claim 6, further comprising a second implantation step of implanting ions so as to be deeper than the first implantation step.