KR0122456B1 - Mode detection method of hot backup device (HBU) - Google Patents

Abstract

In order to reliably and quickly detect CPU failures and other failures in a redundant system of programmable logic controllers (PLCs), the mode transition structure can be switched to three modes and a hot back Up) The CPU reads the status data by an interrupt of the internal mode detection control unit, and informs the main UE about the magnetic operation of the corresponding mode, and the frequency pulse corresponding to this active mode. A mode detection method of a hot backup apparatus in which a mode detection control unit is instructed to output a pulse detection pulse output.

Description

Mode detection method of hot backup device (HBU)

1 is a block diagram of a programmable logic controller (PLC) redundancy system according to the present invention,

2 is a configuration diagram of the hot backup device shown in FIG.

3 is a mode detection control unit and peripheral circuit diagram according to the present invention,

4 is a mode transition state diagram according to the present invention,

5 is a control cable and serial communication link diagram for determining an active mode in a conventional programmable controller, ie, a programmable controller (PC).

* Explanation of symbols for main parts of the drawings

101-104: control cable, 105,105 ': tie breaker,

106,106 ': Logic High, l07: Jumper,

108: Serial communication link,

109,109 ': primary / secondary arbitor,

1,1 ': remote I / O switch, 2,2': main CPU,

3,3 ': Hot Back Up, 4,4': Mother Board,

7: remote input / output controller, 31: shared memory,

32: Mother Board Interface,

33: data memory, 34: CPU, or central processing unit,

35: mode detection control unit, 36: communication control device,

37: Tri-State Buffer, 38: Mode Setting Switch,

39: output driver, 40: transmit / receive driver,

41, 42: Terminal block, 50: Control Bus,

52,55: hot backup address bus,

53: Hot Back Up Control Bus, 51,54: Hot Backup Data Bus,

67: Interrupt, i.e. interception,

80,81: Mode detection pulse (pulse) entry and exit.

The present invention In the redundancy system of programmable logic controller (PLC) as a process control device, it is stable so that process control processing can be continuously performed in case of failure and other failures of the main CPU (Central Processing Unit) device. The present invention relates to a mode detection and a mode change method in which the failure and failure can be detected quickly and the main CPU can continuously perform a process control process.

In the prior art, the mode detection operation detects an active mode and a backup mode. In the primary / secondary arbitor technology, two primary / secondary programmable controllers are used. It can be operated in active mode at the same time at startup, and in order to prevent this, two primary / secondary programmable controllers are initially installed simultaneously in active mode by installing a tie breaker input. It prevents it from working.

In addition, when there are external physical deformations such as a control cable and a detachment of a jumper 107, two primary and secondary programmable controllers may be operated in an active mode.

In addition, the two active modes as described above can be generated by performing the mode detection operation using the dual-mode structure of the active mode and the backup mode. There is a problem.

In addition, since four signals for processing two functions for mode detection are generated through the control cables 101 to 104, the complexity and the likelihood of failure due to the cable are high.

5 is a block diagram of a control cable for determining an active mode in a conventional programmable controller (PC). Here, the primary side programmable control cable 100, the secondary side programmable controller 100 ', the My Primary Request signal 101, the Arthur Primary Request signal Other primary request signal 102, Warn Other signal 103, Other Warns Me signal 104, tie breaker 105, 105 ', Logic High 106, 106', serial It consists of a communication link (Link 108), a hot backup device (Hot Back Up: 109, 109 '), a primary and secondary secondary arbitrator (Arbiter 110, 110'), a jumper (Jumper 107), and the like.

In the conventional apparatus configured as described above, as illustrated in FIG. 5, the primary side programmable controller 100 and the secondary side programmable controller 100 'have the same back up modules 109 and 109', respectively. The backup module is connected to the serial communication link 108 and control cables 101 to 104. In addition, the control cable signal is connected to the primary and secondary arbitrators 110 and 110 'in the hot backup device 109 and 109', and the two backup modules 109 and 109 'are connected by the control cable. Used for system initialization or reset to determine which of the two programmable controllers 100, 100 'will act as active mode or backup mode.

The buckup module 109 of the first order programmable controller 100 generates a My Primary Request signal 101 and requests the primary programmable controller 100 to operate in active mode. . In addition, the backup module 109 'of the secondary side programmable controller 100' also generates another primary request signal 102, and the secondary side programmable controller 100 'operates in an active mode. Requires. The signal is continuously generated to operate as an active mode after initialization, and the signal is connected to the primary / secondary arbitrators 110 and 110 'to determine the mode by a state machine therein. do.

With this determination, the signal continues to be generated when operating in active mode, and if a failure occurs, the signal is stopped and notified to the programmable controller operating in the backup mode to switch to the active mode.

Then, a warning other signal 103 to another person and another warns me signal 104 to others are inputted and outputted to each other to monitor the failure of the primary / secondary programmable controller. Notify the programmable controller.

In addition, since the two programmable controllers can operate in an active mode according to the primary / secondary arbitration (110,110 ') technology, in order to prevent this, an input of a tie breaker (105,105') is provided to provide logic. The jumper (Jumper 107) is connected to a high (Logic High 106, 106 '), pulled-up terminal to set the initial behavior of the active mode. The tie breaker of the opposing programmable controller opens it and sets it up to run in backup mode.

However, as described above, in the prior art, there is a problem that two active modes may be generated at the same time, and a plurality of signals are excessively generated, and thus the possibility of failure due to a complicated internal structure is very high.

Therefore, in order to solve this problem, the present invention provides a remote I / O switching device (1,1 ') and a main CPU device on each of two mother boards (4,4'). : Primary Side / Secondary Side), Hot Back Up Device (3,3 '), these two PLCs are connected by Hot Backup Cable (5), Remote Station Mother (Remote Station Mother) The remote input / output (I / O) control unit 7 and the input / output I / O configured in the board (9) are connected to the motherboard (4, 4 ') by a double loop coaxial cable (6). The hot backup device 3, 3 'of FIG. 2 is connected to the motherboard 4, 4' bus (control bus 50, data bus 51, address bus 52). Is connected to the shared memory 31 and is connected to the hot backup buses (control bus 53, data bus 54, address bus 55). The program memory 30, the data memory 34, the mode detection control unit 35, and the communication control unit 36 are connected to the hot backup bus, and the mode detection control unit 35 and the sipe oil 34 are connected to the hot backup bus. Interrupt means intercept and is connected by symbol 67 of FIG. In addition, the communication control device 36 is connected to the serial communication line 56 and the mode detection control unit 35 is connected to the mode detection pulse line (Mode Detection Pulse Line) 57 of the hot backup device The present invention relates to a detection method.

In addition, in the present invention, the mode detection and the peripheral circuit (FIG. 3) may include the interline 67, the clock 66, the data bus 54, and the control bus of the mode detection control unit 35. (53), reset (67), mode set data bus (Mode Set Data Bus: 79), enable (82) of tri-state buffer (37), hardware filter signal Input / output to (H / W Fault Siganal: 76) and its mode set switch (38), output driver (39), terminal block (Termi-nal Block: 41, 42) and communication control device (36). The present invention relates to a mode detection method of a hot backup device including a transmission / reception driver 40 and a transmission / reception driver power 43.

Therefore, the mode detection method of the hot backup device (HBU) according to the present invention allows the mode change state structure to be switched by three modes, and the internal mode of the hot backup device (3, 3 '). The status data (Status Data) is read by the sieve oil 34 of FIG. 2 by the interrupt 67 of the detection control unit 35, and the sieve oil (CPU) 34 starts the operation of the mode. It informs the main receiver device 2, 2 'of its active mode and instructs the mode detection control unit to output the mode detection pulse of the frequency pulse corresponding to the active mode. According to the status data, the I / O switching device (1,1 ') and the primary / secondary primary CPU (2,2') of FIG. 1 are connected to the hot backup device. Participation in mode detection led to the determination of the active mode.

In addition, by using the mode setting switch 38 of FIG. 3, two programmable logic control modes can be forced into three mode states of master, slave, and single. Early active mode was snowed.

In addition, two different frequency pulses are used as the signals of the mode detection pulse input / output (80,81) of FIG. 3, and the output of a pulse when a hardware pulse (H / W Fault) and a software pulse (S / W Fault) occur. Generated.

In the hot backup mode detection method according to the present invention, the mode state transition structure is switched to three modes, and the mode detection control unit 35 in the hot backup (3, 3 ') device is interleaved. The status data is read by the reciprocating oil (CPU) 34 of FIG. 2 by the rot 67, and the sieving oil 34 starts operation of the corresponding mode, and its active mode is transferred to the main CPU (2, 2). ') And instructs the mode detection control unit to output the mode detection pulse of the frequency pulse corresponding to the active mode.

According to the status data, the I / O switching device (1, 1 ') and the primary / secondary main CPU (2, 2') of FIG. Participate in the detection to determine the active mode.

In addition, the mode setting switch 38 of FIG. 3 forces two programmable logic controller modes to set the state of the three modes of master, slave and single to the initial active mode. In addition, two different frequency pulses are used as the signal of the mode detection pulse input / output (80.81) of FIG. 3, and a hardware fault and a software fault are generated.

Example

Hereinafter, an embodiment of the present invention will be described with reference to the government drawings.

In FIG. 1, a programmable logic controller (PLC) redundancy system corresponds to an active mode in the event of a transition such as the mode transition state diagram of FIG. 4 on each of the two motherboards 4 and 4 'as shown in FIG. Remote I / O disease device (1,1 ') that performs I / O control switching for input / output I / O control Primary / secondary-side main CPU units (2,2 '), device data of the main CPU unit, and status of the main CPU unit, which are responsible for the calculation of the sequence program. It consists of a hot backup (HBU) device (3, 3 ') which transmits (Status) to another main CPU and detects the mode.The two PLCs are connected to a hot backup cable (HBU Cable) ( 5) is connected. In addition, remote I / O control on the Remote Station Mother Board (9) and the remote I / O controller (7) and I / O are double loop coaxial cables (6). The motherboard (Mather Board) (4, 4 ') is connected to the connection.

In addition, the hot back up device 3, 3 'of FIG. 2 is connected to a mother board 4, 4' bus (control bus 50, data bus 51, eded bus 52). Motherboard Interface 32, which is responsible for the interface with the Hot Back Up device 3, 3 ', is the device data of the main CPU device 2, 2'. (Device Data), main CPU status, hot backup (HBU) data (Status), command (Command), mode data can be shared and accessed at the same time It is connected to the shared memory 31 and is connected to a hot backup bus (HBU Bus) (control bus 53, data bus 54, address bus 55).

Then, the program memory 30 that controls the operation of the CPU 34 on the hot backup bus, the data for transmission / reception to the relative hot backup (HBU) device, and a working variable A data memory 33 having a control unit, a communication control unit 36 for controlling transmission / reception data Data, a mode detection control unit 35 for mode detection control is connected, and a mode detection control unit ( 35) and the CPU (CPU) is connected to the mode detection interrupt (Interrupt) 67 to generate an interrupt according to the mode detection and transition to the CPU (34).

The communication control device 36 is connected to the serial communication line 56, and the mode detection control unit 35 is connected to the mode detection pulse line (P1use Line) 57.

The mode detection and the peripheral circuit (FIG. 3) include an interrupt line 67, a clock 66, and a data bus 54 of the mode detection control unit 35. ), Control bus 53, reset (67), mode set data bus 79, enable signal 82 of three-phase buffer 37, hardware fault signal Input / output to (76) and other mode switch 38, output driver 39, terminal blocks 41 and 42, communication control device 36, transmit / receive driver 40, transmit / receive driver power It consists of 43.

Two hot backup (HBU) units (3, 3 ') are connected by a hot backup cable (5), which consists of a mode detection pulse line (57) and a serial communication line (56). When a reset 70 is generated through the pulse detection pulse line or a Fault signal 63 is generated due to a fault, two programmable logic controllers (PLCs) are connected to the master mode according to the mode transition state diagram of FIG. It generates a signal (heterogeneous frequency pluse) to determine whether the signal is de-lave, slave-mode, or single-mode, and accepts the signal of the other party and maintains the output signal.

The reset 70 of the mode detection control unit is initialized by receiving a logic OR, that is, a logic sum signal of the power reset 68 and the bus reset 69. ) Input line 63 inputs the signals of the hardware WDT error 62 of the hot backup (HBU) device and the logic OR of the hardware error 64 of the main CPU device (2, 2 '). Even if the CPU 34 of the hot backup (HBU) device 3 or 3 'is out of the operation sequence of the program memory 30 or cannot operate, the hardware failure signal 76 line is externally. Send the fault output 83 through the output of.

As shown in FIG. 4, determining whether to be a master mode, a slave mode, or a single mode is primarily a mode detection control unit 35. Is determined, and the determined status is interrupted to the CPU 34 of FIG. 2 using the Interrupt 67 output line. Then, the CPU 34 reads the status data of the mode detection control unit through the data bus 54 and determines the mode detection control unit according to the status data. Whether the I / O switching unit (1, l ') and the main pumping unit (CPU) unit (2,2') will re-determine the main pumping unit (CPU) (2,2 '). Determines and instructs the mode detection control unit to output a dual frequency pulse corresponding to the mode state. Accordingly, the mode detection control unit 35 transmits the mode pulse line 75. It generates and maintains the output signal to inform the other hot backup (HBU) device, and the other hot backup (HBU) device performs the same mode detection operation as above and generates and maintains the output signal.

The mode detection control unit 35 outputs a pulse output through a mode pulse line 75 at initialization and receives a pulse input of the mode pulse line 74 to receive an internal timer. ) Count the output and input pulses during the set time, so if the output count is large, the master mode is small, if not, the slave mode is small, and if there is no input pulse, the single A single mode is determined and the CPU 34 is informed via an Interrupt Line 67. If the mode set switch 38 is set to Master, Slave, or Single mode, the mode is detected first and CPU Notify (34).

When a mode is determined as described above and a failure occurs during operation, the hot backup (HBU) device of the failed PLC blocks the pulse output through the mode pulse line 75 by the mode detection controller. . Send out the Fat output 83.

The other hot backup (HBU) device detects this and switches to single mode and maintains the current mode until the cause of fault is corrected and the fault is operated.

As described above, according to the present invention, the state transition structure of the mode is converted into three modes of a master, a slave, and a single mode. The I / O switching device (1,1 ') and the 1st / secondary main CPU device (2,2') provide status data so that one PLC cannot operate in one mode. Participate in mode detection mediation according to the data) to eliminate unstable factors due to mode detection and transition.

In addition, by using two different frequency pulses as the mode detection pulse input / output signals 80 and 81, the mode detection pulse signal is simply transferred to provide a hot backup cable. The possibility of failure and the effects of (5) were minimized.

The mode setting switch 38 forces two PLC active modes to be selected as the initial active mode in three mode states: Master, Slave, and Single. This led to a more stable active mode.

Therefore, it is possible to provide a mode detection method having the above reliability and efficiency.

Claims (4)

In the redundant system of the programmable logic controller as a sequence process control device, it is possible to continuously and stably process control processing in the event of a failure or failure of the CPU 2,2 'device. In the mode detection method of a hot back-up device (3, 3 ') for the mode detection, the mode detection and its peripheral circuits are inter-interline of the mode detection control unit. (Interrupt Line), Clock, Data Bus, Control Bus, Reset, Mode Setting Data Bus, Tri-State Buffer (37) Input / output with enable signal, hardware pulse signal (H / W Fault Signal), its mode setting switch, output driver (39), terminal block, communication control device, It consists of a transmit / receive driver 40 and a transmit / receive driver power. The mode transition structure is detected by detecting three modes of the master mode, the slave mode, the single mode, and the single mode. The state data 34 reads the status data by the interrupt of the mode detection control unit inside the hot backup device, and the sipe oil 34 starts the operation of the corresponding mode, Hot backup, characterized by informing the main sipeu device 2,2 'and instructing the mode detection control unit to generate a mode detection pulse output of a frequency pulse corresponding to this operation mode. Method of mode detection of (HBU) devices. The method of claim 1, wherein in detecting the three modes, determining whether to be the master mode, slave mode, and single mode is primary. The mode detection control unit determines, and the status of the determined mode is applied to the CPU 34 by using the interrupt output line, and thus the CPU 34 is applied. Whether the mode detection control unit reads the status data through the data bus 54 and receives the determination of the mode detection control unit according to the status data to process the process; This main sipeu decides whether the device and the main sieve oil device (2, 2 ') will re-determine, and instructs the mode detection control unit to output heterogeneous frequency pulses corresponding to the mod state. -De-detection control unit via mode pulse line To generate and maintain an output signal to notify the other hot backup device, and the other hot backup device also performs the same mode detection operation as above and generates and maintains an output signal. -De detection method. The method according to any one of claims 1 to 4, wherein the mode detection control unit counters the pulse input at initialization and counts the output and the input pulse during the internal timer setting time, so that if the output count is large, the master mode, If not, the slave mode mode input pulse is determined as single mode mode, and it is informed to the sipeu 34 through the inter-raffline, and if the mode setting switch is set to master, slave, single mode, If it is, the mode is first detected and notified to the sieve oil 34. When a mode is determined and a failure occurs during operation, the hot backup device of the PLC that has failed generates a mode pulse line by the mode detection controller. The pulse output is cut off, the fault output is internalized, and the opposing hot backup device detects this and converts it into a single mode so that the cause of the pulse is healed and resumes normal operation. De Detection - maintaining the de base of a hot backup unit, characterized in that the copper-clad Kane-current mode till then. The method of claim 1, wherein the reset (70) of the mode detection control unit is a logical OR of the power reset (68) and the bus reset (Bus Reset) 69 It is initialized by receiving a signal as an input and is a fault. Input line 63 shows hardware WDT error (H / W WDT Error) 62 of hot backup (HBU) device and hardware error (H / W Error) of main CPU device (2, 2 ') 64. Although the logical oil 34 of the hot backup (HBU) value (3,3 ') is out of the operation sequence of the program memory 30 or cannot be operated by inputting a logical OR signal. A mode detection method for sending a pulse output (83) through an output of a hardware pulse signal (H / W Fault Line) (76) to the outside.