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JPS6482244A - Data communication processor - Google Patents

Data communication processor

Info

Publication number
JPS6482244A
JPS6482244A JP62242101A JP24210187A JPS6482244A JP S6482244 A JPS6482244 A JP S6482244A JP 62242101 A JP62242101 A JP 62242101A JP 24210187 A JP24210187 A JP 24210187A JP S6482244 A JPS6482244 A JP S6482244A
Authority
JP
Japan
Prior art keywords
register
reexecution
data communication
load
selector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62242101A
Other languages
Japanese (ja)
Inventor
Takuma Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62242101A priority Critical patent/JPS6482244A/en
Publication of JPS6482244A publication Critical patent/JPS6482244A/en
Pending legal-status Critical Current

Links

Landscapes

  • Computer And Data Communications (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Abstract

PURPOSE:To quickly detect the abnormality of a system and to distribute the load of the bus use to improve the efficiency of system design by providing first and second reexecution number designating registers, a selector, reexecution number counters, etc. CONSTITUTION:A first register 10 and a second register 11 designate numbers of times of reexecution, and a selector 13 selects one register by a flag 12. Contents of the selected register are set to a reexecution number counter 14 and are decremented by one at each time of reexecuting, and an execution control part 15 repeatedly indicates transfer until the value of the counter 14 reaches zero. In such a case, the value set to a reexecution timing register 18 is made different among data communication processing devices to distribute the load. The number of times of reexecution required for normal data communication processing is set to the register 10, and a larger number is set to the register 11. Thus, the abnormality of the system is quickly detected and the load of the bus use is distributed to improve the efficiency of system design.
JP62242101A 1987-09-25 1987-09-25 Data communication processor Pending JPS6482244A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62242101A JPS6482244A (en) 1987-09-25 1987-09-25 Data communication processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62242101A JPS6482244A (en) 1987-09-25 1987-09-25 Data communication processor

Publications (1)

Publication Number Publication Date
JPS6482244A true JPS6482244A (en) 1989-03-28

Family

ID=17084317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62242101A Pending JPS6482244A (en) 1987-09-25 1987-09-25 Data communication processor

Country Status (1)

Country Link
JP (1) JPS6482244A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04309153A (en) * 1991-04-08 1992-10-30 Fujitsu Ltd Data transfer processing device
JPH08292920A (en) * 1995-04-21 1996-11-05 Nec Corp Network management system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04309153A (en) * 1991-04-08 1992-10-30 Fujitsu Ltd Data transfer processing device
JPH08292920A (en) * 1995-04-21 1996-11-05 Nec Corp Network management system

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