[go: up one dir, main page]

JPS6481552A - Link layer control system - Google Patents

Link layer control system

Info

Publication number
JPS6481552A
JPS6481552A JP62237419A JP23741987A JPS6481552A JP S6481552 A JPS6481552 A JP S6481552A JP 62237419 A JP62237419 A JP 62237419A JP 23741987 A JP23741987 A JP 23741987A JP S6481552 A JPS6481552 A JP S6481552A
Authority
JP
Japan
Prior art keywords
level
signal
congestion
main memory
detection circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62237419A
Other languages
Japanese (ja)
Inventor
Kenji Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62237419A priority Critical patent/JPS6481552A/en
Publication of JPS6481552A publication Critical patent/JPS6481552A/en
Pending legal-status Critical Current

Links

Landscapes

  • Communication Control (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Abstract

PURPOSE:To send a congestion signal without reducing the signal processing capability of level 2 by allowing a processor for controlling level 2 to confirm only a detection signal of a signal processing congestion state detection circuit, sending the congestion signal to an opposed node. CONSTITUTION:A signal processing congestion state detection circuit 5 with >=3 level is provided on the same address space as that of a main memory 4 when viewing from the control processor 2 of >=3 level. That is, the control processor 2 with >=3 level intends to access an area representing occupancy/ vacancy state of the main memory 4 but access actually the congestion state detection circuit 5, which decodes the content and informs the result to the processor 3 for controlling level 2 at all times via a signal line 6 being a notice medium. When the area on the main memory 4 is not idle, the congestion signal SIB is sent to the opposed node via a transmission link 8.
JP62237419A 1987-09-24 1987-09-24 Link layer control system Pending JPS6481552A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62237419A JPS6481552A (en) 1987-09-24 1987-09-24 Link layer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62237419A JPS6481552A (en) 1987-09-24 1987-09-24 Link layer control system

Publications (1)

Publication Number Publication Date
JPS6481552A true JPS6481552A (en) 1989-03-27

Family

ID=17015077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62237419A Pending JPS6481552A (en) 1987-09-24 1987-09-24 Link layer control system

Country Status (1)

Country Link
JP (1) JPS6481552A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6163139A (en) * 1984-09-04 1986-04-01 Nippon Telegr & Teleph Corp <Ntt> Communication protocol controller
JPS6163141A (en) * 1984-09-04 1986-04-01 Nippon Telegr & Teleph Corp <Ntt> Communication control system
JPS61138331A (en) * 1984-12-10 1986-06-25 Fujitsu Ltd Data reception control system
JPS6269349A (en) * 1985-09-20 1987-03-30 Nec Corp Input and output interface
JPS62181552A (en) * 1986-02-06 1987-08-08 Fujitsu Ltd Communication control device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6163139A (en) * 1984-09-04 1986-04-01 Nippon Telegr & Teleph Corp <Ntt> Communication protocol controller
JPS6163141A (en) * 1984-09-04 1986-04-01 Nippon Telegr & Teleph Corp <Ntt> Communication control system
JPS61138331A (en) * 1984-12-10 1986-06-25 Fujitsu Ltd Data reception control system
JPS6269349A (en) * 1985-09-20 1987-03-30 Nec Corp Input and output interface
JPS62181552A (en) * 1986-02-06 1987-08-08 Fujitsu Ltd Communication control device

Similar Documents

Publication Publication Date Title
JPS57189231A (en) Data transferring system
EP0254960A3 (en) A multiprocessor system
KR850700200A (en) Circuit switching system
TW324128B (en) Data transmission device (2)
FR2546699B1 (en) VIDEO SIGNAL PROCESSING NETWORK WITH SYSTEMS FOR AUTOMATICALLY ADJUSTING THE WHITE BALANCE AND THE IMAGE TUBE BEAM CURRENT LIMITER
KR860000599A (en) Command transfer control system between processors
KR860007803A (en) Data transmission method
JPS6481552A (en) Link layer control system
KR920014214A (en) Home video signal processing system
EP0309330A3 (en) Access priority control system for main storage for computer
KR850002914A (en) Message-Oriented Interrupt Devices for Multiprocessor Systems
JPS57152066A (en) Opu communication system in multi-opu system
JPS57191724A (en) Power supply controlling system
JPS5518725A (en) Information control system
JPS57174726A (en) Data transfer controlling system
JPS576480A (en) Buffer memory control system
JPS57183154A (en) Multispeed transmission system
JPS55136749A (en) Data signal conversion system
JPS5644921A (en) Bus control system
JPS5665385A (en) Main memory access control system
JPS57192151A (en) Communicating system for packet signal
JPS57143633A (en) Terminal control system
JPS56107689A (en) Connection control system of automatic exchange
JPS56145442A (en) Multicomputer source controlling system
JPS6461149A (en) Overload control system for packet exchange