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JPS6478166A - Ic tester - Google Patents

Ic tester

Info

Publication number
JPS6478166A
JPS6478166A JP62235169A JP23516987A JPS6478166A JP S6478166 A JPS6478166 A JP S6478166A JP 62235169 A JP62235169 A JP 62235169A JP 23516987 A JP23516987 A JP 23516987A JP S6478166 A JPS6478166 A JP S6478166A
Authority
JP
Japan
Prior art keywords
logical
waveform
pin name
display
logical information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62235169A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Jinno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62235169A priority Critical patent/JPS6478166A/en
Publication of JPS6478166A publication Critical patent/JPS6478166A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To easily set a desired logical waveform by generating a logical waveform from logical information read out of a storage device, and displaying simultaneously plural logical waveforms and a pin name on an arbitrary position of a display. CONSTITUTION:A storage device 41 stores a pin name of an IC to be tested 70, and a storage device 42 stores logical information corresponding to a logical waveform by allowing it to correspond to the pin name. A display 43 arranges and displays the pin name and plural logical waveforms corresponding thereto. Logical waveform generating circuits 44-46 input the logical information and generate a control voltage corresponding to the logical waveform and apply it to the IC 70. Storage devices 47-49 store the logical information selected and read out of the storage 42, and on the other hand, output this logical information to the circuits 44, 45 and 46. Subsequently, when the pin name and the position of the display 43 are designated by a keyboard 40, a central processor 50 reads out its pin name and the logical information corresponding thereto, from the storage devices 41, 42, generates a logical waveform from the logical information, and displays the logical waveform and the pin name in a designated position of the display 43.
JP62235169A 1987-09-18 1987-09-18 Ic tester Pending JPS6478166A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62235169A JPS6478166A (en) 1987-09-18 1987-09-18 Ic tester

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62235169A JPS6478166A (en) 1987-09-18 1987-09-18 Ic tester

Publications (1)

Publication Number Publication Date
JPS6478166A true JPS6478166A (en) 1989-03-23

Family

ID=16982083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62235169A Pending JPS6478166A (en) 1987-09-18 1987-09-18 Ic tester

Country Status (1)

Country Link
JP (1) JPS6478166A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114002583A (en) * 2021-11-02 2022-02-01 厦门芯泰达集成电路有限公司 Pattern editing tool and method based on integrated circuit automatic test system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114002583A (en) * 2021-11-02 2022-02-01 厦门芯泰达集成电路有限公司 Pattern editing tool and method based on integrated circuit automatic test system

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