JPS6477953A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPS6477953A JPS6477953A JP23560187A JP23560187A JPS6477953A JP S6477953 A JPS6477953 A JP S6477953A JP 23560187 A JP23560187 A JP 23560187A JP 23560187 A JP23560187 A JP 23560187A JP S6477953 A JPS6477953 A JP S6477953A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- sections
- frame
- chips
- joining material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
PURPOSE:To disuse a bonding process, and to prevent the scattering of a joining material by separately connecting a chip housed in a die pad section and a second frame section by a printed wiring formed in a first frame section on the periphery of the die pad section. CONSTITUTION:A lead frame 9 is composed of lead frame A sections (nonconductors) 10 constituting first frame sections and lead frame B sections (conductors) 11 organizing second lead frame sections. Chips 15 are joined onto die pads 13 through joining materials 14 in the lead frame constructed in this manner. A process in which the chips 15 and inner leads 16 are bonded by metallic small-gage wires for connection as the next process is unnecessitated because printed wirings 12 arranged to the lead frame A sections 10 and electrodes 17 in the chips are conducted, and the die pads 13 function as the antirunning of the joining material because the shapes of the die pads 13 are constituted slightly of irregularities, thus preventing scattering, adhesion, etc., to the inner leads 16 of the joining material.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23560187A JPS6477953A (en) | 1987-09-19 | 1987-09-19 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23560187A JPS6477953A (en) | 1987-09-19 | 1987-09-19 | Lead frame for semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6477953A true JPS6477953A (en) | 1989-03-23 |
Family
ID=16988421
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23560187A Pending JPS6477953A (en) | 1987-09-19 | 1987-09-19 | Lead frame for semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6477953A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5231304A (en) * | 1989-07-27 | 1993-07-27 | Grumman Aerospace Corporation | Framed chip hybrid stacked layer assembly |
CN106438257A (en) * | 2016-12-13 | 2017-02-22 | 荆门市召铭液压科技有限公司 | Double-fork inclined disc through shaft type axial plunger pump |
-
1987
- 1987-09-19 JP JP23560187A patent/JPS6477953A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5231304A (en) * | 1989-07-27 | 1993-07-27 | Grumman Aerospace Corporation | Framed chip hybrid stacked layer assembly |
CN106438257A (en) * | 2016-12-13 | 2017-02-22 | 荆门市召铭液压科技有限公司 | Double-fork inclined disc through shaft type axial plunger pump |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW200520120A (en) | Semiconductor device package and method for manufacturing same | |
WO1998052217A3 (en) | Method of forming a chip scale package, and a tool used in forming the chip scale package | |
JPS6428945A (en) | Circuit package assembly | |
AU1339797A (en) | Multi-chip device and method of fabrication employing leads over and under processes | |
JPS57207356A (en) | Semiconductor device | |
MY105095A (en) | Semiconductor device having an improved lead arrangement and method for manufacturing the same. | |
TW370694B (en) | Semiconductor device | |
GB9622954D0 (en) | Integrated circuit package and method of fabrication | |
FR2720190B1 (en) | Method for connecting the output pads of an integrated circuit chip, and multi-chip module thus obtained. | |
MY119797A (en) | Resin-molded semiconductor device having a lead on chip structure | |
JPH02278740A (en) | Packaging of semiconductor device | |
JPS6419737A (en) | Multilayer interconnection tape carrier | |
JPS6477953A (en) | Lead frame for semiconductor device | |
JPS57126154A (en) | Lsi package | |
EP0394878A3 (en) | Semiconductor device having multi-layered wiring structure | |
CA2273223A1 (en) | Chip-size package using a polyimide pcb interposer | |
JPS5640268A (en) | Semiconductor device | |
MY106858A (en) | Resin sealing type semiconductor device in which a very small semiconductor chip is sealed in package with resin. | |
JPS647645A (en) | Semiconductor device and manufacture thereof | |
JPS5694753A (en) | Correction method of semiconductor ic chip mounted substrate | |
JPS55124248A (en) | Leadless package | |
KR200155176Y1 (en) | Semiconductor package | |
SG73480A1 (en) | High density integrated circuit package | |
JPS6467947A (en) | Ic package substrate | |
JPS5778146A (en) | Integrated circuit device |