[go: up one dir, main page]

JPS6473936A - Digital radio transmission equipment - Google Patents

Digital radio transmission equipment

Info

Publication number
JPS6473936A
JPS6473936A JP62229621A JP22962187A JPS6473936A JP S6473936 A JPS6473936 A JP S6473936A JP 62229621 A JP62229621 A JP 62229621A JP 22962187 A JP22962187 A JP 22962187A JP S6473936 A JPS6473936 A JP S6473936A
Authority
JP
Japan
Prior art keywords
pattern
signal
output signal
input interruption
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62229621A
Other languages
Japanese (ja)
Inventor
Hidemasa Yamauchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62229621A priority Critical patent/JPS6473936A/en
Publication of JPS6473936A publication Critical patent/JPS6473936A/en
Pending legal-status Critical Current

Links

Landscapes

  • Time-Division Multiplex Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To hold a spectrum of an output signal by outputting a signal being the result of an elastic memory output signal scrambled by a PN pattern. CONSTITUTION:In case of the input interruption, an input interruption signal 103 being an output of an input interruption detecting circuit 1 goes to a logical value '1' and it is supplied to an AND gate 4. A PN pattern generating circuit 3 is controlled by the 3rd timing signal 111 outputted from a timing generating circuit 5 and outputs a PN pattern 105. That is, the input interruption signal 103 with a logical '1' and the PN pattern 105 are given to the AND gate 4 and an AND gate output signal 100 becomes the PN pattern 105. Thus, the PN pattern 105 is multiplexed by a multiplexing circuit 6 and scrambled by a 1st exclusive OR circuit 7 and the result is outputted as the output signal 109.
JP62229621A 1987-09-16 1987-09-16 Digital radio transmission equipment Pending JPS6473936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62229621A JPS6473936A (en) 1987-09-16 1987-09-16 Digital radio transmission equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62229621A JPS6473936A (en) 1987-09-16 1987-09-16 Digital radio transmission equipment

Publications (1)

Publication Number Publication Date
JPS6473936A true JPS6473936A (en) 1989-03-20

Family

ID=16895059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62229621A Pending JPS6473936A (en) 1987-09-16 1987-09-16 Digital radio transmission equipment

Country Status (1)

Country Link
JP (1) JPS6473936A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0425259A (en) * 1990-05-18 1992-01-29 Nec Corp Signal transmission system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0425259A (en) * 1990-05-18 1992-01-29 Nec Corp Signal transmission system

Similar Documents

Publication Publication Date Title
TW278152B (en) A design method of clock generating circuit and pll circuit and semi-conductor device combined with clock generating circuit
EP0228214A3 (en) Apparatus and associated methods for converting serial data pattern signals transmitted or suitable for transmission over a high speed synchronous serial transmission media, to parallel pattern output signals
GB8824338D0 (en) Programmable multiplexer circuit
TW335543B (en) Row decoder with level translator
MY112568A (en) Testing sequential logic circuit upon changing into combinatorial logic circuit
TW325608B (en) Timing signal generation circuit and a display device using such a circuit
EP0111262A3 (en) Output multiplexer having one gate delay
JPS6473936A (en) Digital radio transmission equipment
GB2146818B (en) Voice generating devices
JPS5439617A (en) Noise signal forming circuit
MY104382A (en) Signal synchronizing system.
JPS5593235A (en) Integrated circuit
JPS56108130A (en) Switch circuit
JPS6439154A (en) Digital radio trasmitter
FR2469006B1 (en)
JPS5694859A (en) Data transmission system
JPS5621440A (en) Stuff synchronizing system
JPS5212868A (en) Automatic synchronizing signal generating circuit
ES8402437A1 (en) A device for generating binary digit pseudo-random sequences
JPS5373047A (en) Generation circuit for timing signal
JPS5753680A (en) Electronic watch with melody
JPS57157660A (en) Signal transmission system
JPS644132A (en) Multi-frame transmission system
JPS5319704A (en) Signal transmission system
JPS51146152A (en) Signal selection circuit