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JPS6471218A - Input buffer circuit and input level shift circuit - Google Patents

Input buffer circuit and input level shift circuit

Info

Publication number
JPS6471218A
JPS6471218A JP63122959A JP12295988A JPS6471218A JP S6471218 A JPS6471218 A JP S6471218A JP 63122959 A JP63122959 A JP 63122959A JP 12295988 A JP12295988 A JP 12295988A JP S6471218 A JPS6471218 A JP S6471218A
Authority
JP
Japan
Prior art keywords
level shift
input
source
buffer circuit
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63122959A
Other languages
English (en)
Inventor
Shii Gurahamu Andoriyu
Ii Fuitsutsupatoritsuku Maaku
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gazelle Microcircuits Inc
Original Assignee
Gazelle Microcircuits Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gazelle Microcircuits Inc filed Critical Gazelle Microcircuits Inc
Publication of JPS6471218A publication Critical patent/JPS6471218A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0952—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using Schottky type FET MESFET
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018535—Interface arrangements of Schottky barrier type [MESFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
JP63122959A 1987-05-19 1988-05-19 Input buffer circuit and input level shift circuit Pending JPS6471218A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/052,660 US4791322A (en) 1987-05-19 1987-05-19 TTL compatible input buffer

Publications (1)

Publication Number Publication Date
JPS6471218A true JPS6471218A (en) 1989-03-16

Family

ID=21979065

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63122959A Pending JPS6471218A (en) 1987-05-19 1988-05-19 Input buffer circuit and input level shift circuit

Country Status (4)

Country Link
US (1) US4791322A (ja)
JP (1) JPS6471218A (ja)
DE (1) DE3817136A1 (ja)
GB (1) GB2207317B (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017005063A (ja) * 2015-06-08 2017-01-05 新日本無線株式会社 電圧発生回路、負電圧発生回路、正負電圧論理回路、及び高周波スイッチ回路

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4912745A (en) * 1987-05-19 1990-03-27 Gazelle Microcircuits, Inc. Logic circuit connecting input and output signal lines
US4918336A (en) * 1987-05-19 1990-04-17 Gazelle Microcircuits, Inc. Capacitor coupled push pull logic circuit
JPH0263319A (ja) * 1988-08-30 1990-03-02 Fujitsu Ltd 入力バッファ
US5162672A (en) * 1990-12-24 1992-11-10 Motorola, Inc. Data processor having an output terminal with selectable output impedances
US5298808A (en) * 1992-01-23 1994-03-29 Vitesse Semiconductor Corporation Digital logic protocol interface for different semiconductor technologies
US5367210A (en) * 1992-02-12 1994-11-22 Lipp Robert J Output buffer with reduced noise
US5365127A (en) * 1993-10-18 1994-11-15 Hewlett-Packard Company Circuit for conversion from CMOS voltage levels to shifted ECL voltage levels with process compensation
US5467455A (en) * 1993-11-03 1995-11-14 Motorola, Inc. Data processing system and method for performing dynamic bus termination
US5787291A (en) * 1996-02-05 1998-07-28 Motorola, Inc. Low power data processing system for interfacing with an external device and method therefor
JP2000134085A (ja) * 1998-09-16 2000-05-12 Microchip Technol Inc 低電力デジタル入力回路
JP2009033637A (ja) * 2007-07-30 2009-02-12 Panasonic Corp レベル変換回路
JP2009105848A (ja) * 2007-10-25 2009-05-14 Mitsumi Electric Co Ltd 論理ゲート及びこれを用いた半導体集積回路装置
CN112671392A (zh) * 2020-12-24 2021-04-16 中国人民解放军国防科技大学 一种用于高电平复位电路的抗单粒子瞬态缓冲器

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5739626A (en) * 1980-06-24 1982-03-04 Thomson Csf Logic inverter
JPS57113631A (en) * 1980-12-05 1982-07-15 Ibm Logic gate circuit
JPS6232640A (ja) * 1985-08-05 1987-02-12 Fujitsu Ltd 半導体集積回路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4405870A (en) * 1980-12-10 1983-09-20 Rockwell International Corporation Schottky diode-diode field effect transistor logic
US4450369A (en) * 1981-05-07 1984-05-22 Schuermeyer Fritz L Dynamic MESFET logic with voltage level shift circuit
JPH0763139B2 (ja) * 1985-10-31 1995-07-05 日本電気株式会社 レベル変換回路
JPH0763140B2 (ja) * 1985-11-13 1995-07-05 松下電器産業株式会社 ゲ−ト回路
US4701643A (en) * 1986-03-24 1987-10-20 Ford Microelectronics, Inc. FET gate current limiter circuits
US4701646A (en) * 1986-11-18 1987-10-20 Northern Telecom Limited Direct coupled FET logic using a photodiode for biasing or level-shifting

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5739626A (en) * 1980-06-24 1982-03-04 Thomson Csf Logic inverter
JPS57113631A (en) * 1980-12-05 1982-07-15 Ibm Logic gate circuit
JPS6232640A (ja) * 1985-08-05 1987-02-12 Fujitsu Ltd 半導体集積回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017005063A (ja) * 2015-06-08 2017-01-05 新日本無線株式会社 電圧発生回路、負電圧発生回路、正負電圧論理回路、及び高周波スイッチ回路

Also Published As

Publication number Publication date
DE3817136A1 (de) 1988-12-15
US4791322A (en) 1988-12-13
GB8811699D0 (en) 1988-06-22
GB2207317B (en) 1992-01-29
GB2207317A (en) 1989-01-25

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