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JPS6464411A - Receiver for digital signal processing system - Google Patents

Receiver for digital signal processing system

Info

Publication number
JPS6464411A
JPS6464411A JP22027587A JP22027587A JPS6464411A JP S6464411 A JPS6464411 A JP S6464411A JP 22027587 A JP22027587 A JP 22027587A JP 22027587 A JP22027587 A JP 22027587A JP S6464411 A JPS6464411 A JP S6464411A
Authority
JP
Japan
Prior art keywords
frequency
signal
converter
executed
digital signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22027587A
Other languages
Japanese (ja)
Inventor
Akira Nakazawa
Nobumitsu Asahi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kenwood KK
Original Assignee
Kenwood KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kenwood KK filed Critical Kenwood KK
Priority to JP22027587A priority Critical patent/JPS6464411A/en
Publication of JPS6464411A publication Critical patent/JPS6464411A/en
Pending legal-status Critical Current

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  • Circuits Of Receivers In General (AREA)

Abstract

PURPOSE:To execute the reception of a digital signal processing system not to give an adverse influence to a receiving tone by low area-converting an input analog signal to the signal of a central frequency f'c and obtaining the SH frequency of a sample hold (SH) as 3f'c/4. CONSTITUTION:The input higher harmonic signal of a central frequency fc and a band width B is multiplied by the single frequency of fc+f'c or fc-f'c in an analog multiplier 1 and low band frequency-converted to the frequency signal of the central frequency f'c. Next, non-linear operation is executed with prescribed analog operation in a non-linear operation processing circuit 2 and the output is sent to an LPF3. Then, a generated higher harmonic component is removed and the SH is executed with the SH frequency fs=4f'c/3 in an S/H circuit 4. Then, conversion to a digital signal is executed by an A/D converter 5. The output is demodulation-processed by a signal processing circuit 6 and converted to an analog signal by a D/A converter 7. In such a case, by causing the fs to be more than two fold of the B, the converter 5 and the circuit 6 are not needed to be highly speedy.
JP22027587A 1987-09-04 1987-09-04 Receiver for digital signal processing system Pending JPS6464411A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22027587A JPS6464411A (en) 1987-09-04 1987-09-04 Receiver for digital signal processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22027587A JPS6464411A (en) 1987-09-04 1987-09-04 Receiver for digital signal processing system

Publications (1)

Publication Number Publication Date
JPS6464411A true JPS6464411A (en) 1989-03-10

Family

ID=16748619

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22027587A Pending JPS6464411A (en) 1987-09-04 1987-09-04 Receiver for digital signal processing system

Country Status (1)

Country Link
JP (1) JPS6464411A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009165123A (en) * 2007-12-31 2009-07-23 Agere Systems Inc Method and apparatus for improving jitter tolerance in sfp limit amplified signal

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60145730A (en) * 1984-01-10 1985-08-01 Pioneer Electronic Corp A/d converting device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60145730A (en) * 1984-01-10 1985-08-01 Pioneer Electronic Corp A/d converting device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009165123A (en) * 2007-12-31 2009-07-23 Agere Systems Inc Method and apparatus for improving jitter tolerance in sfp limit amplified signal

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