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JPS6459558A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS6459558A
JPS6459558A JP21731187A JP21731187A JPS6459558A JP S6459558 A JPS6459558 A JP S6459558A JP 21731187 A JP21731187 A JP 21731187A JP 21731187 A JP21731187 A JP 21731187A JP S6459558 A JPS6459558 A JP S6459558A
Authority
JP
Japan
Prior art keywords
access
priority order
functional module
access request
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21731187A
Other languages
Japanese (ja)
Inventor
Tomoyoshi Inasaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP21731187A priority Critical patent/JPS6459558A/en
Publication of JPS6459558A publication Critical patent/JPS6459558A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To form a data processor with superior system performance by monitoring the number of times of access of respective functional module at a constant period, and changing the priority order of an access request from respective functional module for a main memory device according to a monitored result. CONSTITUTION:Count means (counters 5a-8a) count the number of times of access when each of the functional modules 21, 22, and 23-0-23-n generates the access request to a main processing 20. The number of times of access is monitored at the constant period, and the priority order of the access request is changed corresponding to the number of times of access. Therefore, it is possible to make access to the main memory device 20 preferentially by the functional module with large number of times of access out of the functional modules 21, 22, and 23-0-23-n. In such a way, it is possible to set the optimum priority order of a system bus usage right corresponding to the operating state of the data processor.
JP21731187A 1987-08-31 1987-08-31 Data processing system Pending JPS6459558A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21731187A JPS6459558A (en) 1987-08-31 1987-08-31 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21731187A JPS6459558A (en) 1987-08-31 1987-08-31 Data processing system

Publications (1)

Publication Number Publication Date
JPS6459558A true JPS6459558A (en) 1989-03-07

Family

ID=16702167

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21731187A Pending JPS6459558A (en) 1987-08-31 1987-08-31 Data processing system

Country Status (1)

Country Link
JP (1) JPS6459558A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08166922A (en) * 1994-12-14 1996-06-25 Nec Corp Bus access monitor-type priority controller
US6226702B1 (en) 1998-03-05 2001-05-01 Nec Corporation Bus control apparatus using plural allocation protocols and responsive to device bus request activity
JP2010055389A (en) * 2008-08-28 2010-03-11 Fujitsu Microelectronics Ltd Arbitration device, arbitration method and electronic apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08166922A (en) * 1994-12-14 1996-06-25 Nec Corp Bus access monitor-type priority controller
US6226702B1 (en) 1998-03-05 2001-05-01 Nec Corporation Bus control apparatus using plural allocation protocols and responsive to device bus request activity
JP2010055389A (en) * 2008-08-28 2010-03-11 Fujitsu Microelectronics Ltd Arbitration device, arbitration method and electronic apparatus

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