JPS6458041A - Microcomputer - Google Patents

Abstract

PURPOSE:To increase the processing speed of a microcomputer, by using three system clock signals of different phases. CONSTITUTION:The addresses which are previously outputted to an internal address bus 11 in the timings of timing signals 21 and 22 are outputted to an external address bus 13 at the trailing edge of a timing signal 23. An address output circuit 12 consists of a flip-flop circuit and the delay time 1 of an address set to the trailing edge of the signal 23 is limited only to the delay time of a path reaching an output driver from a flip-flop. For input of data, the data on an external data bus 5 is latched by a data input circuit 6 at the trailing edge of a timing signal 19. Then the latched data is transferred to an internal register 9 via a data bus 8 in the timing of a timing signal 20. Thus the data set-up time 2 set to the trailing edge of the signal 19 is limited only to the delay time produced between the bus 5 and the circuit 6.