JPS6446144A - Performance analyzer processing system - Google Patents
Performance analyzer processing systemInfo
- Publication number
- JPS6446144A JPS6446144A JP62201915A JP20191587A JPS6446144A JP S6446144 A JPS6446144 A JP S6446144A JP 62201915 A JP62201915 A JP 62201915A JP 20191587 A JP20191587 A JP 20191587A JP S6446144 A JPS6446144 A JP S6446144A
- Authority
- JP
- Japan
- Prior art keywords
- unit
- circuit
- processing system
- gate
- plural
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/348—Circuit details, i.e. tracer hardware
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE:To realize high-speed operations with a performance analyzer PA processing system by adding a selection circuit, a master register, a logical gate, a counter, etc., to each PA unit of a PA processing unit so that plural programs are processed at one time through the PA unit processing and no action is inhibited when programs are switched. CONSTITUTION:A PA processing system consists of plural PA units and a selection circuit 1 of each PA unit selects groups D0-D7 of items to be measured and sent from a vector processor, a scalar processor, a channel device, etc. A mask setting command is sent to the circuit 1 from a mask register 2 for selection of events. Then the circuit 1 transmits a signal S0 to be selected. The clear signal S4 of an AND gate 3 and the clear signal S3 of a counter 4 are outputted according to the PA unit control mode which is supplied to a control circuit 5. Then the number of instruction processes that passed through the gate 3 according to enable signals are counted. Thus plural programs are processed at one time.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62201915A JPS6446144A (en) | 1987-08-14 | 1987-08-14 | Performance analyzer processing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62201915A JPS6446144A (en) | 1987-08-14 | 1987-08-14 | Performance analyzer processing system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6446144A true JPS6446144A (en) | 1989-02-20 |
Family
ID=16448911
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62201915A Pending JPS6446144A (en) | 1987-08-14 | 1987-08-14 | Performance analyzer processing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6446144A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0962532A (en) * | 1995-08-29 | 1997-03-07 | Kofu Nippon Denki Kk | Performance measuring counter circuit |
-
1987
- 1987-08-14 JP JP62201915A patent/JPS6446144A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0962532A (en) * | 1995-08-29 | 1997-03-07 | Kofu Nippon Denki Kk | Performance measuring counter circuit |
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