JPS6438671A - Apparatus for testing integrated circuit - Google Patents

Abstract

PURPOSE:To perform the highly accurate test of an integrated circuit memory with respect to a delay time by supporting a wafer-shaped integrated circuit, by utilizing the time difference between both pulses generated by two pulse generators, which generate pulses by an integrated circuit test rate signal, as a tolerant delay time. CONSTITUTION:At first, an integrated circuit tester 1 sends the test rate signal generated in a test rate signal generating circuit 11 to the first and second pulse generators 3, 4 through a signal control circuit 13. The pulse generator 3 generates the first pulse to send the same to the integrated circuit memory 5 supported by a wafer support part 22 through an interface part 21. The pulse generator 4 generates the second pulse delayed by the reading delay time tc permitted to the memory 5 by the first pulse to send the same to the memory 5 through the interface part 21. The circuit 13 investigates whether the read data obtained from the memory 5 is held to a result memory 14 and coincides with a test pattern signal to display the judge result showing the quality of the memory 5.