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JPS6429038A - Scrambler - Google Patents

Scrambler

Info

Publication number
JPS6429038A
JPS6429038A JP62184383A JP18438387A JPS6429038A JP S6429038 A JPS6429038 A JP S6429038A JP 62184383 A JP62184383 A JP 62184383A JP 18438387 A JP18438387 A JP 18438387A JP S6429038 A JPS6429038 A JP S6429038A
Authority
JP
Japan
Prior art keywords
gate
output
inputted
scramble
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62184383A
Other languages
Japanese (ja)
Inventor
Tsutomu Hoshino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62184383A priority Critical patent/JPS6429038A/en
Publication of JPS6429038A publication Critical patent/JPS6429038A/en
Pending legal-status Critical Current

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  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To make a scramble not be dissolved even if the scramble is imposed to the preamble part of data, in an mB1C synchronization system by inverting the data to be inputted to the scrambler of a first stage, when the output data of the respective stage comes to be a specified pattern. CONSTITUTION:The data 100 to be scrambled is inputted to the input terminal I1 of an EXOR gate 6, and besides, the output of a DFF 5 is inputted to the input terminal I3 of the EXOR gate 7, and the output of the OFF 2 is inputted to the input terminal I4 of the same gate. The respective outputs of these gates 6, 7 are outputted as a scramble signal 200 through the EXOR gate 8. In this case, when all the outputs of the DFFs 1-5 come to be 1, the output of an AND gate 9 comes to be 1 and is impressed to the gate 6. Thus, a device returns from a state that 0 appears in the output 200 of the gate 8 and the scramble is dissolved to the state that a random pattern is generated.
JP62184383A 1987-07-23 1987-07-23 Scrambler Pending JPS6429038A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62184383A JPS6429038A (en) 1987-07-23 1987-07-23 Scrambler

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62184383A JPS6429038A (en) 1987-07-23 1987-07-23 Scrambler

Publications (1)

Publication Number Publication Date
JPS6429038A true JPS6429038A (en) 1989-01-31

Family

ID=16152227

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62184383A Pending JPS6429038A (en) 1987-07-23 1987-07-23 Scrambler

Country Status (1)

Country Link
JP (1) JPS6429038A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003037643A (en) * 2001-07-24 2003-02-07 Hitachi Kokusai Electric Inc Digital transmitter, digital receiver, data scramble method, data descramble method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003037643A (en) * 2001-07-24 2003-02-07 Hitachi Kokusai Electric Inc Digital transmitter, digital receiver, data scramble method, data descramble method

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